Thanks!
I need this because I have this cache latency (cycle) configuration:
CPU ------ L1-------L2----------DRAM
10 20 (Hit the L2)
10 29 100 (Miss the L2)
BR,
ALI CHAKER
2012/6/7 Nilay Vaish <ni...@cs.wisc.edu>
> On Thu, 7 Jun 2012, Ali chaker wrote:
>
> Hello,
>>
>> I found that there is only one cache parameter for the latency. Is it
>> possible to configure the memory cache with two different latency values
>> (misslatency and hitlatency)?
>>
>>
> I don't think that is possible as of now. But why do you want to have two
> different latencies?
>
> --
> Nilay
> _______________________________________________
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
_______________________________________________
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
