if I've understood, the cache miss latency is calculated during the
simulation.I've found the following formula for misslatemcy in
cache_impl.hh file:

*completion_time = tags->getHitLatency() +(transfer_offset ?
pkt->finishTime : pkt->firstWordTime);*
*missLatency[target->pkt->cmdToIndex()][target->pkt->req->masterId()]
+= completion_time - target->recvTime;*

I don't understand how the cache miss latency is calculated ? the latency
cache parameter is for cache hit latency or cache miss latency?

Thanks,
Ali Chaker

2012/6/7 Nilay Vaish <ni...@cs.wisc.edu>

> On Thu, 7 Jun 2012, Ali chaker wrote:
>
>  cache hitlatency is the time between sendind address and data returning
>> from cache and cache misslatency is the time between sending address  and
>> data returning from  next-level cache/memory.
>>
>>
> Really!
>
> Think of a three level hierarchy (L1 cache, L2 cache and the memory). If
> the L1 miss latency is a fixed variable, then how will you correctly model
> the latency for the cases when the data is returned from L2 and when the
> data is returned from the memory? Should it really be the same in both the
> cases?
>
>
> --
> Nilay
> ______________________________**_________________
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/**mailman/listinfo/gem5-users<http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users>
>
_______________________________________________
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Reply via email to