On Thu, 7 Jun 2012, Ali chaker wrote:
cache hitlatency is the time between sendind address and data returning
from cache and cache misslatency is the time between sending address and
data returning from next-level cache/memory.
Really!
Think of a three level hierarchy (L1 cache, L2 cache and the memory). If
the L1 miss latency is a fixed variable, then how will you correctly model
the latency for the cases when the data is returned from L2 and when the
data is returned from the memory? Should it really be the same in both the
cases?
--
Nilay
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