Hi, Fernando
Thanks for your advice.
We will try.
Regards,
Zhiguo
From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On
Behalf Of Fernando Endo
Sent: Thursday, March 13, 2014 2:43 AM
To: gem5 users mailing list
Subject: Re: [gem5-users] A question about InOrderCPU model in
Hello,
To simulate a correct execution time, although it's an cycle approximate
in-order simulator, you should do this in the O3 model:
- Patch the O3:
- to issue only the oldest instruction in the IQ, except re-issuing
instructions
- to implement and extra register scoreboard to track regist
ROB not keeping pipeline depth 1 is to resemble more closely intel inorder
atom core. They have dispatch width 2 and issue2 and issue queue entries of
16
This is OOO core. If ROB is not pipeline depth then you can plug in the
above parameters . You can do ROB=1 with issue queue entries to be 1 bu
Hi, Sudarshan
Thanks for your reply.
My concern is the load store queue in O3CPU may cause performance error as
loads and stores are executed out of order which is not the case in InOrder
CPU.
You said that "ROB entries can be made to pipeline depth than keeping it
1". May I know why ROB entry sh
Yes u can do that..ROB entries can be made to pipeline depth than keeping
it 1.if Rob is made to 1 then u can't keep issue width of 2 since Intel
atom inorder processor have fetch and issue width 2.. Intel atom does not
have a load store queue...but load store queue entries could be made to
have sa
