Re: [gem5-users] Simple DRAM not draining when cores do not switch L1's

ng list mailto:gem5-users@gem5.org>> Date: Wednesday, 7 November 2012 12:46 To: gem5 users mailing list mailto:gem5-users@gem5.org>> Subject: Re: [gem5-users] Simple DRAM not draining when cores do not switch L1's Yes. And I hope to add a draining regression soon

Re: [gem5-users] Simple DRAM not draining when cores do not switch L1's

y Gutierrez mailto:atgut...@umich.edu>> > Reply-To: gem5 users mailing list gem5-users@gem5.org>> > Date: Monday, 5 November 2012 21:08 > To: "gem5-users@gem5.org<mailto:gem5-users@gem5.org>" <mailto:gem5-users@gem5.org>> > Subject: Re: [gem5-users] Simple D

Re: [gem5-users] Simple DRAM not draining when cores do not switch L1's

t;gem5-users@gem5.org<mailto:gem5-users@gem5.org>" mailto:gem5-users@gem5.org>> Subject: Re: [gem5-users] Simple DRAM not draining when cores do not switch L1's NOTE, the problem with this trace is that it hangs while trying to drain because the physmem never signals draine

Re: [gem5-users] Simple DRAM not draining when cores do not switch L1's

NOTE, the problem with this trace is that it hangs while trying to drain because the physmem never signals drained; it's dramWriteQueue is never emptied and only refreshes forever. -Tony ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cg

Re: [gem5-users] Simple DRAM not draining when cores do not switch L1's

Hi Andreas, Actually, it appears the simple_dram does not drain properly at all in some cases. You should be able to reproduce this error using a clean checkout (I did add DPRINTFs to simple_dram.cc:drain()) without any modifications; the following command line is what I ran: ./build/ALPHA/m5.opt

Re: [gem5-users] Simple DRAM not draining when cores do not switch L1's

gt;" mailto:gem5-users@gem5.org>> Subject: [gem5-users] Simple DRAM not draining when cores do not switch L1's I have a system that repeatedly switching back and forth between core types; I am trying to evaluate the effects on the caches due to switching. I give each core its own L1

[gem5-users] Simple DRAM not draining when cores do not switch L1's

I have a system that repeatedly switching back and forth between core types; I am trying to evaluate the effects on the caches due to switching. I give each core its own L1 caches and when switching out, it keeps its L1s connected. However, when I upgraded to the latest repo that uses simple DRAM.