I have a system that repeatedly switching back and forth between core
types; I am trying to evaluate the effects on the caches due to switching.
I give each core its own L1 caches and when switching out, it keeps its L1s
connected. However, when I upgraded to the latest repo that uses simple
DRAM. For some reason the configuration is causing the physmem to never
signal drain. Instead, while draining it just continually refreshed. The
caches and all other objects needing to drain signal drain properly. Here
is a DRAM and Drain trace right before it first attempts to drain:
38190278001: system.physmem: Access time is 18001
38190278001: system.physmem: Reached scheduleNextReq()
38190278001: system.physmem: chooseNextReq(): Returning False
38190296001: system.physmem: processRespondEvent(): Some req has reached
its readyTime
38190296001: system.physmem: Responding to Address 11166592.. 38190296001:
system.physmem: Done
38190297500: system.physmem: Inside recvTimingReq: request Writeback addr
11133824 size 64
38190297500: system.physmem: Write queue limit 32 current size 9
38190297500: system.physmem: Address: 11133824 Rank 1 Bank 6 Row 169
38190297500: system.physmem: Adding to write queue
38190297500: system.physmem: Responding to Address 11133824.. 38190297500:
system.physmem: Done
38190382000: system.physmem: Inside recvTimingReq: request ReadExReq addr
11166656 size 64
38190382000: system.physmem: Read queue limit 32 current size 0
38190382000: system.physmem: Address: 11166656 Rank 0 Bank 6 Row 170
38190382000: system.physmem: Adding to read queue
38190382000: system.physmem: Request <extra arg>%ld - need to schedule
immediately38190382001: system.physmem: Reached scheduleNextReq()
38190382001: system.physmem: Timing access to addr 11166656, rank/bank/row
0 6 170
38190382001: system.physmem: Returning 14000 from estimateLatency()
38190382001: system.physmem: Req 11166656: curtick is 38190382001 accessLat
is 14000 readytime is 38190400001 busbusyuntil is 38190296001. Scheduling
at readyTime
38190382001: system.physmem: Access time is 18001
38190382001: system.physmem: Reached scheduleNextReq()
38190382001: system.physmem: chooseNextReq(): Returning False
38190400001: system.physmem: processRespondEvent(): Some req has reached
its readyTime
38190400001: system.physmem: Responding to Address 11166656.. 38190400001:
system.physmem: Done
38190401500: system.physmem: Inside recvTimingReq: request Writeback addr
11133888 size 64
38190401500: system.physmem: Write queue limit 32 current size 10
38190401500: system.physmem: Address: 11133888 Rank 1 Bank 6 Row 169
38190401500: system.physmem: Adding to write queue
38190401500: system.physmem: Responding to Address 11133888.. 38190401500:
system.physmem: Done
38190452000: system.physmem: internal queues not drained
38190452000: system.physmem: not drained
38190452000: system.cpu: CPU not drained
38190452000: system.cpu.icache.cpu_side-CpuSidePort: PacketQueue not drained
38190452000: system.cpu.icache: Cache not drained
38190453000: system.cpu: CPU done draining, processing drain event
38190453000: system.cpu.icache.cpu_side-CpuSidePort: PacketQueue done
draining, processing drain event
38196600000: system.physmem: Refreshing at tick 38196600000
38204400000: system.physmem: Refreshing at tick 38204400000
38212200000: system.physmem: Refreshing at tick 38212200000
38220000000: system.physmem: Refreshing at tick 38220000000
38227800000: system.physmem: Refreshing at tick 38227800000
38235600000: system.physmem: Refreshing at tick 38235600000
38243400000: system.physmem: Refreshing at tick 38243400000
38251200000: system.physmem: Refreshing at tick 38251200000
38259000000: system.physmem: Refreshing at tick 38259000000
38266800000: system.physmem: Refreshing at tick 38266800000
Here is the cache configuration I am using. I am not too familiar with the
DRAM code. Does anyone have any ideas why the drainManger is never being
signaled when I have this setup?
def config_cache(options, system):
if options.l2cache:
# Provide a clock for the L2 and the L1-to-L2 bus here as they
# are not connected using addTwoLevelCacheHierarchy. Use the
# same clock as the CPUs, and set the L1-to-L2 bus width to 32
# bytes (256 bits).
system.l2 = L2Cache(clock=options.clock,
size=options.l2_size,
assoc=options.l2_assoc,
block_size=options.cacheline_size)
system.tol2bus = CoherentBus(clock=options.clock, width=32)
system.l2.cpu_side = system.tol2bus.master
system.l2.mem_side = system.membus.slave
for i in xrange(options.num_cpus):
if options.caches:
icache = L1Cache(size='32kB',
assoc=2,
block_size=options.cacheline_size)
dcache = L1Cache(size='32kB',
assoc=2,
block_size=options.cacheline_size)
# big core's cache
big_icache = L1Cache(size='32kB',#options.big_l1i_size,
assoc=2,
block_size=options.cacheline_size)
big_dcache = L1Cache(size='32kB',#options.big_l1d_size,
assoc=2,
block_size=options.cacheline_size)
# little core's cache
little_icache = L1Cache(size='32kB',#options.little_l1i_size,
assoc=2,
block_size=options.cacheline_size)
little_dcache = L1Cache(size='32kB',#options.little_l1d_size,
assoc=2,
block_size=options.cacheline_size)
# When connecting the caches, the clock is also inherited
# from the CPU in question
system.cpu[i].addPrivateSplitL1Caches(icache, dcache)
system.big_cpu[i].addPrivateSplitL1Caches(big_icache,
big_dcache)
system.little_cpu[i].addPrivateSplitL1Caches(little_icache,
little_dcache)
system.cpu[i].createInterruptController()
if options.l2cache:
system.cpu[i].connectAllPorts(system.membus)
system.big_cpu[i].connectAllPorts(system.tol2bus, system.membus)
system.little_cpu[i].connectAllPorts(system.tol2bus,
system.membus)
else:
system.cpu[i].connectAllPorts(system.membus)
return system
Thanks,
Tony
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