Re: [gem5-users] cache_impl bug

think this is related to a bug in the cache, and I am pretty sure this > patch: http://reviews.gem5.org/r/1294/ will fix it. > > Could you give it a go? > > Andreas > > From: Ali chaker mailto:ali.chaker2...@gmail.com > >> > Reply-To: gem5 users mailing list gem5-use

[gem5-users] cache_impl bug

HI, I'm running bbench in gem5 with 2 cores and I've the following error: gem5.debug: build/ARM/mem/cache/cache_impl.hh:893: void Cache::handleResponse(Packet*) [with TagStore = LRU]: Assertion `pkt->req->masterId() < system->maxMasters()' failed. Program received signal SIGABRT, Aborted. 0x00

[gem5-users] Cycles Statistics ARM FS

s ? Regards, Ali Chaker ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Latency_input ARM FS

d I've the following statistics: > > > > *system.l2.overall_avg_mshr_miss_latency::cpu.data 116713.648032* > > *system.l2.overall_avg_miss_latency::cpu.data 136045.358298* > > * > * > > It seems like hit latency is used in acce

[gem5-users] Latency_input ARM FS

045.358298* * * It seems like hit latency is used in access and response. So * avg_miss_latency*= 15.8**2*+2.5+2(buses latency) +100=136.1? Is it right? Thanks in advance Regards, Ali Chaker ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.o

[gem5-users] IPC_bbench_ARM_FS

the committedOps? What is the difference between (*system.cpu.committedOps* <<< *sim_ops*) and between (*system.cpu.committedInsts <<< sim_insts) *? ** Regards, Ali Chaker ___ gem5-users mailing list gem5-users@gem5.org http:/

[gem5-users] L2_latency and system panic

2cache --cpu-type=arm_detailed -n 4* Thanks in advance Regards, Ali Chaker ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] convertig "cycle" to "ns"

Hi, The latency is mentioned as number of cycles, so can we convert "cycle" to "ns". In another word, if I want to set the L1 latency to 2 cycles @1GHZ and @2GHZ: @1GHZ l1 latency = (1/1,000,000,000)*2 seconds @2GHZ l1 latency = (1/2,000,000,000)*2 seconds Is that r

[gem5-users] cache eviction O3CPU

Hi, I have a question regarding Cache statistics in gem5. Is there any information about cache eviction in the statis.txt gem5 output file? what about system.cpu.icache.writebacks::writebacks and system.cpu.dcache.writebacks::writebacks? Thanks, Ali Chaker

Re: [gem5-users] Cache_Latency_parameter

et->pkt->cmdToIndex()][target->pkt->req->masterId()] += completion_time - target->recvTime;* I don't understand how the cache miss latency is calculated ? the latency cache parameter is for cache hit latency or cache miss latency? Thanks, Ali Chaker 2012/6/7 Nilay Vaish > On

Re: [gem5-users] Cache_Latency_parameter

cache hitlatency is the time between sendind address and data returning from cache and cache misslatency is the time between sending address and data returning from next-level cache/memory. BR, Ali Chaker 2012/6/7 Nilay Vaish > On Thu, 7 Jun 2012, Ali chaker wrote: > > Thanks! >

Re: [gem5-users] Cache_Latency_parameter

Thanks! I need this because I have this cache latency (cycle) configuration: CPU -- L1---L2--DRAM 10 20 (Hit the L2) 10 29100 (Miss the L2) BR, ALI CHAKER 2012/6/7 Nilay Vaish > On Thu, 7 Jun 2012, Ali chaker wr

[gem5-users] Cache_Latency_parameter

Hello, I found that there is only one cache parameter for the latency. Is it possible to configure the memory cache with two different latency values ​​(misslatency and hitlatency)? Thanks & Regards, ALI CHAKER ___ gem5-users mailing list gem5-u

Re: [gem5-users] Cache Miss statistics and CPU MODEL

Thanks for these details. Regards, Ali Chaker 2012/6/1 Jack Harvard > You wouldn't expect the O3CPU and Timing/Atomic to have exactly the same > cache miss rate, for example, when the branch prediction is turned on in > the O3 CPU, the i cache miss rate won't be the sam

[gem5-users] Cache Miss statistics and CPU MODEL

erall accesses system.l2.overall_miss_rate::cpu.data0.126456 # miss rate for overall accesses * *Any help would be appreciated! Thanks! BR, ALI CHAKER ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.or