Re: [gem5-users] modifying Ruby memory model

Thanks, Nilay! So, is Ruby_cycles the total number of cycles for non-memory and memory requests together? And can we add up total memory_total_requests for each individual memory controller and divide it by Ruby_cycles to get memory utilization for the same? Would it be appropriate to calculate me

Re: [gem5-users] I can not understand how does the cpu model work and its work flow..........

I have see that website, but I still can not figure out the underlying work flow. For example, in the AtomicSimpleCPU diagram in the website, I can see the first function is "tick()", but who will call tick() to startup AtomicSimpleCPU ?? I have see several member functions ( e.g. resume(), swit

Re: [gem5-users] could i add a new opcode to source code of benchmark

thank you for reply i have read -- http://gem5.org/M5ops and tutorious many times, but i can't understand how to do it, so i read util/m5/m5op.h, util/m5/m5.c and util/m5/m5op_alpha.S. It seems that have many work to do, it should edit ISA Parser and so on. it's almost impossible for me

Re: [gem5-users] I can not understand how does the cpu model work and its work flow..........

take a look at http://www.m5sim.org/SimpleCPU Amin On Thu, Jun 7, 2012 at 10:31 AM, Jacky Lee wrote: > out how to call these functions, > which will call them, and the order of calling functions. > ___ gem5-users mailing list gem5-users@gem5.org http:

Re: [gem5-users] bzip2 can't run properly in x86 O3 mode

No fast forward and max inst. I compiled the binary in SPEC2006 and I didn't modify the source file. The input is from test input. I have posted the link to download the binary and input I used in my previous email, and I wrote the command I used in my first email. My command line is: build/X86/ge

[gem5-users] I can not understand how does the cpu model work and its work flow..........

Hi everyone: I have studied the cpu model in gem5 long time, but I really don't understand how does the cpu work. For example: I knew the AtomicSimpleCPU has several member functions (e.g. serialize(), unserialize(), resume(), switchOut(), takeOverFrom, etc.), but I can not figure out how to ca

[gem5-users] Stock ICS image and ICS image with BBench released.

Hello fellow gem5 users, I have released a clean/stock version of Android 4.0 Ice Cream Sandwich (ICS) as well as a modified one with BBench and a few extras at: http://gem5.org/BBench-gem5 I have also updated the section on building your own Android disk image and I've added a section describin

Re: [gem5-users] Help Understanding Stats

On Jun 7, 2012, at 4:28 AM, Ira Ray Jenkins wrote: > I've completed a few benchmark runs, and in looking at the stats I'm a > little confused. Specifically regarding the translation buffers... The > dtb is the "data", and the "itb" is the instruction, correct? Why then > do the comments on many o

Re: [gem5-users] Cache_Latency_parameter

On Thu, 7 Jun 2012, Ali chaker wrote: cache hitlatency is the time between sendind address and data returning from cache and cache misslatency is the time between sending address and data returning from next-level cache/memory. Really! Think of a three level hierarchy (L1 cache, L2 cache a

Re: [gem5-users] Cache_Latency_parameter

cache hitlatency is the time between sendind address and data returning from cache and cache misslatency is the time between sending address and data returning from next-level cache/memory. BR, Ali Chaker 2012/6/7 Nilay Vaish > On Thu, 7 Jun 2012, Ali chaker wrote: > > Thanks! >> >> I need th

Re: [gem5-users] Cache_Latency_parameter

On Thu, 7 Jun 2012, Ali chaker wrote: Thanks! I need this because I have this cache latency (cycle) configuration: CPU -- L1---L2--DRAM 10 20 (Hit the L2) 10 29100 (Miss the L2) BR, ALI CHAKER 2012/6/7 Nilay Vaish On Th

Re: [gem5-users] could i add a new opcode to source code of benchmark

On Thu, 7 Jun 2012, xuxin wrote: Dear all I'm sorry to bother you. I read tutorials and find special opcodes in M5 is very useful. I want to insert a new operation into the source codejust for notifying each CPU how many times this operation does. 1. is that practical in gem5 ? 2. if it's p

Re: [gem5-users] Cache_Latency_parameter

Thanks! I need this because I have this cache latency (cycle) configuration: CPU -- L1---L2--DRAM 10 20 (Hit the L2) 10 29100 (Miss the L2) BR, ALI CHAKER 2012/6/7 Nilay Vaish > On Thu, 7 Jun 2012, Ali chaker wrote: > >

Re: [gem5-users] Cache_Latency_parameter

On Thu, 7 Jun 2012, Ali chaker wrote: Hello, I found that there is only one cache parameter for the latency. Is it possible to configure the memory cache with two different latency values ??(misslatency and hitlatency)? I don't think that is possible as of now. But why do you want to hav

Re: [gem5-users] modifying Ruby memory model

On Wed, 6 Jun 2012, tejasi pimpalkhute wrote: Hi Nilay, I want to dump the statistics for memory utilization ( number of clock cycles used for data transfer divided by the number of total clock cycles). Could you please let me know where can I a register for this so that I can have the values i

[gem5-users] Cache_Latency_parameter

Hello, I found that there is only one cache parameter for the latency. Is it possible to configure the memory cache with two different latency values ​​(misslatency and hitlatency)? Thanks & Regards, ALI CHAKER ___ gem5-users mailing list gem5-users@ge

[gem5-users] Help Understanding Stats

I've completed a few benchmark runs, and in looking at the stats I'm a little confused. Specifically regarding the translation buffers... The dtb is the "data", and the "itb" is the instruction, correct? Why then do the comments on many of the "itb" lines says "DTB"? Is this a copy/past mistake or

[gem5-users] could i add a new opcode to source code of benchmark

Dear all I'm sorry to bother you. I read tutorials and find special opcodes in M5 is very useful. I want to insert a new operation into the source codejust for notifying each CPU how many times this operation does. 1. is that practical in gem5 ? 2. if it's possible, how to do it ? Best Re