Re: [PATCH] Make __ibm128 a distinct type, patch 2 of 2 (PR 85657)

bootstrap and regression test (with the previous patch also applied). Can I check this into the trunk and the GCC 8 branch? [gcc] 2018-05-18 Michael Meissner PR target/85657 * config/rs6000/rs6000-builtin.def (BU_IBM128_2): New helper macro for __builtin_{,un}pack_ibm128

Re: [PATCH] Make __ibm128 a distinct type, patch 2 of 2 (PR 85657)

Evidently I forgot the patch. [gcc] 2018-05-21 Michael Meissner PR target/85657 * config/rs6000/rs6000-builtin.def (BU_IBM128_2): New helper macro for __builtin_{,un}pack_ibm128. (PACK_IF): Declare __builtin_{,un}pack_ibm128. (UNPACK_IF): Likewise

[PATCH] PR target/85358: Add target hook to prevent default widening

d people prefer modifications to the patch? [gcc] 2018-05-22 Michael Meissner PR target/85358 * target.def (default_widening_p): New target hook to say whether default widening between modes should be done. * targhooks.h (hook_bool_mode_mode_bool_true):

Re: [PATCH] PR target/85358: Add target hook to prevent default widening

rs is the assumption that there is only one type for a given size, and that isn't true for IF/KF/TFmode. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797

Update svn.html documentation

! development, prior to the patches being submitted to the mainline. ! The branch is maintained by Michael Meissner, ! mailto:meiss...@linux.vnet.ibm.com";>meiss...@linux.vnet.ibm.com. linaro/gcc-x_y-branch Linaro compilers based on GCC x.y releases. These branches -

Re: [PATCH] PR target/85358: Add target hook to prevent default widening

need to be changed to include the new type of mode > as well. Yes. I think trying to change it to a non-scalar composite mode would likely be much more work. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797

[PATCH], rs6000 cleanup, make constraints tighter

since there are various failures due to memory allocation in the trunk when I tested it (bugzilla 61950). Are these patches ok to be installed in the trunk? I would like to install them in 4.9 and 4.8 trees as well. 2014-08-07 Michael Meissner * config/rs6000/constraints.md (wh c

Re: [PATCH], rs6000 cleanup, make constraints tighter

onstraint wm Carrot used with wi, since wi is now the constraint to use for DImode in FP/VSX registers. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797

Re: [PATCH], rs6000 cleanup, make constraints tighter

This is the patch I checked in as subversion id 213834. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797 Index: gcc/config/rs6000/constraints.md

[PATCH], Fix error in powerpc bootstrap

There was some code in the rs6000.c that new warnings prevented the powerpc compiler from bootstraping. I fixed it under the 'obvious' rule, after doing a bootstrap with the change: 2014-08-21 Michael Meissner * config/rs6000/rs6000.c (print_operand, 'y'

[PATCH, rs6000] PR 62195, Fix wi constraint

the patch ok to check in? 2014-08-21 Michael Meissner PR target/62195 * doc/md.texi (Machine Constraints): Update PowerPC wi constraint documentation to state it is only for VSX operations. * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Make wi

[PATCH], PR target/59054, powerpc code regression for power7/power8

ewise. (cmp_fpr): Do not use %x for CR register output. (extendsfdf2_fpr): Fix constraints when -mallow-upper-df and -mallow-upper-sf debug switches are used. [gcc/testsuite] 2013-11-11 Michael Meissner PR target/59054 * gcc.target/powerpc/pr59054.c: New

Re: [PATCH], PR target/59054, powerpc code regression for power7/power8

On Mon, Nov 11, 2013 at 04:45:36PM -0500, Michael Meissner wrote: > [gcc] > 2013-11-11 Michael Meissner > > PR target/59054 > * config/rs6000/rs6000.md (movdi_internal32): Eliminate > constraints that would allow DImode into the traditional Altivec >

Revert libsanitizer patches or fix 59009

the release criteria.) After the patch has been reverted, the poster may appeal the decision to the Steering Committee. Note that no distinction is made between patches which are themselves buggy and patches that expose latent bugs elsewhere in the compiler. -- Michael Meissner, IBM IBM, M/S

Re: Revert libsanitizer patches or fix 59009

people to enable it. It should only be default on x86_64 until people are motivated to fix libsantizer on all instances of the platform. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460, USA email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797

Re: Revert libsanitizer patches or fix 59009

On Tue, Nov 12, 2013 at 10:07:32AM -0800, Kostya Serebryany wrote: > On Tue, Nov 12, 2013 at 10:04 AM, Michael Meissner > wrote: > > On Tue, Nov 12, 2013 at 09:43:38AM -0800, Kostya Serebryany wrote: > >> or, alternatively, we can disable libsanitizer on PowerPC if the > &

Re: Revert libsanitizer patches or fix 59009

you will have a good internet connection where you are going, and you will have enough cycles to spare from your travels to fix any fall out. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460, USA email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797

Re: Revert libsanitizer patches or fix 59009

ompile farm for a reason. Use it to test system dependent changes before committing them to the trunk. I have too much on my plate that I'm scrambling to get my changes done before stage1 closes. I don't have time or engery to fix code that other people broke. I'm sorry, but I'

[PATCH] Fix various power8 tests that I wrote

duplicated. These changes cause all of these tests to now pass. Are they ok to check in? 2013-11-21 Michael Meissner PR target/59054 * gcc.target/powerpc/direct-move.h (VSX_REG_ATTR): Allow test to specify an appropriate register class for VSX operations. (load_vsx

Re: [PATCH] Fix various power8 tests that I wrote

440-dlmzb-strlen-1.c 32-bit fail gcc.target/powerpc/ppc-vector-memcpy.c 64-bit & 32-bit fail -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460, USA email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797

Re: New rematerialization sub-pass in LRA

r options (location of loops in memory, etc.), but other than that there is no real difference in using the current reload, the current LRA, and the new patches. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797

Re: __float128 typeinfo

lex128; It would be nice to have a standard name for IEEE 128-bit floating point, whether it is a defacto standard like __float128, or something in future standards like _Float128. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797

[PATCH], PowerPC PR 61431, Fix little endian word swapping for 128-bit types

128-2.c now passes on the little endian power8 with this fix. Are these patches ok to check into the trunk, and 4.9/4.8 branches? 2014-06-06 Michael Meissner PR target/61431 * config/rs6000/vsx.md (VSX_LE): Split VSX_D into 2 separate iterators, VSX_D that handles 6

Re: [PATCH] Add SPECIAL_FLOAT_MODE to enable adding IEEE 128-bit floating point to PowerPC

On Fri, May 08, 2015 at 01:05:59PM -0600, Jeff Law wrote: > On 05/06/2015 11:29 AM, Michael Meissner wrote: > >On Wed, May 06, 2015 at 04:03:00PM +0100, Richard Sandiford wrote: > >>Jeff Law writes: > >>>So my worry here is that folks writing these loops to iterat

[PATCH], Add IEEE 128-bit floating point to PowerPC, patch #1

patches ok to install in the trunk? 2015-05-22 Michael Meissner * config/rs6000/rs6000-modes.def (IFmode): Define IFmode to provide access to the IBM extended double floating point mode if long double is IEEE 128-bit floating point. (KFmode): Define KFmode to

Re: [PATCH], Add IEEE 128-bit floating point to PowerPC, patch #1

. I can remove the lines and do the build again, if you would prefer. I don't think it is strictly necessary. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797

Re: [PATCH], Add IEEE 128-bit floating point to PowerPC, patch #1

o make further modifications. However, in order for the glibc people to start, I need the basic support in the compiler in the tree. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797

Re: [PATCH], Add IEEE 128-bit floating point to PowerPC, patch #1

On Tue, Jun 02, 2015 at 08:14:12PM +, Joseph Myers wrote: > On Tue, 2 Jun 2015, Michael Meissner wrote: > > > On Tue, Jun 02, 2015 at 05:55:10PM +, Joseph Myers wrote: > > > Is the use of FRACTIONAL_FLOAT_MODE to avoid iterations over > > > floating-point mo

[PATCH], Add support for --with-advance-toolchain= to PowerPC

patch to the active branches (4.9 and 5). Is this patch acceptable to commit to the trunk and to the branches? 2015-06-02 Michael Meissner * config.gcc (powerpc*-*-*): Add support for a new configure option --with-advance-toolchain= which overrides using the default hea

Re: [PATCH], Add support for --with-advance-toolchain= to PowerPC

On Wed, Jun 03, 2015 at 12:05:36AM +, Joseph Myers wrote: > On Tue, 2 Jun 2015, Michael Meissner wrote: > > > * config.gcc (powerpc*-*-*): Add support for a new configure > > option --with-advance-toolchain= which overrides using the > > default header file

[PATCH] PR target/65849 -- Add additional options to powerpc #pragma/attribute target support

4.8, maybe 4.7). Is this ok? [gcc] 2015-04-23 Michael Meissner PR target/65849 * config/rs6000/rs6000.opt (-mvsx-align-128): Make options that save to independent variables use the Save attribute. This will allow these options to be modified with the #pragma

[PATCH] Add SPECIAL_FLOAT_MODE to enable adding IEEE 128-bit floating point to PowerPC

ating point mode. I found some of the GET_MODE_WIDER_MODE loops needed to add a check for running out of modes if the mode type was special. For those loops, I added a test for mode not being VOIDmode. 2015-05-05 Michael Meissner * machmode.h (GET_MODE_WIDER_MODE_SPECIAL): New macro t

Re: [PATCH] Add SPECIAL_FLOAT_MODE to enable adding IEEE 128-bit floating point to PowerPC

r.c the function init_expr_target uses it to set up the conversion tables. Perhaps it is simpler just to have a target hook that says whether a given conversion can happen automatically (as opposed to explicitly if asked for by the user). -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797

Re: [PATCH] Add SPECIAL_FLOAT_MODE to enable adding IEEE 128-bit floating point to PowerPC

On Wed, May 06, 2015 at 03:27:48PM +, Joseph Myers wrote: > On Tue, 5 May 2015, Michael Meissner wrote: > > > The problem is the PowerPC will have 2 128-bit floating point types, one > > using > > the IBM double-double format (a pair of doubles to give the user mor

Re: PATCH [8 of 8], rs6000, add support for scalar floating point in Altivec registers

lines in rs6000-cpu.def that sets the default. 2014-11-14 Michael Meissner * config/rs6000/predicates.md (memory_fp_constant): New predicate to return true if the operand is a floating point constant that must be put into the constant pool, before register allocation

Re: PATCH, PR 63965, rs6000, add support for scalar floating point in Altivec registers

), power8 systems (default cpu = power8 and power5). The compilers bootstrap and do not have regressions. Are the patches ok to install? 2014-11-20 Michael Meissner PR target/63965 * config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Do not set Altivec & -16 mas

[PATCH], PR 64019, fix power7/power8 regression

eventually generates the lfd instruction with an offset instead of an lxsdx. I have bootstraped these patches on big endian power7, big endian power8, and little endian power8 systems, and there were no regressions. Is the patch ok to install? [gcc] 2014-12-01 Michael Meissner PR ta

[PATCH] PR 65138, Fix PowerPC little endian -flto bugs

the run. Is it ok to install in the trunk and to back port to GCC 4.9 (and GCC 4.8 if it is still active)? 2015-03-02 Michael Meissner PR 65138/target * config/rs6000/rs6000-cpus.def (powerpc64le): Add new generic processor type for 64-bit little endian PowerPC

[PATCH] PR 65138, Fix PowerPC little endian -flto bugs, GCC 4.9 backport

-bit Linux systems. These patches passed bootstrap (for C/C++) and there were no tests that failed due to the use of -flto. I'll check these patches in on January 4th, unless there is an objection. [branches/gcc-4_9-patch/gcc] 2015-03-03 Michael Meissner Backport from trunk

Re: [PATCH] PR target/65240, Fix Power{7,8} insn constraint issue with -O3 -ffast-math

On Fri, Mar 06, 2015 at 01:05:31PM +0100, Richard Biener wrote: > On Thu, Mar 5, 2015 at 9:06 PM, Michael Meissner > wrote: > > This patch fixes PR 65240, which was a latent bug that was introduced when I > > added the -mupper-regs support to the PowerPC compiler. In the PowerP

[PATCH] PR target/65242, Fix powerpc abort in gen_add2_insn

system, and there were no regressions. Is the patch ok to apply? I do not believe it needs to be back ported to GCC 4.9 since the -mupper-regs changes are not installed currently on that branch. [gcc] 2015-03-09 Michael Meissner PR target/65242 * config/rs6000/rs6000.c

Re: [PATCH] PR target/65240, Fix Power{7,8} insn constraint issue with -O3 -ffast-math

On Wed, Mar 11, 2015 at 01:02:06PM -0400, David Edelsohn wrote: > I am concerned with the create_TOC_reference use for TARGET_TOC. Has > this been tested with big endian -mcmodel=small? Yes, that was a problem. Patch coming up soon. Thanks. -- Michael Meissner, IBM IBM, M/S 2506R, 55

Re: [PATCH] PR target/65240, Fix Power{7,8} insn constraint issue with -O3 -ffast-math

On Wed, Mar 11, 2015 at 08:52:54PM -0400, David Edelsohn wrote: > On Wed, Mar 11, 2015 at 6:21 PM, Michael Meissner > wrote: > > On Wed, Mar 11, 2015 at 01:02:06PM -0400, David Edelsohn wrote: > >> I am concerned with the create_TOC_reference use for TARGET_TOC. Has >

Re: [PATCH] PR target/65240, Fix Power{7,8} insn constraint issue with -O3 -ffast-math

with fusion, and I believe it will reduce the life time for some of these address temporaries. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797

[PATCH], PR 65569, Fix powerpc long double regression PF 65240 caused

uming that the last two spec runs build without errors, can I apply the patch? 2015-03-25 Michael Meissner PR target/65569 * config/rs6000/rs6000.md (extenddftf2_fprs): On VSX systems use XXLXOR to create 0.0. On pre-VSX systems make sure the constant 0.0 is corre

Re: [RS6000] Fix 65576 regression

be either "j" or "E". If you are doing a double->long double conversion, and it happens to pick GPRs for some reason, the GPR side will do a load/move of 0.0 instead of using li to load 0 on pre-VSX systems. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797

[PATCH], PR target/65614, Prefer to use LFD on powerpc for constants

-mlra and upper register support. Is the patch ok to commit to trunk? [gcc] 2015-04-03 Michael Meissner PR target/65614 * config/rs6000/rs6000.c (rs6000_rtx_costs): Make FLOAT_EXTEND more expensive, so that LFD is used to load double constants, and not LFS

Re: [Bug target/65614] [5 Regression] PowerPC VSX systems should use XSCPSGNDP to copy scalar fp data to/from Altivec registers

ch to fix the problem > > The FLOAT_EXTEND cost should be based on the processor tuning, not the ISA. This patch moves the decision to the cost structure based on the processor tuning. Is it ok to install? [gcc] 2015-04-06 Michael Meissner PR target/65614 * con

Re: [Bug target/65614] [5 Regression] PowerPC VSX systems should use XSCPSGNDP to copy scalar fp data to/from Altivec registers

ed the values for the other insns. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797

[PATCH] PR 66474, Document using %x for VSX registers on PowerPC

A user pointed out that we never documented the requirement to use %x in the ouptut template when VSX registers are used. This patch adds the necessary documentation. Is it ok to install in the trunk and the open release branches? 2015-06-09 Michael Meissner PR target/66474

Re: [PATCH] PR 66474, Document using %x for VSX registers on PowerPC

On Tue, Jun 09, 2015 at 02:17:19PM -0500, Segher Boessenkool wrote: > On Tue, Jun 09, 2015 at 02:00:48PM -0400, Michael Meissner wrote: > > +asm ("xvadddp %x0,%x1,%x2" "=wa" (v1) : "wa" (v2), "wa" (v3)); > > A colon went missing?

Re: [PATCH] PR 66474, Document using %x for VSX registers on PowerPC

On Tue, Jun 09, 2015 at 08:28:35PM -0400, David Edelsohn wrote: > On Tue, Jun 9, 2015 at 3:26 PM, Michael Meissner > wrote: > > On Tue, Jun 09, 2015 at 02:17:19PM -0500, Segher Boessenkool wrote: > >> On Tue, Jun 09, 2015 at 02:00:48PM -0400, Michael Meissner wrote: > >

[PATCH], Add IEEE 128-bit floating point to PowerPC, patch #2

patches on a big endian power7 and a little endian power8 with no regressions. Are these patches ok to install in the trunk? 2015-06-16 Michael Meissner * config/rs6000/rs6000-protos.h (rs6000_secondary_reload_memory): Use machine mode, not enum machine_mode in the prototype

Re: [PATCH], Add IEEE 128-bit floating point to PowerPC, patch #2b

07-08 Michael Meissner * config/rs6000/rs6000-protos.h (rs6000_secondary_reload_memory): Use machine mode, not enum machine_mode in the prototype. * config/rs6000/rs6000.h (FLOAT128_IEEE_P): New helper macros to classify 128-bit floating point su

[PATCH], PR target/64205, Fix -mcpu=G5 breakage on PowerPC

02-06 Michael Meissner PR target/64205 * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Do not add a general secondary reload handler for SDmode, unless we have both read/write support for SDmode. [gcc/testsuite] 2015-02-06 Michael Meissner

Re: [PATCH 10/11][RS6000] Migrate reduction optabs to reduc_..._scal

2x 0,0,9 addi 9,9,16 lxvd2x 12,0,10 xvadddp 12,12,0 stxvd2x 12,0,10 bdnz .L2 lfd 0,-16(1) xxpermdi 1,12,12,2 fadd 1,0,1 blr .long 0 It is unacceptable to have to do the inner loop doing a load, vector add, and store in the loop. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797

PATCH [intro], rs6000, add support for scalar floating point in Altivec registers

um speeds up, as it doesn't generate the new instructions. I would like to also figure out why bwaves/cactusADM slow down. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797

Re: PATCH [patch 1 of 7], rs6000, add support for scalar floating point in Altivec registers

bootstraps again: 2014-11-11 Michael Meissner * config/rs6000/predicates.md (easy_fp_constant): Delete redunant tests for 0.0. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797

Re: PATCH [2 of 7], rs6000, add support for scalar floating point in Altivec registers

Michael Meissner * config/rs6000/vector.md (VEC_R): Move secondary reload support insns to rs6000.md from vector.md. (reload___store): Likewise. (reload___load): Likewise. (vec_reload_and_plus_): Likewise. * config/rs6000/rs6000.md (RELOAD): New

Re: PATCH [3 of 7], rs6000, add support for scalar floating point in Altivec registers

n when the PowerPC bootstraps? I also fixed up the tests that were affected by these changes. [gcc, patch] 2014-11-11 Michael Meissner * config/rs6000/vsx.md (vsx_float2): Only provide the vector forms of the instructions. Move VSX scalar forms to rs6000.md, and add s

Re: PATCH [4 of 7], rs6000, add support for scalar floating point in Altivec registers

. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797 Index: gcc/config/rs6000/rs6000.c === --- gcc/config/rs6000/rs6000.c (revision 217376

Re: PATCH [5 of 7], rs6000, add support for scalar floating point in Altivec registers

patches and make sure there are no regressions. Is this patch ok to check in? 2014-11-11 Michael Meissner Ulrich Weigand * config/rs6000/rs6000.c (rs6000_secondary_reload_toc_costs): Helper function to identify costs of a TOC load for secondary

Re: PATCH [6 of 7], rs6000, add support for scalar floating point in Altivec registers

. * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mupper-regs-{sf,df}. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797 Index: gcc/config/rs6000/rs6000.opt

Re: PATCH [7 of 7], rs6000, add support for scalar floating point in Altivec registers

some time (this test was a preliminary test for the upper regs support). Assuming the previous patches are checked in, is this patch ok to install? 2014-11-11 Michael Meissner * gcc.target/powerpc/p8vector-ldst.c: Rewrite to use 40 live floating point variables instead of using

Re: [PATCH 10/11][RS6000] Migrate reduction optabs to reduc_..._scal

On Tue, Nov 11, 2014 at 01:10:01AM -0600, Segher Boessenkool wrote: > On Mon, Nov 10, 2014 at 05:36:24PM -0500, Michael Meissner wrote: > > However, the double pattern is completely broken. This cannot go in. > > [snip] > > > It is unacceptable to have to do the inner l

Re: [PATCH 10/11][RS6000] Migrate reduction optabs to reduc_..._scal

On Wed, Nov 12, 2014 at 03:26:35AM -0600, Segher Boessenkool wrote: > On Tue, Nov 11, 2014 at 08:27:22PM -0500, Michael Meissner wrote: > > > Before the patch, the final reduction used *vsx_reduc_splus_v2df; after > > > the patch, it is *vsx_reduc_plus_v2df_scalar. The

Re: [PATCH] rs6000: Add undocumented switch -mprefixed-addr

{ "power9-vector", OPTION_MASK_P9_VECTOR, false, > >> true }, > >>{ "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, > >> true }, > >>{ "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, > >> true }, > >> + { "prefixed-addr", OPTION_MASK_PREFIXED_ADDR, false, > >> true }, > > Do we want this? Why? > > Performance folks are using it for testing purposes.  Eventually this > will probably drop out, but for now I think it's best to have the > undocumented switch. I use that table with -mdebug=reg so I can make sure exactly what options are on or off. Please add any undocumented switch to the table. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797

Re: [PATCH] rs6000: Add basic support for prefixed and PC-relative addresses

I have rewritten this section. In particular rather than basing everything off of the mode, I have a now have a more targeted approach that knows which register, mode, and with sign extension requires D/DS/DQ addresses. Of course this only works after register allocation. Before register allocat

[PATCH] Disable PowerPC pc-relative support until the code is checked in

like other options (i.e. if you do -mpcrel, it also enables -mcpu=target and -mprefixed-addr). Can I check these patches into the trunk? [gcc] 2019-06-06 Michael Meissner * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Delete enabling -mprefixed-addr and -mpcrel

Re: [PATCH] Disable PowerPC pc-relative support until the code is checked in

On Thu, Jun 06, 2019 at 06:14:29PM -0500, Segher Boessenkool wrote: > Hi Mike, > > On Thu, Jun 06, 2019 at 06:42:16PM -0400, Michael Meissner wrote: > > 2019-06-06 Michael Meissner > > > > * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Delete >

[PATCH, v2] Disable PowerPC pc-relative support until the code is checked in

-mcpu=future is done first. Then test if -mprefixed-addr is on for -mpcrel. (rs6000_disable_incompatible_switches): Add -mcpu=future support. [gcc/testsuite] 2019-06-07 Michael Meissner * gcc.target/powerpc/localentry-1.c: Add -mpcrel option. * gcc.target/powerpc

[PATCH], PowerPC PR90822 (cleanup lfiwax, lfiwzx generation)

was more mtvsrwz mtvsrwa instructions. The 64-bit code is more similar, but I notice that we aren't generating as many mtvsrd instructions, but instead generating mtvsrwa and mtvsrwd instructions. Can I check this into the trunk? [gcc] 2019-06-14 Michael Meissner PR target/

[PATCH] PowerPC: Add 'prefix' to the 'isa' attribute

27; target. I have bootstrapped the compiler and run make check with no regressions. Can I check this into the trunk? 2019-06-17 Michael Meissner * config/rs6000/rs6000.md (isa attribute): Add support for prefixed instructions. Index: gcc/config/rs6000

Re: [PATCH], PowerPC PR90822 (cleanup lfiwax, lfiwzx generation)

On Tue, Jun 18, 2019 at 06:37:54AM -0500, Segher Boessenkool wrote: > On Mon, Jun 17, 2019 at 05:24:37PM -0400, Michael Meissner wrote: > > I wrote the code to generate LFIWAX and LFIWZX originally for the power7 in > > the > > 2010 time frame. At the time, we did not al

[PATCH, v2] PowerPC: Add 'prefix' to the 'isa' attribute

On Tue, Jun 18, 2019 at 07:13:22AM -0500, Segher Boessenkool wrote: > On Mon, Jun 17, 2019 at 08:04:42PM -0400, Michael Meissner wrote: > > --- gcc/config/rs6000/rs6000.md (revision 272270) > > +++ gcc/config/rs6000/rs6000.md (working copy) > > @@ -267,7 +267,9

[PATCH], PowerPC #11, Add DS offset mode to rs6000.c's reg_addr

mask != 0) && !indexed_only_p + && msize >= 16 && rc == RELOAD_REG_GPR) { addr_mask |= RELOAD_REG_OFFSET; - if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) + if (TARGET_QUAD_MEMORY) addr_mask |= RELOAD

[PATCH], PowerPC #12, Add instruction format enumeration

s have not yet been written, but I expect them to be: * Patch 21 finish prefixed insn support for vectors & 128-bit int/floats * Patch 22 enable pc-relative by default * Patch 23 add pcrel linker optimization * Patch 24 new tests 2019-07-24 Michael Meissner * config/rs6000/

[PATCH], PowerPC #13, Add support for matching prefixed insns

tch 21 finish prefixed insn support for vectors & 128-bit int/floats * Patch 22 enable pc-relative by default * Patch 23 add pcrel linker optimization * Patch 24 new tests 2019-07-24 Michael Meissner * config/rs6000/predicates.md (lwa_operand): If we have prefixed addr

[PATCH], PowerPC #14, Add pc-relative support to load up addresses

22 enable pc-relative by default * Patch 23 add pcrel linker optimization * Patch 24 new tests 2019-07-24 Michael Meissner * config/rs6000/rs6000.c (rs6000_emit_move): Add support to load up addresses if we have pc-relative support. * config/rs6000

[PATCH], PowerPC #15, Rename some prefixed addressing functions

test suite. Can I check this into the FSF trunk? 2019-07-25 Michael Meissner * config/rs6000/predicates.md (prefixed_mem_operand): Rename rs6000_prefixed_address_mode_p to prefixed_addr_mode_p. * config/rs6000/rs6000-protos.h (prefixed_addr_mode_p): Rename from

[PATCH], PowerPC #16, Update a comment and move a predicate

* Patch 22 enable pc-relative by default * Patch 23 add pcrel linker optimization * Patch 24 new tests 2019-07-25 Michael Meissner * config/rs6000/predicates.md (pcrel_external_address): Update comment. (prefixed_mem_operand): Move lower in the file so the pcrel_*

[PATCH], PowerPC #17, adds the prefixed RTL attribute & automatically emit a leading 'p'

d make check. Assuming there are no regressions, can I check this into the FSF trunk? 2019-07-25 Michael Meissner * config/rs6000/rs6000-prefixed.c: New file. * config/rs6000/rs6000-protos.h (prefixed_addr_reg_p): Add declaration. (prefixed_load_p): Add decl

[PATCH], PowerPC #18, Add prefixed support for scalars

hem to be: * Patch 21 finish prefixed insn support for vectors & 128-bit int/floats * Patch 22 enable pc-relative by default * Patch 23 add pcrel linker optimization * Patch 24 new tests 2019-07-25 Michael Meissner * config/rs6000/predicates.md (add_operand): Add support for

[PATCH], PowerPC #19, Add 'future' cost structure

ure.md. The following patches have not yet been written, but I expect them to be: * Patch 21 finish prefixed insn support for vectors & 128-bit int/floats * Patch 22 enable pc-relative by default * Patch 23 add pcrel linker optimization * Patch 24 new tests 2019-07-25 Michael Meissner

[PATCH], PowerPC #20, Add placeholder for 'future' scheduling

support for vectors & 128-bit int/floats * Patch 22 enable pc-relative by default * Patch 23 add pcrel linker optimization * Patch 24 new tests 2019-07-25 Michael Meissner * config/rs6000/future.md: New file, clone from power9.md and change cpu=future. Place holder unt

[PATCH, committed] Fix comment about pcrel_external_address

I committed this patch as 'obvious'. As I'm preparing the next round of future PowerPC patches, I noticed I had a typo in the usage for the predicate pcrel_external_address. 2019-08-01 Michael Meissner * config/rs6000/predicates.md (pcrel_external_address): Update

[PATCH], Add future cost placeholder to PowerPC

check this into the FSF trunk? 2019-08-01 Michael Meissner * config/rs6000/rs6000.c (future_cost): Add separate cost structure for a 'future' machine. (rs6000_option_override_internal): If -mcpu=future, use the future costs instead of power9. Index:

[PATCH] Add future.md placeholder to PowerPC

is into the FSF branch? 2019-08-01 Michael Meissner * config/rs6000/future.md: New file. * config/rs6000/rs6000.md (top level): Include future.md. * config/rs6000/t-rs6000 (MD_INCLUDES): Add future.md Index: gcc/config/r

Re: [PATCH], Add future cost placeholder to PowerPC

On Thu, Aug 01, 2019 at 04:26:11PM -0500, Segher Boessenkool wrote: > On Thu, Aug 01, 2019 at 03:47:56PM -0400, Michael Meissner wrote: > > Add future_cost placeholder. > > > > Currently, the -mcpu=future uses the power9 costs. This patch separates out > > the cost

Re: [PATCH] Add future.md placeholder to PowerPC

Whoops, I forgot to include the ChangeLog entry when I committed subversion id 274030 to add future.md. I just added it in subversion id 274129. 2019-08-02 Michael Meissner * config/rs6000/future.md: New file. * config/rs6000/rs6000.md: Include future.md. * config

PowerPC 'future' patches introduction

ogram in some cases. The eighth, ninth, and tenth passes adds tests for the 'future' machine to the testsuite. After these patches are installed, Alan Modra will have a set of patches update the thread local storage (TLS) for use with pc-relative addressing. -- Michael Meissner, IBM IB

[PATCH], Patch #1 of 10, Add instruction format enumeration

ormat used was DS format instead of D format for the scalar values. If the register is a pseudo register, the function returns the default instruction format. This function will primarily be used in the next patch to identify whether an insn uses a prefixed instruction or not. 2019-08-14 Mi

[PATCH], Patch #2 of 10, Add RTL prefixed attribute

he insn and not the operands directly. Most of the new code is in a new file (rs6000-prefixed.c). 2019-08-14 Michael Meissner * config/rs6000/rs6000-prefixed.c: New file. * config/rs6000/rs6000-protos.h (rs6000_final_prescan_insn): Update calling signature. (pr

[PATCH], Patch #3 of 10, Add prefixed addressing support

-14 Michael Meissner * config/rs6000/predicates.md (add_operand): Add support for the PADDI instruction. (non_add_cint_operand): Add support for the PADDI instruction. (lwa_operand): Add support for the prefixed PLWA instruction. * config/rs6000/rs6000.c

[PATCH], Patch #4 of 10, Adjust costs based on insn sizes

patches have been bootstrapped on a little endian power8 system in progression, and there were no regressions. Once the previous patches have been checked in, can I check this patch into the trunk? 2019-08-14 Michael Meissner * config/rs6000/rs6000.c (rs6000_num_insns): New function

[PATCH], Patch #5 of 10, Make -mpcrel default for -mcpu=future

are checked in? 2019-08-14 Michael Meissner * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Enable pc-relative support by default on 'future' systems. Index: gcc/config/rs6000/rs6000-cpus.def =

[PATCH], Patch #6 of 10, Add 'future' support to function attributes

;future") I have built each of the patches on a little endian power8 system and there were no regressions in either the bootstrap or make check operations. Can I check this patch into the trunk after the other patches have been checked in? [gcc] 2019-08-14 Michael Meissner *

[PATCH], Patch #7 of 10, Add support for PCREL_OPT

e endian power8 system and there were no regressions. Once the previous patches are checked in, can I check this patch into the trunk? [gcc] 2019-08-14 Michael Meissner * config/rs6000/pcrel.md: New file. * config/rs6000/predicates.md (one_reg_memory_operand): New predicate.

[PATCH], Patch #8 of 10, Miscellaneous future tests

This patch adds miscellaneous tests for the new prefixed addressing. With patches 1-7 applied, these patches all succeed. Can I check these patches into the trunk? 2019-08-14 Michael Meissner * gcc/testsuite/gcc.target/powerpc/prefix-odd-memory.c: New test. * gcc/testsuite

[PATCH], Patch #9 of 10, Add tests with large memory offsets

trunk when the previous patches have been applied? 2019-08-14 Michael Meissner * gcc/testsuite/gcc.target/powerpc/prefix-large.h: New set of tests to test prefixed addressing on 'future' system with large numeric offsets. * gcc/testsuite/gcc.target/powe

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