(I'm not sure if an earlier patch got mailed out, I'm sorry if there are
duplicate postings).
I had a thinko in my patch on August 11th, in that I allowed the wi constraint
to be FLOAT_REGS on a non-VSX system, but I had a pattern in movdi that
generated a VSX instruction. I have tightened wi, so that it applies only when
VSX is used.
In addition, I had used wi for lfiwax/lfiwzx and in the case issued an ISA 2.07
(power8) instruction. I have changed these cases to use the wj constraint
(constraint for register class under ISA 2.07 for doing move direct of
DImode). I decided that it wasn't worth adding a new constraint for these
cases, and if the user does -mcpu=power8 -mno-move-direct, it will still
generate the lfiwax/lfiwzx instructions which target the traditional floating
point registers. I have done bootstraps with this compiler and it had no
regressions. Is the patch ok to check in?
2014-08-21 Michael Meissner <meiss...@linux.vnet.ibm.com>
PR target/62195
* doc/md.texi (Machine Constraints): Update PowerPC wi constraint
documentation to state it is only for VSX operations.
* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Make wi
constraint only active if VSX.
* config/rs6000/rs6000.md (lfiwax): Use wj constraint instead of
wi cosntraint for ISA 2.07 lxsiwax/lxsiwzx instructions.
(lfiwzx): Likewise.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
Index: gcc/doc/md.texi
===================================================================
--- gcc/doc/md.texi (revision 214280)
+++ gcc/doc/md.texi (working copy)
@@ -2136,7 +2136,7 @@ If @option{-mmfpgpr} was used, a floatin
Floating point register if direct moves are available, or NO_REGS.
@item wi
-FP or VSX register to hold 64-bit integers or NO_REGS.
+FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.
@item wj
FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.
Index: gcc/config/rs6000/constraints.md
===================================================================
--- gcc/config/rs6000/constraints.md (revision 214280)
+++ gcc/config/rs6000/constraints.md (working copy)
@@ -74,7 +74,7 @@ (define_register_constraint "wh" "rs6000
;; At present, DImode is not allowed in the Altivec registers. If in the
;; future it is allowed, wi/wj can be set to VSX_REGS instead of FLOAT_REGS.
(define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]"
- "FP or VSX register to hold 64-bit integers or NO_REGS.")
+ "FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.")
(define_register_constraint "wj" "rs6000_constraints[RS6000_CONSTRAINT_wj]"
"FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.")
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (revision 214280)
+++ gcc/config/rs6000/rs6000.c (working copy)
@@ -2643,7 +2643,7 @@ rs6000_init_hard_regno_mode_ok (bool glo
wf - Preferred register class for V4SFmode.
wg - Float register for power6x move insns.
wh - FP register for direct move instructions.
- wi - FP or VSX register to hold 64-bit integers.
+ wi - FP or VSX register to hold 64-bit integers for VSX insns.
wj - FP or VSX register to hold 64-bit integers for direct moves.
wk - FP or VSX register to hold 64-bit doubles for direct moves.
wl - Float register if we can do 32-bit signed int loads.
@@ -2663,16 +2663,14 @@ rs6000_init_hard_regno_mode_ok (bool glo
rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; /* SFmode */
if (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
- {
- rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; /* DFmode */
- rs6000_constraints[RS6000_CONSTRAINT_wi] = FLOAT_REGS; /* DImode */
- }
+ rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; /* DFmode */
if (TARGET_VSX)
{
rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
+ rs6000_constraints[RS6000_CONSTRAINT_wi] = FLOAT_REGS; /* DImode */
if (TARGET_VSX_TIMODE)
rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; /* TImode */
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 214280)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -5614,7 +5614,7 @@ (define_insn "*fselsfdf4"
; We don't define lfiwax/lfiwzx with the normal definition, because we
; don't want to support putting SImode in FPR registers.
(define_insn "lfiwax"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi,!wj")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
(unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
UNSPEC_LFIWAX))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
@@ -5694,7 +5694,7 @@ (define_insn_and_split "floatsi<mode>2_l
(set_attr "type" "fpload")])
(define_insn "lfiwzx"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi,!wj")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
(unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
UNSPEC_LFIWZX))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
