This set of 7 patches finally adds the support to allow scalar floating point
values to live in the traditional Altivec registers on machines that have the
appropriate support.
ISA 2.06 (i.e. power7): double precision can go in Altivec registers
ISA 2.07 (i.e. power8): single precision can go in Altivec registers
The PowerPC architecture is complicated in that you can use register+offset
addressing as well as pre-increment/pre-decrement modes for scalar values that
go in the traditional floating point registers, but only register+register
addressing in the traditional Altivec registers.
I've been trying to get this work into shape since I started on the power7
(2010 time frame). With all of these patches applied, I have no regressions,
and would like permission to check in the changes.
I have arranged these patches as a series of 7 patches:
Patch #1: Delete some redundant code I noticed
Patch #2: Move the reload handlers from vector.md to rs6000.md
Patch #3: Make int<->fp conversions aware of upper-regs support
Patch #4: Miscellaneous patches to setup options, etc.
Patch #5: Rework secondary reload handlers to deal with upper regs
Patch #6: Make -mupper-regs-{df,sf} visible and documented
Patch #7: New tests for -mupper-regs-{sf,df}. Fix p8vector-ldst.c.
At the moment, these patches do not make the options default, but I would like
to submit a patch to make them default in the future.
In terms of performance on spec 2006 on a power8:
libquantum speeds up (SF mode)
bwaves slows down
gromacs speeds up (both SF and DF mode)
cactusADM slows down
namd speeds up (DF mode)
calculix speeds up (SF mode)
lbm speeds up (DF mode)
I'm puzzled why libquantum speeds up, as it doesn't generate the new
instructions. I would like to also figure out why bwaves/cactusADM slow down.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
