om: Richard Biener
Sent: Thursday, August 22, 2024 5:47 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v2] Match: Support form 1 for scalar signed integer .SAT_ADD
On Wed, Aug 7, 2024 at 11:31 AM
Thanks Jeff.
> OK. I'm assuming we don't have to worry about the case where X is wider
> than Xmode? ie, a DImode on rv32?
Yes, the DImode is disabled by ANYI iterator for ussub pattern.
Pan
-Original Message-
From: Jeff Law
Sent: Sunday, August 25, 2024 11:22
s-complement add of its arguments
> promoted/demoted to the result type, correct?
Yes, that make sense to me.
Pan
-Original Message-
From: Richard Biener
Sent: Sunday, August 25, 2024 3:42 PM
To: Li, Pan2
Cc: Jakub Jelinek ; gcc-patches@gcc.gnu.org
Subject: Re: [PATCH v1] Vect: P
Got it, thanks Jeff.
Pan
-Original Message-
From: Jeff Law
Sent: Monday, August 26, 2024 10:21 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v3] RISC-V: Support IMM for operand 0 of ussub pattern
On
sent here - that is,
> the comment quotes a source form while we match what we see on
> GIMPLE? I do expect the matching will be quite fragile when not
> being isolated.
Got it, will update the comments to gimple.
Pan
-Original Message-
From: Richard Biener
Sent: Monday, A
in v3.
Pan
-Original Message-
From: Richard Biener
Sent: Tuesday, August 27, 2024 5:09 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; tamar.christ...@arm.com; juzhe.zh...@rivai.ai;
kito.ch...@gmail.com; jeffreya...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v2] Vect: Reconcile t
inal Message-
From: Richard Biener
Sent: Tuesday, August 27, 2024 4:41 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; tamar.christ...@arm.com; juzhe.zh...@rivai.ai;
kito.ch...@gmail.com; jeffreya...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v3] Match: Support form 1 for scalar signed i
Kindly ping.
Pan
-Original Message-
From: Li, Pan2
Sent: Monday, August 19, 2024 10:05 AM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com;
rdapp@gmail.com; Li, Pan2
Subject: [PATCH v2] Test: Move pr116278 run test to dg/torture
Hi Patrick,
Could you please help to re-trigger the pre-commit?
Thanks in advance!
Pan
-Original Message-
From: Patrick O'Neill
Sent: Tuesday, August 20, 2024 12:14 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com; Jef
Noted with thanks, will commit with that change if no surprise from test.
Pan
-Original Message-
From: Richard Biener
Sent: Wednesday, August 28, 2024 3:24 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com; rdapp
iginal Message-
From: Richard Biener
Sent: Tuesday, June 4, 2024 9:22 PM
To: Li, Pan2 ; Richard Sandiford
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
tamar.christ...@arm.com
Subject: Re: [PATCH v1] Internal-fn: Add new IFN mask_len_strided_load/store
On Tue, May 28
Kindly ping, almost the same but for subtract.
Pan
-Original Message-
From: Li, Pan2
Sent: Tuesday, May 28, 2024 4:30 PM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; tamar.christ...@arm.com;
richard.guent...@gmail.com; Li, Pan2
Subject: [PATCH v1
Thanks Richard, will commit after the rebased pass the regression test.
Pan
-Original Message-
From: Richard Biener
Sent: Wednesday, June 5, 2024 3:19 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
tamar.christ...@arm.com
Subject: Re: [PATCH
rt + stride * i] && mask[i] && i < (len + bias)
Pan
-----Original Message-
From: Li, Pan2
Sent: Wednesday, June 5, 2024 9:18 AM
To: Richard Biener ; Richard Sandiford
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
tamar.christ...@arm.com
Subje
double confirm if you cannot see .SAT_SUB after
widen_mul pass in x86 for unsigned scalar int?
Of course, I will have a try later as in the middle of sth.
https://gcc.gnu.org/pipermail/gcc-patches/2024-May/653024.html
Pan
-Original Message-
From: Uros Bizjak
Sent: Wednesday, June 5, 202
5, 2024 4:30 PM
To: Li, Pan2
Cc: Richard Biener ; gcc-patches@gcc.gnu.org;
juzhe.zh...@rivai.ai; kito.ch...@gmail.com; tamar.christ...@arm.com
Subject: Re: [PATCH v1] Internal-fn: Support new IFN SAT_SUB for unsigned
scalar int
On Wed, Jun 5, 2024 at 10:22 AM Li, Pan2 wrote:
>
> > Is
Committed with the example in commit log updated, thanks all.
Pan
-Original Message-
From: Li, Pan2
Sent: Wednesday, June 5, 2024 4:38 PM
To: Uros Bizjak
Cc: Richard Biener ; gcc-patches@gcc.gnu.org;
juzhe.zh...@rivai.ai; kito.ch...@gmail.com; tamar.christ...@arm.com
Subject: RE
Thanks for explaining. I see, cmove is well designed for such cases.
Pan
-Original Message-
From: Uros Bizjak
Sent: Wednesday, June 5, 2024 4:46 PM
To: Li, Pan2
Cc: Richard Biener ; gcc-patches@gcc.gnu.org;
juzhe.zh...@rivai.ai; kito.ch...@gmail.com; tamar.christ...@arm.com
Subject
Thanks Richard for comments, will address the comments in v7, and looks like I
also need to resolve conflict up to a point.
Pan
-Original Message-
From: Richard Biener
Sent: Wednesday, June 5, 2024 4:50 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch
v |
+-+|
| PHI | <--+
+-+
So I am not very sure if we need (or reasonable) to take care of all the PHI
gimple flows (may impossible ?) Or keep the simplest one for now and add more
case by case.
Thanks a lot.
Pan
-Original Message-
From: L
Committed, thanks Richard.
Pan
-Original Message-
From: Richard Biener
Sent: Thursday, June 6, 2024 6:50 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
tamar.christ...@arm.com; ubiz...@gmail.com
Subject: Re: [PATCH v2] Vect: Support IFN
#x27;t enough.
Got it. Thanks, will send the v7 if no surprise from test suites.
Pan
-Original Message-
From: Richard Biener
Sent: Thursday, June 6, 2024 6:47 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
tamar.christ...@arm.com
Subject: Re:
Committed, thanks Richard.
Pan
-Original Message-
From: Richard Biener
Sent: Thursday, June 6, 2024 10:04 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
tamar.christ...@arm.com
Subject: Re: [PATCH v7] Match: Support more form for scalar
Committed the series as the middle-end patch committed.
Pan
From: Li, Pan2
Sent: Monday, June 3, 2024 11:24 AM
To: juzhe.zh...@rivai.ai; gcc-patches
Cc: kito.cheng
Subject: RE: [PATCH v1 1/5] RISC-V: Add testcases for scalar unsigned SAT_ADD
form 1
Thanks Juzhe, will commit it after the
n/max
> or zicond?
No, I mean some other forms like branch need the improvement from the middle
end(aka widen_mul).
Pan
-Original Message-
From: Robin Dapp
Sent: Friday, June 7, 2024 6:18 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; kito.ch.
> LGTM.
Committed, thanks Robin.
> Let's keep in mind that min/max will save us two insns(?)
> and a conditional move would save us one.
Got it, cmov is well designed for such case(s).
Pan
-Original Message-
From: Robin Dapp
Sent: Friday, June 7, 2024 9:57 PM
To:
, 2024 9:50 PM
To: Robin Dapp ; Demin Han ;
钟居哲 ; gcc-patches
Cc: kito.cheng ; Li, Pan2
Subject: Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern
On 6/10/24 1:33 AM, Robin Dapp wrote:
>> But isn't canonicalization of EQ/NE safe, even for IEEE NaN and +-0.0?
>>
>> ta
Thank a lot, Jeff.
Pan
-Original Message-
From: Jeff Law
Sent: Tuesday, June 11, 2024 4:15 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com
Subject: Re: [PATCH v1] Widening-Mul: Fix one ICE of gcall insertion for PHI
rectories under gcc/testsuite, I am not very familiar
that where
is the best reasonable location.
Pan
-Original Message-
From: Sam James
Sent: Monday, June 10, 2024 11:33 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
richard.guent...@gmail.co
Got it, thanks. Let me prepare the patch after test.
Pan
-Original Message-
From: Jeff Law
Sent: Tuesday, June 11, 2024 9:42 AM
To: Li, Pan2 ; Sam James
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
richard.guent...@gmail.com
Subject: Re: [PATCH v1
entioned, aka
"a first stmt return twice since you may not insert anything before that".
Could you help to explain more about it? Thanks a lot.
Pan
-Original Message-
From: Richard Biener
Sent: Tuesday, June 11, 2024 3:07 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh..
PHI node
during vectorization. We still need some enhancement from middle-end to support
PHI node vectorization.
After that I will add more test cases with sorts of forms.
Pan
-Original Message-
From: Robin Dapp
Sent: Tuesday, June 11, 2024 4:03 PM
To: Li, Pan2 ; gcc-patches@gcc.g
Committed, thanks Robin.
Pan
-Original Message-
From: Robin Dapp
Sent: Tuesday, June 11, 2024 4:19 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com
Subject: Re: [PATCH v1] RISC-V: Implement .SAT_SUB
Got it. Thanks Richard.
Pan
-Original Message-
From: Richard Biener
Sent: Tuesday, June 11, 2024 5:31 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com
Subject: Re: [PATCH v1] Widening-Mul: Fix one ICE of gcall insertion for PHI
match
On Tue
> Since you are moving it to torture, please remove -O3 as it is already
> supplied there as one of the torture options.
Oh, I see. Thanks for comments, and will update it in v2.
Pan
From: Andrew Pinski
Sent: Tuesday, June 11, 2024 9:45 PM
To: Li, Pan2
Cc: GCC Patches ; 钟居哲 ; Kito
Committed, thanks Richard.
Pan
-Original Message-
From: Richard Biener
Sent: Wednesday, June 12, 2024 2:41 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com
Subject: Re: [PATCH v1] Widening-Mul: Take gsi after_labels
Do we need to upgrade the binutils of the riscv-gnu-toolchain repo? Or we may
have unknown prefixed ISA extension `zaamo' when building.
Pan
-Original Message-
From: Patrick O'Neill
Sent: Wednesday, June 12, 2024 1:08 AM
To: Jeff Law ; gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com;
Committed, thanks Jeff.
Pan
-Original Message-
From: Jeff Law
Sent: Thursday, June 13, 2024 2:11 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
pins...@gmail.com
Subject: Re: [PATCH v2] Test: Move target
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Thursday, June 13, 2024 5:23 PM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; jeffreyalaw ;
Robin Dapp ; Li, Pan2
Subject: Re: [PATCH v1] RISC-V: Bugfix vec_extract vls mode iterator
restriction mismatch
LGTM
: Thursday, June 13, 2024 8:01 PM
To: Li, Pan2
Cc: Richard Biener ; gcc-patches@gcc.gnu.org;
juzhe.zh...@rivai.ai; kito.ch...@gmail.com; tamar.christ...@arm.com
Subject: RE: [PATCH v7] Match: Support more form for scalar unsigned SAT_ADD
On Thu, 6 Jun 2024, Li, Pan2 wrote:
> Committed, tha
Thanks for another try.
Looks the build failure list below has nothing to do with this patch. I think
the correlated owner will take care of this Werror build issue soon.
Pan
-Original Message-
From: Maciej W. Rozycki
Sent: Friday, June 14, 2024 12:15 AM
To: Li, Pan2
Cc: Richard
Thanks Juzhe, will commit the series after the middle-end patch.
Pan
From: juzhe.zh...@rivai.ai
Sent: Friday, June 14, 2024 10:24 AM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; jeffreyalaw ;
Robin Dapp ; Li, Pan2
Subject: Re: [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB
Committed, thanks Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Friday, June 14, 2024 3:33 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; jeffreya...@gmail.com;
rdapp@gmail.com
Subject: Re: [PATCH v1] RISC-V: Bugfix vec_extract v mode iterator
Thanks Richard for comments.
> :c shouldn't be necessary on the plus
> or on the bit_xor
> OK with those changes.
Will remove the :c and commit it if there is no surprise from test suites.
Pan
-Original Message-
From: Richard Biener
Sent: Friday, June 14, 2024 4:05 P
Hi Richard,
Here is one PR related to this patch (by git bisect), details as below.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115458
I am still trying to narrow down which change caused this failure or any hints
here?
Pan
-Original Message-
From: Richard Biener
Sent: Wednesday, M
> It definitely looks like a latent issue being triggered. Either in LRA
> or in how the target presents itself.
Thanks Richard, will have a try and keep you posted.
Pan
-Original Message-
From: Richard Biener
Sent: Friday, June 14, 2024 9:11 PM
To: Li, Pan2
Cc: gcc-p
Committed with those changes and test suites passed.
Pan
-Original Message-
From: Li, Pan2
Sent: Friday, June 14, 2024 4:15 PM
To: Richard Biener
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com; rdapp@gmail.com
Subject: RE: [PATCH v1
CH for this.
Pan
-Original Message-
From: Richard Biener
Sent: Tuesday, June 18, 2024 7:03 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v1] Match: Support forms 7 and 8 for the un
Thanks Richard, will commit this one and then have a try to reduce unnecessary
pattern following your suggestion.
Pan
-Original Message-
From: Richard Biener
Sent: Tuesday, June 18, 2024 7:08 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com
Committed the series, thanks Juzhe.
Pan
From: 钟居哲
Sent: Wednesday, June 19, 2024 12:01 PM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; jeffreyalaw ;
rdapp.gcc ; Li, Pan2
Subject: Re: [PATCH v1 2/7] RISC-V: Add testcases for unsigned .SAT_ADD vector
form 3
lgtm
--Reply to Message
Committed the series, thanks Juzhe.
Pan
From: 钟居哲
Sent: Wednesday, June 19, 2024 11:55 AM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; jeffreyalaw ;
rdapp.gcc ; Li, Pan2
Subject: Re: [PATCH v1 1/2] RISC-V: Add testcases for unsigned .SAT_SUB scalar
form 11
lgtm
--Reply to
the next step, thanks a lot.
patt_34 = .SAT_SUB (m_11, wsize_12(D));
patt_35 = (vector([8,8]) short unsigned int) patt_34;
Pan
-Original Message-
From: Richard Biener
Sent: Friday, June 14, 2024 4:05 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.
Committed the series, thanks Juzhe.
Pan
From: 钟居哲
Sent: Wednesday, June 19, 2024 9:20 PM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; jeffreyalaw ;
rdapp.gcc ; Li, Pan2
Subject: Re: [PATCH v1 1/8] RISC-V: Add testcases for unsigned .SAT_SUB vector
form 3
lgtm
--Reply to Message
Got it. Thanks Richard for suggestion.
Pan
-Original Message-
From: Richard Biener
Sent: Wednesday, June 19, 2024 4:00 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v1] Match
re some additional change
from vectorize_convert when
I try to do that in previous. Let me double check about it, and keep you posted.
Pan
-Original Message-
From: Richard Biener
Sent: Friday, June 21, 2024 3:00 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; ki
/home/pli/gcc/555/riscv-gnu-toolchain/gcc/__RISCV_BUILD__/../gcc/passes.cc:1688
0x191a116 execute_todo
Pan
-Original Message-
From: Richard Biener
Sent: Friday, June 21, 2024 5:29 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffr
> You need to refactor this to add to the stmts pattern def sequence
> (look for append_pattern_def_seq uses for example)
Thanks Richard, really save my day, will have a try in v2.
Pan
-Original Message-
From: Richard Biener
Sent: Saturday, June 22, 2024 9:19 PM
To: Li, Pan2
C
5, 2024 4:00 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
jeffreya...@gmail.com; pins...@gmail.com
Subject: RE: [PATCH v2] Vect: Support truncate after .SAT_SUB pattern in zip
Hi,
> -Original Message-
> Fr
torized code if a is limited to char unsigned. Of
course we can do that based on this patch.
Pan
-Original Message-
From: Tamar Christina
Sent: Tuesday, June 25, 2024 12:01 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@
Got it, thanks Tamer, will have a try.
Pan
-Original Message-
From: Tamar Christina
Sent: Tuesday, June 25, 2024 2:11 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
jeffreya...@gmail.com; pins...@gmail.com
Subject
Thanks Tamer, gimple_ranger works well for that case, will send another patch
after this one.
Pan
-Original Message-
From: Li, Pan2
Sent: Tuesday, June 25, 2024 2:26 PM
To: Tamar Christina ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent
Thanks Richard, will address the comments in v2.
Pan
-Original Message-
From: Richard Biener
Sent: Wednesday, June 26, 2024 9:52 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v1
.
Sure, and will send the v2 if no surprise from test.
Pan
-Original Message-
From: Richard Biener
Sent: Wednesday, June 26, 2024 9:56 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com; pins...@gmail.com
Subject: Re: [PA
Kindly ping.
Pan
-Original Message-
From: Li, Pan2
Sent: Monday, July 15, 2024 6:35 PM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com;
rdapp@gmail.com; Li, Pan2
Subject: [PATCH v3] RISC-V: Implement the .SAT_TRUNC for scalar
Committed, thanks Robin.
Pan
-Original Message-
From: Robin Dapp
Sent: Monday, July 22, 2024 11:27 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com
Subject: Re: [PATCH v3] RISC-V: Implement the .SAT_TRUNC for scalar
LGTM
even ones without SAT_TRUNC support. And then you should not need the
> other testcase either.
Thanks all, will address above comments and commit it if no surprise from test.
Pan
-Original Message-
From: Richard Sandiford
Sent: Tuesday, July 23, 2024 10:03 PM
To: Richard Biener
Cc: L
> OK.
Committed, thanks Richard.
Pan
-Original Message-
From: Richard Biener
Sent: Friday, July 26, 2024 9:32 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
tamar.christ...@arm.com; jeffreya...@gmail.com; rdapp@gmail.com
Subject:
> OK
Committed, thanks Richard.
Pan
-Original Message-
From: Richard Biener
Sent: Monday, July 29, 2024 5:03 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
tamar.christ...@arm.com; jeffreya...@gmail.com; rdapp@gmail.com
Subject:
> OK.
Thanks Richard, will wait the confirmation from Thomas in case I missed some
more failed cases.
Pan
-Original Message-
From: Richard Biener
Sent: Monday, July 29, 2024 4:44 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
tamar.chr
Thanks Richard S for comments, updated in v2.
https://gcc.gnu.org/pipermail/gcc-patches/2024-July/658637.html
Pan
-Original Message-
From: Richard Sandiford
Sent: Tuesday, July 30, 2024 12:09 AM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com
Committed, thanks Robin.
Pan
-Original Message-
From: Robin Dapp
Sent: Tuesday, July 30, 2024 2:28 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Robin
Dapp
Subject: Re: [PATCH v1] RISC-V: Take Xmode instead of Pmode
Kindly ping.
Pan
-Original Message-
From: Li, Pan2
Sent: Tuesday, July 23, 2024 1:06 PM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com;
rdapp@gmail.com; Li, Pan2
Subject: [PATCH v1] RISC-V: Implement the quad and oct .SAT_TRUNC
> Still OK.
Thanks Richard, let me wait the final confirmation from Richard S.
Pan
-Original Message-
From: Richard Biener
Sent: Tuesday, July 30, 2024 5:03 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
tamar.christ...@arm.com; jeffr
Thanks Jeff for comments, let me refine the comments in v2.
Pan
-Original Message-
From: Jeff Law
Sent: Sunday, August 4, 2024 6:25 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v1] RISC-V: Support IMM
e need to take care of vector in type_strictly_matches_mode_p,
right ?
Pan
-Original Message-
From: Richard Biener
Sent: Monday, August 5, 2024 7:02 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com; rdapp@gmail.com
Sub
gust 5, 2024 7:16 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v1] Match: Support form 1 for scalar signed integer .SAT_ADD
On Mon, Aug 5, 2024 at 9:14 AM wrote:
>
> From: Pan Li
-
From: Li, Pan2
Sent: Monday, August 5, 2024 9:52 PM
To: Richard Biener
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com; rdapp@gmail.com
Subject: RE: [PATCH v1] Match: Support form 1 for scalar signed integer .SAT_ADD
Thanks Richard for
attern matching be constrainted.
Sure, will have a try in vectorizable_internal_function.
Pan
-Original Message-
From: Richard Biener
Sent: Monday, August 5, 2024 9:43 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com; rdap
m: Richard Biener
Sent: Tuesday, August 6, 2024 7:50 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@gmail.com;
jeffreya...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v1] Match: Support form 1 for scalar signed integer .SAT_ADD
On Tue, Aug 6, 2024 at 3:21 AM
, NULL)
> + && type_has_mode_precision_p (otype))
To:
> + if (type_has_mode_precision_p (otype)
> + && gimple_unsigned_integer_sat_trunc (lhs, ops, NULL))
Pan
-Original Message-
From: Richard Biener
Sent: Tuesday, August 6, 2024 9:26 PM
To: Li, Pan2
Cc: gcc-patches@gc
Thanks Edwin, should be one silly mistake, will fix it ASAP.
Pan
-Original Message-
From: Edwin Lu
Sent: Friday, April 12, 2024 5:20 AM
To: Li, Pan2 ; Bernd Edlinger ;
Kito Cheng ; juzhe.zh...@rivai.ai
Cc: gcc-patches
Subject: Re: [PATCH v1] RISC-V: Bugfix ICE for the vector return
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Friday, April 12, 2024 2:11 PM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; Li, Pan2
Subject: Re: [PATCH v1] RISC-V: Bugfix ICE non-vector in
TARGET_FUNCTION_VALUE_REGNO_P
LGTM。
juzhe.zh
ssage-
From: Kito Cheng
Sent: Friday, April 12, 2024 4:56 PM
To: Li, Pan2
Cc: juzhe.zh...@rivai.ai; gcc-patches
Subject: Re: [PATCH v1] RISC-V: Bugfix ICE non-vector in
TARGET_FUNCTION_VALUE_REGNO_P
Does FP reg also need gurared with TARGET_HARD_FLOAT? could you try to
compile that case with
Message-
From: Li, Pan2
Sent: Friday, April 12, 2024 6:58 PM
To: Kito Cheng
Cc: juzhe.zh...@rivai.ai; gcc-patches
Subject: RE: [PATCH v1] RISC-V: Bugfix ICE non-vector in
TARGET_FUNCTION_VALUE_REGNO_P
Sure thing, the FP_RETURN only acts on ABI_xxx similar to below:
#define FP_RETURN
Kindly ping^ for this ice fix.
Pan
-Original Message-
From: Li, Pan2
Sent: Saturday, April 6, 2024 8:02 PM
To: Li, Pan2 ; Jeff Law ; Robin Dapp
; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; richard.guent...@gmail.com;
Wang, Yanzhang ; Liu, Hongtao
Subject
Sure, will revert b3b2799b872 and then file the patch for the xfail tests.
Pan
-Original Message-
From: Robin Dapp
Sent: Friday, April 19, 2024 10:54 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com
Subject: Re: [PATCH v1] RI
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Saturday, April 20, 2024 9:20 AM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; Robin Dapp ; Li,
Pan2
Subject: Re: [PATCH v1] RISC-V: Add xfail test case for wv insn register overlap
LGTM.
juzhe.zh
Committed, thanks Robin.
Pan
-Original Message-
From: Robin Dapp
Sent: Saturday, April 20, 2024 7:46 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com
Subject: Re: [PATCH] RISC-V: Add xfail test case for wv insn highest
Committed, thanks Juzhe.
Pan
From: 钟居哲
Sent: Sunday, April 21, 2024 7:59 AM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; rdapp.gcc ; Li,
Pan2
Subject: Re: [PATCH v1] RISC-V: Add xfail test case for incorrect overlap on v0
lgtm
juzhe.zh...@rivai.ai
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Monday, April 22, 2024 11:49 AM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; Robin Dapp ; Li,
Pan2
Subject: Re: [PATCH v1] RISC-V: Add xfail test case for widening register
overlap of vf4/vf8
LGTM
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Monday, April 22, 2024 2:40 PM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; Robin Dapp ; Li,
Pan2
Subject: Re: [PATCH v1] RISC-V: Add xfail test case for highest-number regno
ternary overlap
LGTM
Sure thing. Sorry for that Fortran is not fully tested for this change, will
take a look into it ASAP.
Pan
From: 钟居哲
Sent: Tuesday, April 23, 2024 6:06 AM
To: patrick ; Li, Pan2 ; gcc-patches
Cc: kito.cheng ; rdapp.gcc
Subject: Re: Re: [PATCH v1] RISC-V: Adjust overlap attr after revert
al Message-
From: Palmer Dabbelt
Sent: Tuesday, April 23, 2024 8:43 AM
To: juzhe.zh...@rivai.ai
Cc: Patrick O'Neill ; Li, Pan2 ; Robin
Dapp ; gcc-patches@gcc.gnu.org; Kito Cheng
Subject: Re: Re: [PATCH v1] RISC-V: Revert RVV wv instructions overlap and
xfail tests
On Mon, 22 Apr 2024 1
-Original Message-
From: Patrick O'Neill
Sent: Tuesday, April 23, 2024 8:32 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v1] RISC-V: Adjust overlap attr after revert d3544cea63d
and e65aaf8efe1
This pat
ARGET="-O0 -g"
make -j $(nproc) all-gcc && make install-gcc
3. ../__RISC-V_INSTALL___RV64/bin/riscv64-unknown-elf-gcc
gcc/testsuite/gcc.dg/graphite/pr111878.c -O3 -fgraphite-identity
-fsave-optimization-record -march=rv64gcv -mabi=lp64d -c -S -o -
Pan
-Original Message
Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Wednesday, April 24, 2024 2:46 PM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; Robin Dapp ; Li,
Pan2
Subject: Re: [PATCH v1] RISC-V: Add xfail test case for highpart overlap of
vext.vf
LGTM
Request review as this revert patch contains some manually resolved conflict
changes.
Passed the rv64gcv fully regression test with isl build.
Pan
-Original Message-
From: Li, Pan2
Sent: Wednesday, April 24, 2024 8:59 PM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch
Committed, thanks Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Wednesday, April 24, 2024 9:11 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; rdapp@gmail.com
Subject: Re: [PATCH v1] Revert "RISC-V: Support highpart register overlap for
vwcvt&q
in Dapp
Sent: Wednesday, April 24, 2024 10:12 PM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com
Subject: Re: [PATCH v1] Revert "RISC-V: Support highpart register overlap for
vwcvt"
> (define_insn "@pred_vwsll_scalar
is true currently.
Pan
-Original Message-
From: Li, Pan2
Sent: Wednesday, April 24, 2024 10:38 PM
To: Robin Dapp ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com
Subject: RE: [PATCH v1] Revert "RISC-V: Support highpart register overlap for
vwcvt"
> Just n
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