This patch support ssdbltrp[1] and smdbltrp[2] extension.
To enable GCC to recognize and process ssdbltrp and smdbltrp extension
correctly at compile time.
[1] https://github.com/riscv/riscv-isa-manual/blob/main/src/ssdbltrp.adoc
[2] https://github.com/riscv/riscv-isa-manual/blob/main/src/smdbltr
This patch support ssdbltrp[1] and smdbltrp[2] extension.
To enable GCC to recognize and process ssdbltrp and smdbltrp extension
correctly at compile time.
[1] https://github.com/riscv/riscv-isa-manual/blob/main/src/ssdbltrp.adoc
[2] https://github.com/riscv/riscv-isa-manual/blob/main/src/smdbltr
This patch support zilsd and zclsd[1] extensions.
To enable GCC to recognize and process zilsd and zclsd extension correctly at
compile time.
[1] https://github.com/riscv/riscv-zilsd
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(riscv_subset_list::check_conflict_ext): New exten
This patch support svvptc extension.
To enable GCC to recognize and process svvptc extension correctly at compile
time.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New extension.
* common/config/riscv/riscv-ext-bitmask.def (RISCV_EXT_BITMASK): Ditto.
* config/ri
This patch support svvptc extension[1].
To enable GCC to recognize and process svvptc extension correctly at compile
time.
[1] https://github.com/riscv/riscv-svvptc
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New extension.
* common/config/riscv/riscv-ext-bitmask.def (
This patch support svvptc extension[1].
To enable GCC to recognize and process svvptc extension correctly at compile
time.
[1] https://github.com/riscv/riscv-svvptc
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New extension.
* common/config/riscv/riscv-ext-bitmask.def (
This patch support zilsd and zclsd[1] extensions.
To enable GCC to recognize and process zilsd and zclsd extension correctly at
compile time.
[1] https://github.com/riscv/riscv-zilsd
Changes for v2:
- Remove the addition of zilsd extension in
gcc/common/config/riscv/riscv-ext-bitmask.def
- Fix
This patch support ssnpm, smnpm and smmpm extensions[1].
To enable GCC to recognize and process ssnpm, smnpm and smmpm extensions
correctly at compile time.
[1]
https://github.com/riscv/riscv-j-extension/blob/master/zjpm/instructions.adoc
gcc/ChangeLog:
* common/config/riscv/riscv-comm
This patch support zilsd and zclsd[1] extensions.
To enable GCC to recognize and process zilsd and zclsd extension correctly at
compile time.
[1] https://github.com/riscv/riscv-zilsd
Changes for v2:
- Remove the addition of zilsd and zclsd extension in
gcc/common/config/riscv/riscv-ext-bitmask.
This patch support zama16b extension[1].
To enable GCC to recognize and process zama16b extension correctly at compile
time.
[1] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New extension.
* config
This patch support sdtrig and ssstrict extensions[1].
To enable GCC to recognize and process sdtrig and ssstrict extensions correctly
at compile time.
[1] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New e
The patch has been modified as follows：
This patch support ssnpm, smnpm, smmpm, sspm and supm extensions[1].
To enable GCC to recognize and process ssnpm, smnpm, smmpm, sspm and
supm extensions correctly at compile time.
[1]https://github.com/riscv/riscv-j-extension/blob/master/zjpm/instructio
This patch add zvfbfa and zvfofp8min intrinsic[1].
To enable GCC to recognize and process zvfbfa and zvfofp8min extensions
correctly at compile time.
[1]https://github.com/aswaterman/riscv-misc/blob/e515758c24504cf3c16145bc763a76c59425ed1b/isa/zvfbfa.adoc
gcc/ChangeLog:
* common/config/
Okay, thanks.
Dongyan Chen
在 2025/5/7 7:11, Jeff Law 写道:
On 4/18/25 2:47 AM, Dongyan Chen wrote:
This patch support sdtrig and ssstrict extensions[1].
To enable GCC to recognize and process sdtrig and ssstrict extensions
correctly at compile time.
[1]https://github.com/riscv/riscv
get *-*-* } 0 } */
+/* { dg-error "'-march=rv64gc_zilsd_zclsd': zclsd extension supports in
rv32 only" "" { target *-*-* } 0 } */
+/* { dg-error
"'-march=rv64imafdc_zicsr_zifencei_zilsd_zmmul_zaamo_zalrsc_zca_zcd_zclsd':
zilsd extension supports in
This patch support Qualcomm uC Xqccmp extension[1].
To enable GCC to recognize and process xqccmp extension correctly at compile
time.
[1]https://github.com/quic/riscv-unified-db/releases/tag/Xqccmp_extension-0.1.0
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New extension.
This patch support ssnpm, smnpm, smmpm, sspm and supm extensions[1].
To enable GCC to recognize and process ssnpm, smnpm, smmpm, sspm and
supm extensions correctly at compile time.
[1]https://github.com/riscv/riscv-j-extension/blob/master/zjpm/instructions.adoc
Changes for v4:
- Fix the code bas
This patch support ssnpm, smnpm, smmpm, sspm and supm extensions[1].
To enable GCC to recognize and process ssnpm, smnpm, smmpm, sspm and
supm extensions correctly at compile time.
[1]https://github.com/riscv/riscv-j-extension/blob/master/zjpm/instructions.adoc
Changes for v5:
- Fix the testsuit
Okay, thanks!
在 2025/5/12 21:32, Kito Cheng 写道:
This patch is somewhat corrupt...but anyway, fixed and pushed to trunk
During the GCC compilation, some warnings about temporary object dangling
references emerged. They appeared in these code lines in riscv-common.cc:
const riscv_ext_info_t &implied_ext_info, const riscv_ext_info_t &ext_info =
get_riscv_ext_info (ext) and auto &ext_info = get_riscv_ext_info (search
I fix the code by changing the argument type of get_riscv_ext_info to
`const char *` and the link is:
https://gcc.gnu.org/pipermail/gcc-patches/2025-May/684057.html
在 2025/5/16 10:35, Kito Cheng 写道:
Hm, it really doesn't make too much sense to get that warning, but
I can reproduce that whe
During the GCC compilation, some warnings about temporary object dangling
references emerged. They appeared in these code lines in riscv-common.cc:
const riscv_ext_info_t &implied_ext_info, const riscv_ext_info_t &ext_info =
get_riscv_ext_info (ext) and auto &ext_info = get_riscv_ext_info (search
Failed testcases occurred in the regression test of gcc: cset-sext-sfb.c failed
the -Oz test, and zba-slliuw.c failed the -Og test.
This patch solves the problem by skipping the optimization.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cset-sext-sfb.c: Skip for -Oz.
* gcc.target/r
Thanks. I will pay attention to this.
Dongyan Chen
在 2025/5/22 11:49, Jeff Law 写道:
On 5/21/25 9:16 PM, Dongyan Chen wrote:
Failed testcases occurred in the regression test of gcc:
cset-sext-sfb.c failed
the -Oz test, and zba-slliuw.c failed the -Og test.
This patch solves the problem by
This patch support svbare extension, which is an extension in RVA23 profile.
To enable GCC to recognize and process svbare extension correctly at compile
time.
---
gcc/config/riscv/riscv-ext.def | 13 +
gcc/config/riscv/riscv-ext.opt | 2 ++
gcc/doc/riscv-ext.texi
This patch implies zicsr for svade and svadu extensions.
According to the riscv-privileged spec, the svade and svadu extensions
are privileged instructions, so they should imply zicsr.
gcc/ChangeLog:
* config/riscv/riscv-ext.def: Imply zicsr.
---
gcc/config/riscv/riscv-ext.def | 4 ++--
This patch support smcntrpmf extension[1].
To enable GCC to recognize and process smcntrpmf extension correctly at compile
time.
[1]https://github.com/riscvarchive/riscv-smcntrpmf
gcc/ChangeLog:
* config/riscv/riscv-ext.def: New extension defs.
* config/riscv/riscv-ext.opt: Ditt
This patch support svbare extension, which is an extension in RVA23 profile.
To enable GCC to recognize and process svbare extension correctly at compile
time.
gcc/ChangeLog:
* config/riscv/riscv-ext.def: New extension defs.
* config/riscv/riscv-ext.opt: Ditto.
* doc/risc
Okay, thanks, I get that.
Dongyan Chen
在 2025/6/3 9:34, Kito Cheng 写道:
LGTM, and will commit once CI happy, BTW, next time you could name the
testcase into arch-.c e.g. arch-svbare.c, that could prevent
potential filename conflict. :)
I add a ChangeLog and update testname in
https://gcc.gnu.org/pipermail/gcc-patches/2025-June/685401.html
Thanks
Dongyan Chen
在 2025/6/3 3:34, Jeff Law 写道:
On 5/29/25 7:27 AM, Dongyan Chen wrote:
This patch support svbare extension, which is an extension in RVA23
profile.
To enable GCC to
Yes, I would like to do it.
Dongyan Chen
在 2025/6/19 23:17, Kito Cheng 写道:
I guess we should implement an auto generated document for mcpu and
mtune document like what we do for -march.
Dongyan, do you have interest to implement that? :)
On Thu, Jun 19, 2025 at 10:02 PM Jeff Law wrote:
We
According to the discussion in
https://gcc.gnu.org/pipermail/gcc-patches/2025-June/686893.html, by creating
a -mtune=generic may be a good idea to slove the question regarding the branch
cost.
gcc/ChangeLog:
* config/riscv/riscv-cores.def (RISCV_TUNE): Add "generic" tune.
(RISCV_
According to the discussion in
https://gcc.gnu.org/pipermail/gcc-patches/2025-June/686893.html, by creating
a -mtune=generic may be a good idea to slove the question regarding the branch
cost.
gcc/ChangeLog:
* config/riscv/riscv-cores.def (RISCV_TUNE): Add "generic" tune.
(RISCV_
According to the discussion in
https://gcc.gnu.org/pipermail/gcc-patches/2025-June/686893.html, by creating
a -mtune=generic may be a good idea to slove the question regarding the branch
cost.
Changes for v2:
- Delete the code about -mcpu=generic.
gcc/ChangeLog:
* config/riscv/riscv-cor
OKay, the patch v2 is in the link :
https://gcc.gnu.org/pipermail/gcc-patches/2025-June/686987.html
Thanks
Dongyan Chen
在 2025/6/18 17:40, Kito Cheng 写道:
@@ -78,6 +79,7 @@ RISCV_CORE("sifive-e31", "rv32imac", "sifive-3-series")
RISCV_CORE("sifive
Thanks, I found that it can also be solved by changing the default mtune
in file "configure" of riscv-gnu-toolchain and I will prepare a PR to
riscv-gnu-toolchain repo.
Dongyan Chen
在 2025/6/19 15:55, Kito Cheng 写道:
Thanks, pushed with one minor change.
Robin has mentioned tha
Automatically generate -mcpu and -mtune options in invoke.texi from
the unified riscv-cores.def metadata, ensuring documentation stays in sync
with definitions and reducing manual maintenance.
gcc/ChangeLog:
* Makefile.in: Add riscv-mcpu.texi and riscv-mtune.texi to the list
of files
Hi, I've come across a question regarding the branch cost of gcc. In the link
https://gcc.godbolt.org/z/hnddevd5h, gcc fails to recognize the optimization
branch judgment, while llvm does. I eventually discovered that the value of the
branch
cost was too small. Moreover, in that link, if I add "-m
Thanks very much!
Dongyan Chen
在 2025/6/17 15:34, Yangyu Chen 写道:
On 17/6/2025 12:08, Dongyan Chen wrote:
Hi, I've come across a question regarding the branch cost of gcc. In
the link
https://gcc.godbolt.org/z/hnddevd5h, gcc fails to recognize the
optimization
branch judgment, while
No worries, thanks!
在 2025/7/29 23:02, Kito Cheng 写道:
I thought I already merged that until today's RISC-V patchwork
meeting, committed to trunk :P
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