This patch support ssnpm, smnpm and smmpm extensions[1]. To enable GCC to recognize and process ssnpm, smnpm and smmpm extensions correctly at compile time.
[1] https://github.com/riscv/riscv-j-extension/blob/master/zjpm/instructions.adoc gcc/ChangeLog: * common/config/riscv/riscv-common.cc: New extension. * config/riscv/riscv.opt: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-45.c: New test. --- gcc/common/config/riscv/riscv-common.cc | 12 ++++++++++++ gcc/config/riscv/riscv.opt | 12 ++++++++++++ gcc/testsuite/gcc.target/riscv/arch-45.c | 5 +++++ 3 files changed, 29 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/arch-45.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index b34409adf39c..2d218e4ad748 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -227,6 +227,10 @@ static const riscv_implied_info_t riscv_implied_info[] = {"ssstateen", "zicsr"}, {"sstc", "zicsr"}, + {"ssnpm", "zicsr"}, + {"smnpm", "zicsr"}, + {"smmpm", "zicsr"}, + {"xsfvcp", "zve32x"}, {NULL, NULL} @@ -409,6 +413,10 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"ssstateen", ISA_SPEC_CLASS_NONE, 1, 0}, {"sstc", ISA_SPEC_CLASS_NONE, 1, 0}, + {"ssnpm", ISA_SPEC_CLASS_NONE, 1, 0}, + {"smnpm", ISA_SPEC_CLASS_NONE, 1, 0}, + {"smmpm", ISA_SPEC_CLASS_NONE, 1, 0}, + {"svinval", ISA_SPEC_CLASS_NONE, 1, 0}, {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0}, {"svpbmt", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1736,6 +1744,10 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = RISCV_EXT_FLAG_ENTRY ("svnapot", x_riscv_sv_subext, MASK_SVNAPOT), RISCV_EXT_FLAG_ENTRY ("svvptc", x_riscv_sv_subext, MASK_SVVPTC), + RISCV_EXT_FLAG_ENTRY ("ssnpm", x_riscv_ss_subext, MASK_SSNPM), + RISCV_EXT_FLAG_ENTRY ("smnpm", x_riscv_sm_subext, MASK_SMNPM), + RISCV_EXT_FLAG_ENTRY ("smmpm", x_riscv_sm_subext, MASK_SMMPM), + RISCV_EXT_FLAG_ENTRY ("ztso", x_riscv_ztso_subext, MASK_ZTSO), RISCV_EXT_FLAG_ENTRY ("xcvmac", x_riscv_xcv_subext, MASK_XCVMAC), diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 7515c8ea13dd..eca25b0ecd30 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -472,6 +472,18 @@ Mask(SVNAPOT) Var(riscv_sv_subext) Mask(SVVPTC) Var(riscv_sv_subext) +TargetVariable +int riscv_ss_subext + +Mask(SSNPM) Var(riscv_ss_subext) + +TargetVariable +int riscv_sm_subext + +Mask(SMNPM) Var(riscv_sm_subext) + +Mask(SMMPM) Var(riscv_sm_subext) + TargetVariable int riscv_ztso_subext diff --git a/gcc/testsuite/gcc.target/riscv/arch-45.c b/gcc/testsuite/gcc.target/riscv/arch-45.c new file mode 100644 index 000000000000..c23136d3f0b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-45.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_ssnpm_smnpm_smmpm -mabi=lp64" } */ +int foo() +{ +} -- 2.43.0
