This patch support svbare extension, which is an extension in RVA23 profile.
To enable GCC to recognize and process svbare extension correctly at compile
time.
gcc/ChangeLog:
* config/riscv/riscv-ext.def: New extension defs.
* config/riscv/riscv-ext.opt: Ditto.
* doc/riscv-ext.texi: Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-60.c: New test.
---
gcc/config/riscv/riscv-ext.def | 13 +++++++++++++
gcc/config/riscv/riscv-ext.opt | 2 ++
gcc/doc/riscv-ext.texi | 4 ++++
gcc/testsuite/gcc.target/riscv/arch-60.c | 5 +++++
4 files changed, 24 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/arch-60.c
diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index d0adc2b6569b..fc3f2374ede6 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -1948,6 +1948,19 @@ DEFINE_RISCV_EXT(
/* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
/* EXTRA_EXTENSION_FLAGS */ 0)
+DEFINE_RISCV_EXT(
+ /* NAME */ svbare,
+ /* UPPERCAE_NAME */ SVBARE,
+ /* FULL_NAME */ "Satp mode bare is supported",
+ /* DESC */ "",
+ /* URL */ ,
+ /* DEP_EXTS */ ({"zicsr"}),
+ /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+ /* FLAG_GROUP */ sv,
+ /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+ /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+ /* EXTRA_EXTENSION_FLAGS */ 0)
+
#include "riscv-ext-corev.def"
#include "riscv-ext-sifive.def"
#include "riscv-ext-thead.def"
diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index c0dcde652930..ae6ce1fd54f9 100644
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -377,6 +377,8 @@ Mask(SVADU) Var(riscv_sv_subext)
Mask(SVADE) Var(riscv_sv_subext)
+Mask(SVBARE) Var(riscv_sv_subext)
+
Mask(XCVALU) Var(riscv_xcv_subext)
Mask(XCVBI) Var(riscv_xcv_subext)
diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index e64c0d653a9f..890a165d66a9 100644
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -578,6 +578,10 @@
@tab 1.0
@tab Cause exception when hardware updating of A/D bits is disabled
+@item svbare
+@tab 1.0
+@tab Satp mode bare is supported
+
@item xcvalu
@tab 1.0
@tab Core-V miscellaneous ALU extension
diff --git a/gcc/testsuite/gcc.target/riscv/arch-60.c
b/gcc/testsuite/gcc.target/riscv/arch-60.c
new file mode 100644
index 000000000000..ea599f20522d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-60.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_svbare -mabi=lp64" } */
+int foo()
+{
+}
--
2.43.0
