This patch support zilsd and zclsd[1] extensions. To enable GCC to recognize and process zilsd and zclsd extension correctly at compile time.
[1] https://github.com/riscv/riscv-zilsd gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::check_conflict_ext): New extension. * common/config/riscv/riscv-ext-bitmask.def (RISCV_EXT_BITMASK): Ditto. * config/riscv/riscv.opt: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-45.c: New test. * gcc.target/riscv/arch-46.c: New test. * gcc.target/riscv/arch-47.c: New test. --- gcc/common/config/riscv/riscv-common.cc | 17 +++++++++++++++++ gcc/common/config/riscv/riscv-ext-bitmask.def | 2 ++ gcc/config/riscv/riscv.opt | 4 ++++ gcc/testsuite/gcc.target/riscv/arch-45.c | 5 +++++ gcc/testsuite/gcc.target/riscv/arch-46.c | 6 ++++++ gcc/testsuite/gcc.target/riscv/arch-47.c | 5 +++++ 6 files changed, 39 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/arch-45.c create mode 100644 gcc/testsuite/gcc.target/riscv/arch-46.c create mode 100644 gcc/testsuite/gcc.target/riscv/arch-47.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 4c9a72d1180a..eb999b322c78 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -111,6 +111,10 @@ static const riscv_implied_info_t riscv_implied_info[] = {"zfinx", "zicsr"}, {"zdinx", "zicsr"}, + {"zclsd", "zilsd"}, + {"zilsd", "zicsr"}, + {"zclsd", "zicsr"}, + {"zk", "zkn"}, {"zk", "zkr"}, {"zk", "zkt"}, @@ -331,6 +335,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zicntr", ISA_SPEC_CLASS_NONE, 2, 0}, {"zihpm", ISA_SPEC_CLASS_NONE, 2, 0}, + {"zilsd", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zclsd", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zk", ISA_SPEC_CLASS_NONE, 1, 0}, {"zkn", ISA_SPEC_CLASS_NONE, 1, 0}, {"zks", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1301,6 +1308,14 @@ riscv_subset_list::check_conflict_ext () if (lookup ("zcf") && m_xlen == 64) error_at (m_loc, "%<-march=%s%>: zcf extension supports in rv32 only", m_arch); + + if (lookup ("zilsd") && m_xlen == 64) + error_at (m_loc, "%<-march=%s%>: zilsd extension supports in rv32 only", + m_arch); + + if (lookup ("zclsd") && m_xlen == 64) + error_at (m_loc, "%<-march=%s%>: zclsd extension supports in rv32 only", + m_arch); if (lookup ("zfinx") && lookup ("f")) error_at (m_loc, @@ -1641,6 +1656,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = RISCV_EXT_FLAG_ENTRY ("ziccif", x_riscv_zi_subext, MASK_ZICCIF), RISCV_EXT_FLAG_ENTRY ("zicclsm", x_riscv_zi_subext, MASK_ZICCLSM), RISCV_EXT_FLAG_ENTRY ("ziccrse", x_riscv_zi_subext, MASK_ZICCRSE), + RISCV_EXT_FLAG_ENTRY ("zilsd", x_riscv_zi_subext, MASK_ZILSD), RISCV_EXT_FLAG_ENTRY ("zicboz", x_riscv_zicmo_subext, MASK_ZICBOZ), RISCV_EXT_FLAG_ENTRY ("zicbom", x_riscv_zicmo_subext, MASK_ZICBOM), @@ -1721,6 +1737,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = RISCV_EXT_FLAG_ENTRY ("zcd", x_riscv_zc_subext, MASK_ZCD), RISCV_EXT_FLAG_ENTRY ("zcmp", x_riscv_zc_subext, MASK_ZCMP), RISCV_EXT_FLAG_ENTRY ("zcmt", x_riscv_zc_subext, MASK_ZCMT), + RISCV_EXT_FLAG_ENTRY ("zclsd", x_riscv_zc_subext, MASK_ZCLSD), RISCV_EXT_FLAG_ENTRY ("svinval", x_riscv_sv_subext, MASK_SVINVAL), RISCV_EXT_FLAG_ENTRY ("svnapot", x_riscv_sv_subext, MASK_SVNAPOT), diff --git a/gcc/common/config/riscv/riscv-ext-bitmask.def b/gcc/common/config/riscv/riscv-ext-bitmask.def index a733533df98e..af3ea47162b9 100644 --- a/gcc/common/config/riscv/riscv-ext-bitmask.def +++ b/gcc/common/config/riscv/riscv-ext-bitmask.def @@ -80,5 +80,7 @@ RISCV_EXT_BITMASK ("zcf", 1, 5) RISCV_EXT_BITMASK ("zcmop", 1, 6) RISCV_EXT_BITMASK ("zawrs", 1, 7) RISCV_EXT_BITMASK ("svvptc", 1, 8) +RISCV_EXT_BITMASK ("zilsd", 1, 9) +RISCV_EXT_BITMASK ("zclsd", 1, 10) #undef RISCV_EXT_BITMASK diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index a6a61a83db1b..f2891ea65e38 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -253,6 +253,8 @@ Mask(ZICCLSM) Var(riscv_zi_subext) Mask(ZICCRSE) Var(riscv_zi_subext) +Mask(ZILSD) Var(riscv_zi_subext) + TargetVariable int riscv_za_subext @@ -457,6 +459,8 @@ Mask(ZCMP) Var(riscv_zc_subext) Mask(ZCMT) Var(riscv_zc_subext) +Mask(ZCLSD) Var(riscv_zc_subext) + Mask(XCVBI) Var(riscv_xcv_subext) TargetVariable diff --git a/gcc/testsuite/gcc.target/riscv/arch-45.c b/gcc/testsuite/gcc.target/riscv/arch-45.c new file mode 100644 index 000000000000..2c2598202714 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-45.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zilsd -mabi=ilp32d" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-46.c b/gcc/testsuite/gcc.target/riscv/arch-46.c new file mode 100644 index 000000000000..52b698d83b12 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-46.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zilsd -mabi=ilp32d" } */ +int foo() +{ +} +/* { missing " for " dg-error 6 ".'error: '-march=rv64gc_zilsd': zilsd extension supports in rv32 only " } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-47.c b/gcc/testsuite/gcc.target/riscv/arch-47.c new file mode 100644 index 000000000000..c5544bd4ae61 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-47.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zclsd -mabi=ilp32d" } */ +int foo() +{ +} -- 2.43.0
