Re: [PATCH] [x86] [RFC] Prevent loop vectorization if it's in a deeply nested big loop.

On Fri, Nov 29, 2024 at 2:30 AM Hongtao Liu wrote: > > On Thu, Nov 28, 2024 at 4:57 PM Richard Biener > wrote: > > > > On Thu, Nov 28, 2024 at 3:04 AM Hongtao Liu wrote: > > > > > > On Wed, Nov 27, 2024 at 9:43 PM Richard Biener > > > wrote: > > > > > > > > On Wed, Nov 27, 2024 at 4:26 AM liuho

Re: [PATCH] ifcombine: avoid unsound forwarder-enabled combinations [PR117723]

On Fri, Nov 29, 2024 at 8:59 AM Alexandre Oliva wrote: > > > When ifcombining contiguous blocks, we can follow forwarder blocks and > reverse conditions to enable combinations, but when there are > intervening blocks, we have to constrain ourselves to paths to the > exit that share the PHI args wi

[PATCH] middle-end/117801 - failed register coalescing due to GIMPLE schedule

For a TSVC testcase we see failed register coalescing due to a different schedule of GIMPLE .FMA and stores fed by it. This can be mitigated by making direct internal functions participate in TER - given we're using more and more of such functions to expose target capabilities it seems to be a nat

[PATCH] ext-dce: Fix SIGN_EXTEND handling and cleanups [PR117360]

Hi! This is mostly a blind attempt to fix the PR + various cleanups. The PR is about a shift of a HOST_WIDE_INT by 127 invoking UB. Most of carry_backpropagate works on GET_MODE_INNER of the operand, mode is assigned enum machine_mode mode = GET_MODE_INNER (GET_MODE (x)); at the beginning and e

Re: [PATCH] Fortran: fix crash with bounds check writing array section [PR117791]

../../gcc/fortran/trans-io.cc: In function 'tree_node* gfc_trans_transfer(gfc_code*)': ../../gcc/fortran/trans-io.cc:2662:24: error: enumeration value 'EXPR_UNKNOWN' not handled in switch [-Werror=switch] 2662 | switch (ref->u.ar.start[n]->expr_type) |

Re: [PATCH] Fortran: fix crash with bounds check writing array section [PR117791]

H Harald, hi Paul, Harald Anlauf wrote: Pushed as r15-5766 . This caused a build fail; see also: https://gcc.gnu.org/PR117843 It looks as if a 'default: break;' is missing. …/gcc/fortran/trans-io.cc: In function 'tree_node* gfc_trans_transfer(gfc_code*)': …/gcc/fortran/trans-io.cc:2662:24:

[PATCH] gimple-fold: Fix up type_has_padding_at_level_p [PR117065]

Hi! The following testcase used to ICE on the trunk since the clear small object if it has padding optimization before my r15-5746 change, now it doesn't just because type_has_padding_at_level_p isn't called on the testcase. Though, as the testcase shows, structures/unions which contain erroneous

Re: [PATCH 1/2]middle-end: refactor type to be explicit in operand_equal_p [PR114932]

On Tue, Aug 20, 2024 at 3:07 PM Tamar Christina wrote: > > Hi All, > > This is a refactoring with no expected behavioral change. > The goal with this is to make the type of the expressions being used explicit. > > I did not change all the recursive calls to operand_equal_p () to recurse > directly

Re: [PATCH] gimple-fold: Fix up type_has_padding_at_level_p [PR117065]

On Fri, 29 Nov 2024, Jakub Jelinek wrote: > Hi! > > The following testcase used to ICE on the trunk since the clear small > object if it has padding optimization before my r15-5746 change, > now it doesn't just because type_has_padding_at_level_p isn't called > on the testcase. > > Though, as th

Re: [PATCH] middle-end/117801 - failed register coalescing due to GIMPLE schedule

On Fri, Nov 29, 2024 at 09:19:55AM +0100, Richard Biener wrote: > For a TSVC testcase we see failed register coalescing due to a > different schedule of GIMPLE .FMA and stores fed by it. This > can be mitigated by making direct internal functions participate > in TER - given we're using more and m

Re: [PATCH v3 0/4] Hard Register Constraints

Ping. On Fri, Oct 25, 2024 at 11:57:16AM +0200, Stefan Schulze Frielinghaus wrote: > This is a follow-up to > https://gcc.gnu.org/pipermail/gcc-patches/2024-September/663238.html > > The primary changes are about error handling and documentation updates. > Now, we error out whenever a hard regist

[PUSHED] fortran: Add default to switch in gfc_trans_transfer [PR117843]

This fixes a bootstrap failure due to a warning on enum values not being handled. In this case, it is just checking two values and the rest should are not handled so adding a default case fixes the issue. Pushed as obvious. PR fortran/117843 gcc/fortran/ChangeLog: * trans-io.cc (

Re: [PATCH 2/2]middle-end: use two's complement equality when comparing IVs during candidate selection [PR114932]

On Tue, Aug 20, 2024 at 3:08 PM Tamar Christina wrote: > > Hi All, > > IVOPTS normally uses affine trees to perform comparisons between different > IVs, > but these seem to have been missing in two key spots and instead normal tree > equivalencies used. > > In some cases where we have a two-compl

[PATCH] testsuite: Add check vect_unpack for pr117776.cc [PR117844]

I had missed that you need to check vect_unpack if you are vectorizing a conversion from char to int. Pushed as obvious after a quick test. PR testsuite/117844 gcc/testsuite/ChangeLog: * g++.dg/vect/pr117776.cc: Check vect_unpack. Signed-off-by: Andrew Pinski --- gcc/testsuite

Re: [PATCH v3] MATCH: Simplify `(trunc)copysign ((extend)x, CST)` to `copysign (x, -1.0/1.0)` [PR112472]

On Thu, Nov 14, 2024 at 11:59 AM Eikansh Gupta wrote: > > This patch simplify `(trunc)copysign ((extend)x, CST)` to `copysign (x, > -1.0/1.0)` > depending on the sign of CST. Previously, it was simplified to `copysign (x, > CST)`. > It can be optimized as the sign of the CST matters, not the val

Re: [PATCH v3] c++, coroutines: Fix awaiter var creation [PR116506].

Hi Jason, gentle ping for this one (sorry I forgot to ping earlier and then WG21 …) > On 31 Oct 2024, at 08:40, Iain Sandoe wrote: > > This version tested on x86_64-darwin,linux, powerpc64-linux, on folly > and by Sam on wider codebases, > Why don't you need a variable to preserve o acro

Re: [PATCH] middle-end/117801 - failed register coalescing due to GIMPLE schedule

On Fri, 29 Nov 2024, Jakub Jelinek wrote: > On Fri, Nov 29, 2024 at 09:19:55AM +0100, Richard Biener wrote: > > For a TSVC testcase we see failed register coalescing due to a > > different schedule of GIMPLE .FMA and stores fed by it. This > > can be mitigated by making direct internal functions

[PATCH 1/3] arm, mve: Fix scan-assembler for test7 in dlstp-compile-asm-2.c

After the changes to the vctp intrinsic codegen changed slightly, where we now unfortunately seem to be generating unneeded moves and extends of the mask. These are however not incorrect and we don't have a fix for the unneeded codegen right now, so changing the testcase to accept them so we can c

[PATCH 0/3] arm, mve: Fix DLSTP testism and issue after changes in codegen

This patch series does not really need to be a patch series but just makes it easier to send it all and has one common goal which is to clean up the DLSTP implementation new to GCC 16 after some codegen changes. The first two patches clean-up some testcases and the last fixes an actual issue that h

[PATCH 2/3] arm, mve: Pass -std=c99 to dlstp-loop-form.c to avoid new warning

This fixes a testism introduced by the warning produced with the -std=c23 default. The testcase is a reduced piece of code meant to trigger an ICE, so there's little value in trying to change the code itself. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/dlstp-loop-form.c: Add -std=c99

[PATCH 3/3] arm, mve: Detect uses of vctp_vpr_generated inside subregs

Address a problem we were having where we were missing on detecting uses of vctp_vpr_generated in the analysis for 'arm_attempt_dlstp_transform' because the use was inside a SUBREG and rtx_equal_p does not catch that. Using reg_overlap_mentioned_p is much more robust. gcc/ChangeLog: * g

Re: [PATCH] arm, mve: Do not DLSTP transform loops if VCTP is not first

Hi Christophe, On 28/11/2024 17:00, Christophe Lyon wrote: Hi Andre, Thanks, the patch LGTM except a minor nit: /* Using a VPR that gets re-generated within the loop. */ -void test10 (int32_t *a, int32_t *b, int32_t *c, int n) +void test10a (int32_t *a, int32_t *b, int32_t *c, int n) [...]

Re: [PATCH 1/3] arm, mve: Fix scan-assembler for test7 in dlstp-compile-asm-2.c

On 11/29/24 11:30, Andre Vieira wrote: After the changes to the vctp intrinsic codegen changed slightly, where we now unfortunately seem to be generating unneeded moves and extends of the mask. These are however not incorrect and we don't have a fix for the unneeded codegen right now, so chan

Re: [PATCH 2/3] arm, mve: Pass -std=c99 to dlstp-loop-form.c to avoid new warning

On 11/29/24 11:30, Andre Vieira wrote: This fixes a testism introduced by the warning produced with the -std=c23 default. The testcase is a reduced piece of code meant to trigger an ICE, so there's little value in trying to change the code itself. gcc/testsuite/ChangeLog: * gcc.tar

Re: [PATCH 3/3] arm, mve: Detect uses of vctp_vpr_generated inside subregs

On 11/29/24 11:30, Andre Vieira wrote: Address a problem we were having where we were missing on detecting uses of vctp_vpr_generated in the analysis for 'arm_attempt_dlstp_transform' because the use was inside a SUBREG and rtx_equal_p does not catch that. Using reg_overlap_mentioned_p is mu

Re: [PATCH 0/3] arm, mve: Fix DLSTP testism and issue after changes in codegen

On 11/29/24 11:30, Andre Vieira wrote: This patch series does not really need to be a patch series but just makes it easier to send it all and has one common goal which is to clean up the DLSTP implementation new to GCC 16 after some codegen changes. The first two patches clean-up some testcas

Re: [PATCH]AArch64 Suppress default options when march or mcpu used is not affected by it.

Hi Tamar, > On 15 Nov 2024, at 14:24, Tamar Christina wrote: > > Hi All, > > This patch makes it so that when you use any of the Cortex-A53 errata > workarounds but have specified an -march or -mcpu we know is not affected by > it > that we suppress the errata workaround. > > This is a driver

RE: [PATCH]AArch64 Suppress default options when march or mcpu used is not affected by it.

Hi Kyril, Thanks for the review, unfortunately this is an old version of the patch, I sent a new one on Thu 11/21/2024 with updates and automated tests. Would you mind reviewing that one? I've noted the documentation comment you mentioned :) Thanks, Tamar > -Original Message- > From:

Re: [PATCH]AArch64 Suppress default options when march or mcpu used is not affected by it.

> On 21 Nov 2024, at 10:13, Tamar Christina wrote: > >>> I tried writing automated testcases for these, however the testsuite doesn't >>> want to scan the output of -### and it makes the excess error tests always >>> fail >>> unless you use dg-error, which also looks for"error:". So tested ma

Re: [PATCH 1/3] aarch64: Fix up flags for vget_low_*, vget_high_* and vreinterpret intrinsics

Andrew Pinski writes: > These 3 intrinsics will not raise an fp exception, or read FPCR. These > intrinsics, > will be folded into VIEW_CONVERT_EXPR or a BIT_FIELD_REF which is already set > to > be const expressions too. > > Built and tested for aarch64-linux-gnu. > > gcc/ChangeLog: > > *

Re: [PATCH]AArch64 Suppress default options when march or mcpu used is not affected by it.

Hi Tamar, > On 29 Nov 2024, at 11:25, Tamar Christina wrote: > > Hi Kyril, > > Thanks for the review, unfortunately this is an old version of the patch, I > sent a new one on Thu 11/21/2024 > with updates and automated tests. > > Would you mind reviewing that one? I've noted the documentatio

Re: [PATCH 2/3] aarch64: add attributes to the prefetch_builtins

Andrew Pinski writes: > This adds the attributes associated with prefetch to the bultins. > Just call aarch64_get_attributes with FLAG_PREFETCH_MEMORY to get the > attributes. > > Built and tested for aarch64-linux-gnu. > > gcc/ChangeLog: > > * config/aarch64/aarch64-builtins.cc (aarch64_in

Re: [PATCH 3/3] aarch64: Add attributes to the data intrinsics.

Andrew Pinski writes: > All of the data intrinsics don't read/write memory nor they are fp related. > So adding the attributes will improve the code generation slightly. > > Built and tested for aarch64-linux-gnu > > gcc/ChangeLog: > > * config/aarch64/aarch64-builtins.cc (aarch64_init_data_

Re: [PATCH v2 0/8] aarch64: Enable C/C++ operations on SVE ACLE types.

On 11/18/24 7:09 PM, Richard Sandiford wrote: Tejas Belagod writes: Hi, This is v2 of the series https://gcc.gnu.org/pipermail/gcc-patches/2024-November/667743.html based on review comments. Changes in this version include: 1. Canonicalised all index ranges for VLAs to BIT_FIELD_REF. 2. A

Re: [PATCH] aarch64: Mark __builtin_aarch64_im_lane_boundsi as leaf and nothrow [PR117665]

Andrew Pinski writes: > __builtin_aarch64_im_lane_boundsi is known not to throw or call back into > another > function since it will either folded into an NOP or will produce a compiler > error. > > This fixes the ICE by fixing the missed optimization. It does not fix the > underlying > issue w

Re: [PATCH] wwwdocs: Align the DCO text for the GNU Toolchain to match community usage.

On 11/21/24 12:04 PM, Carlos O'Donell wrote: > Adjust the DCO text to match the broader community usage including > the Linux kernel use around "real names." Ping. :-) The glibc contribution checklist text has been updated: https://sourceware.org/glibc/wiki/Contribution%20checklist The binutils

[PATCH v1] Match: Refactor the unsigned SAT_SUB match patterns [NFC]

From: Pan Li This patch would like to refactor the all unsigned SAT_SUB patterns, aka: * Extract type check outside. * Re-arrange the related match pattern forms together. The below test suites are passed for this patch. * The rv64gcv fully regression test. * The x86 bootstrap test. * The x86 fu

Re: [PATCH] arm, testsuite: Adjust Arm tests after c23 changes

FTR this patch is superseded by Andre's patch: https://gcc.gnu.org/pipermail/gcc-patches/2024-November/670378.html On Thu, 28 Nov 2024 at 11:12, Christophe Lyon wrote: > > After the recent c23, GCC complains because the testcase calls f() > with a parameter whereas the prototype has none. > >

[PATCH] tree-optimization/115438 - SLP reduction vect vs. bwaves

503.bwaves_r shows a case where the non-SLP optimization of performing the reduction adjustment with the initial value as part of the epilogue rather than including it as part of the initial vector value. It allows to break a critical dependence path. The following restores this ability for singl

Re: [PATCH v5 5/5] aarch64: add SVE2 FP8DOT2 and FP8DOT4 intrinsics

Thanks for the update! Claudio Bantaloukas writes: > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index 2a4f016e2df..f7440113570 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -21957,6 +21957,18 @@ Enable the fp8 (8-bit floating point) multiply > accumulate exten

[PATCH] aarch64: Add ISA requirements to some SVE/SME md comments

Kyrylo Tkachov writes: > Hi Richard >> On 6 Nov 2024, at 18:16, Richard Sandiford wrote: >> >> This series adds support for FEAT_SVE2p1 (-march=...+sve2p1). >> One thing that the extension does is make some SME and SME2 instructions >> available outside of streaming mode. It also adds quite a f

RE: [PATCH v2 4/4] vect: Disable `omp declare variant' tests for aarch64

Ping, I'm filling in for Victor on the patch series. Regards, Tamar > -Original Message- > From: Victor Do Nascimento > Sent: Tuesday, November 5, 2024 12:38 AM > To: gcc-patches@gcc.gnu.org > Cc: ja...@redhat.com > Subject: Re: [PATCH v2 4/4] vect: Disable `omp declare variant' tests f

Re: [PATCH] aarch64: Extend SVE2 bit-select instructions for Neon modes.

Kyrylo Tkachov writes: >> On 27 Nov 2024, at 09:34, Richard Sandiford >> wrote: >> >> Soumya AR writes: >>> NBSL, BSL1N, and BSL2N are bit-select intructions on SVE2 with certain >>> operands >>> inverted. These can be extended to work with Neon modes. >>> >>> Since these instructions are un

Re: [PATCH] c++, v2: Implement C++26 P3176R1 - The Oxford variadic comma

On 11/26/24 5:27 AM, Jonathan Wakely wrote: On Tue, 26 Nov 2024 at 08:34, Jakub Jelinek wrote: On Mon, Nov 25, 2024 at 03:40:18PM -0500, Marek Polacek wrote: Just "omitting a comma", I think. "of a function parameter list" I suppose we should also test -Wno-deprecated and/or -Wno-deprecated

[PATCH] c++, coroutines: Make suspend index consistent for debug.

Tested on x86_64-darwin, x86_64-linux, OK for trunk? thanks Iain --- 8< --- At present, we only update the suspend index when we actually are at the stage that the coroutine is considered suspended. This is on the basis that it is UB to resume or destroy a coroutines that is not suspended (and th

[PATCH] c++, coroutines: Handle statement expressions part 1.

Tested on x86_64-darwin, x86_64/powerpc64-linux, on folly and more widely by Sam. There are possibly additional BZ dups that will be covered (this fixes 117231, a P1). OK for trunk? thanks Iain --- 8< --- In the current implementation, statement expressions were intentionally unsupported (as a C

[PATCH] c++, coroutines:Ensure bind exprs are visited once [PR98935].

Tested on x86_64-darwin, x86_64, powerpc64-linux, OK for trunk? thanks Iain --- 8< --- Recent changes in the C++ FE and the coroutines implementation have exposed a latent issue in which a bind expression containing a var that we need to capture in the coroutine state gets visited twice. This cau

Re: [PATCH v5 5/5] aarch64: add SVE2 FP8DOT2 and FP8DOT4 intrinsics

On 11/29/2024 1:00 PM, Richard Sandiford wrote: Thanks for the update! Claudio Bantaloukas writes: diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 2a4f016e2df..f7440113570 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -21957,6 +21957,18 @@ Enable the fp8 (8-bit

[PATCH] aarch64: Fix bootstrap build failure due to missing header

Inclusion of "arm_acle.h" would requires stdint.h that may not be available during first stage of cross-compilation. libgcc/ChangeLog: * config/aarch64/aarch64-unwind.h (_CHKFEAT_GCS): Add. --- Regression tested on aarch64-unknown-linux-gnu and no regressions have been found. Is this

Re: [PATCH] aarch64: Add ISA requirements to some SVE/SME md comments

> On 29 Nov 2024, at 13:04, Richard Sandiford wrote: > > Kyrylo Tkachov writes: >> Hi Richard >>> On 6 Nov 2024, at 18:16, Richard Sandiford >>> wrote: >>> >>> This series adds support for FEAT_SVE2p1 (-march=...+sve2p1). >>> One thing that the extension does is make some SME and SME2 instr

[PATCH] c++, v3: Implement C++26 P3176R1 - The Oxford variadic comma

On Fri, Nov 29, 2024 at 08:36:21AM -0500, Jason Merrill wrote: > > This should be either "omission of ',' before" or "omitting ',' before" > > > > But not "omitting of" :-) > > Agreed. Picked omission of. > I also might say "varargs" instead of "variadic", since the latter could > also refer to

Re: [PATCH] aarch64: Fix bootstrap build failure due to missing header

Hi Yury, > On 29 Nov 2024, at 13:57, Yury Khrustalev wrote: > > Inclusion of "arm_acle.h" would requires stdint.h that may > not be available during first stage of cross-compilation. Do you mean when trying to build a big-endian cross-compiler or something? The change seems harmless to me but t

Re: [PATCH] libgccjit: Add support for machine-dependent builtins

Oh, nice. I'll send my future patches on the forgejo instance, then. Le 2024-11-20 à 17 h 35, Mark Wielaard a écrit : Hi Antoni, On Wed, Nov 20, 2024 at 11:11:01AM -0500, Antoni Boucher wrote: From what I understand, pull requests on forge.sourceware.org can be removed at any time, so I coul

[PATCH v2 1/3] arm, mve: Fix scan-assembler for test7 in dlstp-compile-asm-2.c

After the changes to the vctp intrinsic codegen changed slightly, where we now unfortunately seem to be generating unneeded moves and extends of the mask. These are however not incorrect and we don't have a fix for the unneeded codegen right now, so changing the testcase to accept them so we can c

Re: [PATCH v5 5/5] aarch64: add SVE2 FP8DOT2 and FP8DOT4 intrinsics

> On 29 Nov 2024, at 13:00, Richard Sandiford wrote: > > Thanks for the update! > > Claudio Bantaloukas writes: >> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi >> index 2a4f016e2df..f7440113570 100644 >> --- a/gcc/doc/invoke.texi >> +++ b/gcc/doc/invoke.texi >> @@ -21957,6 +21957,18

[PATCH v2 3/3] arm, mve: Detect uses of vctp_vpr_generated inside subregs

Address a problem we were having where we were missing on detecting uses of vctp_vpr_generated in the analysis for 'arm_attempt_dlstp_transform' because the use was inside a SUBREG and rtx_equal_p does not catch that. Using reg_overlap_mentioned_p is much more robust. gcc/ChangeLog: PR

Re: [PATCH v3] arm: [MVE intrinsics] Fix support for predicate constants [PR target/114801]

Hi, On Mon, 25 Nov 2024 at 21:08, Christophe Lyon wrote: > > In this PR, we have to handle a case where MVE predicates are supplied > as a const_int, where individual predicates have illegal boolean > values (such as 0xc for a 4-bit boolean predicate). To avoid the ICE, > fix the constant (any n

Re: [PATCH v5 5/5] aarch64: add SVE2 FP8DOT2 and FP8DOT4 intrinsics

On 11/29/2024 2:15 PM, Kyrylo Tkachov wrote: On 29 Nov 2024, at 13:00, Richard Sandiford wrote: Thanks for the update! Claudio Bantaloukas writes: diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 2a4f016e2df..f7440113570 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke

Re: [PATCH] aarch64: Fix bootstrap build failure due to missing header

Hi Kyrill, On Fri, Nov 29, 2024 at 02:06:17PM +, Kyrylo Tkachov wrote: > Hi Yury, > > > On 29 Nov 2024, at 13:57, Yury Khrustalev wrote: > > > > Inclusion of "arm_acle.h" would requires stdint.h that may > > not be available during first stage of cross-compilation. > > Do you mean when try

Re: [PATCH] c++, v3: Implement C++26 P3176R1 - The Oxford variadic comma

On 11/29/24 8:55 AM, Jakub Jelinek wrote: On Fri, Nov 29, 2024 at 08:36:21AM -0500, Jason Merrill wrote: This should be either "omission of ',' before" or "omitting ',' before" But not "omitting of" :-) Agreed. Picked omission of. I also might say "varargs" instead of "variadic", since th

Re: [PATCH] aarch64: Fix bootstrap build failure due to missing header

> On 29 Nov 2024, at 14:25, Yury Khrustalev wrote: > > Hi Kyrill, > > On Fri, Nov 29, 2024 at 02:06:17PM +, Kyrylo Tkachov wrote: >> Hi Yury, >> >>> On 29 Nov 2024, at 13:57, Yury Khrustalev wrote: >>> >>> Inclusion of "arm_acle.h" would requires stdint.h that may >>> not be available d

[PATCH] c++: Make sure fold_sizeof_expr returns the correct type [PR117775]

We currently ICE upon the following code, that is valid under -Wno-pointer-arith: === cut here === int main() { decltype( [](auto) { return sizeof(void); } ) x; return x.operator()(0); } === cut here === The problem is that "fold_sizeof_expr (sizeof(void))" returns size_one_node, that has a d

Re: [PATCH] Introduce feeble_inline attribute [PR93008]

On 11/28/24 7:57 AM, Jan Hubicka wrote: I think a 4 state flag { never_inline, default, auto_inline, always_inline } would be fine. The question is how to call the macro(s) and values and how to merge those from different decls and what we do currently e.g. for noinline, always_inline, on the s

RE: [RFC] PR81358: Enable automatic linking of libatomic

> -Original Message- > From: Joseph Myers > Sent: 28 November 2024 05:45 > To: Prathamesh Kulkarni > Cc: Xi Ruoyao ; Matthew Malcomson > ; gcc-patches@gcc.gnu.org > Subject: RE: [RFC] PR81358: Enable automatic linking of libatomic > > External email: Use caution opening links or attach

[PATCH v2] aarch64: Fix build failure due to missing header

Including the "arm_acle.h" header in aarch64-unwind.h requires stdint.h to be present and it may not be available during the first stage of cross-compilation of GCC. When cross-building GCC for the aarch64-none-linux-gnu target (on any supporting host) using the 3-stage bootstrap build process whe

[PATCH] libstdc++: Hide TLS variables in `std::call_once`

-- Best regards, LIU Hao From 78ae9cacdfea8bab4fcc8a18068ad30401eb588d Mon Sep 17 00:00:00 2001 From: LIU Hao Date: Fri, 29 Nov 2024 17:17:01 +0800 Subject: [PATCH] libstdc++: Hide TLS variables in `std::call_once` This is a transitional change for PR80881, because on Windows, thread-local var

Re: [PATCH] aarch64: Fix bootstrap build failure due to missing header

On Fri, Nov 29, 2024 at 02:31:34PM +, Kyrylo Tkachov wrote: > > > Would you recommend to re-phrase the commit message? > > Thanks for explaining. Yes, I think describing the use case a bit more in the > commit message like you just did would be useful. > Ok with that change. > Kyrill Thanks

[PATCH v7 03/12] RISC-V: Add CRC expander to generate faster CRC.

This is parts of patches #3 and #4 from Mariam's series. Specifically it introduces an expander in the RISC-V backend that can generate a CRC using a clmul based sequence. It also has support for exploiting zbkb if we need to reflect values. I'm explicitly not including most of the tests. E

Re: [PATCH] libstdc++: Hide TLS variables in `std::call_once`

The change seems reasonable but this needs a change to config/abi/pre/gnu.ver to export the new symbol in the GLIBCXX_3.4.34 version. Please add full stops (periods) to the ChangeLog entry, to make complete sentences. Is "PR libstdc++/, target/" valid like that? I don't think it is, it sh

Re: [PATCH] libstdc++: Hide TLS variables in `std::call_once`

在 2024-11-29 23:08, Jonathan Wakely 写道: The change seems reasonable but this needs a change to config/abi/pre/gnu.ver to export the new symbol in the GLIBCXX_3.4.34 version. I have added it in the attached patch. However it exists only if `_GLIBCXX_HAVE_TLS` is defined, so seems to require an

Re: [PATCH v2 1/3] arm, mve: Fix scan-assembler for test7 in dlstp-compile-asm-2.c

On 11/29/24 15:14, Andre Vieira wrote: After the changes to the vctp intrinsic codegen changed slightly, where we now unfortunately seem to be generating unneeded moves and extends of the mask. These are however not incorrect and we don't have a fix for the unneeded codegen right now, so chan

Re: [PATCH] libstdc++: Hide TLS variables in `std::call_once`

On Fri, 29 Nov 2024 at 15:31, LIU Hao wrote: > > 在 2024-11-29 23:08, Jonathan Wakely 写道: > > The change seems reasonable but this needs a change to > > config/abi/pre/gnu.ver to export the new symbol in the GLIBCXX_3.4.34 > > version. > > I have added it in the attached patch. However it exists on

Re: [PATCH] libstdc++: Hide TLS variables in `std::call_once`

On Fri, 29 Nov 2024 at 15:49, Jonathan Wakely wrote: > > On Fri, 29 Nov 2024 at 15:31, LIU Hao wrote: > > > > 在 2024-11-29 23:08, Jonathan Wakely 写道: > > > The change seems reasonable but this needs a change to > > > config/abi/pre/gnu.ver to export the new symbol in the GLIBCXX_3.4.34 > > > vers

Re: [PATCH v2 3/3] arm, mve: Detect uses of vctp_vpr_generated inside subregs

On 11/29/24 15:15, Andre Vieira wrote: Address a problem we were having where we were missing on detecting uses of vctp_vpr_generated in the analysis for 'arm_attempt_dlstp_transform' because the use was inside a SUBREG and rtx_equal_p does not catch that. Using reg_overlap_mentioned_p is mu

Re: [PATCH] libstdc++: Hide TLS variables in `std::call_once`

在 2024-11-29 23:50, Jonathan Wakely 写道: It looks like your patch is against gcc-14 not trunk, the GLIBCXX_15.1.0 version is already there. Sorry, I mean GLIBCXX_3.4.34 for 15.1.0 Oops that's what I used to test the patch. Reapplied to master now. -- Best regards, LIU Hao From bafa1604e632d6

[C PATCH] c: Set attributes for fields when forming a composite type [PR117806]

It seems we also miss a decl_attributes call for the fields when building the composite type. Bootstrapped and regression tested on x86_64. c: Set attributes for fields when forming a composite type [PR117806] We need to call decl_attributes when creating the fields for a composi

Re: [PATCH] libstdc++: Make std::basic_stacktrace swappable with unequal allocators

On Thu, 28 Nov 2024 at 18:59, Jonathan Wakely wrote: > > The standard says that it's undefined to swap two containers if the > allocators are not equal and do not propagate. This ensures that swap is > always O(1) and non-throwing, but has other undesirable consequences > such as LWG 2152. The 201

RE: [RFC] PR81358: Enable automatic linking of libatomic

On Fri, 29 Nov 2024, Prathamesh Kulkarni wrote: > > My expectation is that CFLAGS should not be modified until after > > save_CFLAGS is set, which should not be until after configure has > > executed the logic that sets a -g -O2 default. Is there some problem > > with that ordering (e.g. configur

Re: [PATCH v2] aarch64: Fix build failure due to missing header

> On 29 Nov 2024, at 14:49, Yury Khrustalev wrote: > > Including the "arm_acle.h" header in aarch64-unwind.h requires > stdint.h to be present and it may not be available during the > first stage of cross-compilation of GCC. > > When cross-building GCC for the aarch64-none-linux-gnu target >

Re: [PATCH] libstdc++: Make std::basic_stacktrace swappable with unequal allocators

Patch v2 fixes the bug in the slow path for swap, and improves the test so that it fails with the old buggy code. commit 44214429d428f4fe5a148c7636b844600a10f9a4 Author: Jonathan Wakely Date: Thu Nov 28 13:59:09 2024 libstdc++: Make std::basic_stacktrace swappable with unequal allocators

[Patch, fortran] PR102689 revisited - Segfault with RESHAPE of CLASS as actual argument

Hi All, This patch was originally pushed as r15-2739. Subsequently memory faults were found and so the patch was reverted. At the time, I could find where the problem lay. This morning I had another look and found it almost immediately :-) The fix is the 'gfc_resize_class_size_with_len' in the ch

[patch,avr] PR117726: Post-reload split 2-byte and 3-byte shifts

This patch splits 2-byte and 3-byte shifts after reload into a 3-operand byte shift and a residual 2-operand shift. The "2op" shift insn alternatives are not needed and removed because all shift insn already have a "r,0,n" alternative that does the job. Ok for trunk? Johann -- AVR: target/11

Re: [PUSHED] fortran: Add default to switch in gfc_trans_transfer [PR117843]

Thanks, Andrew, for fixing this! I did not get any reports from the pre-commit testers; I only saw the fallout later. And sorry for breaking bootstrap! Harald Am 29.11.24 um 10:16 schrieb Andrew Pinski: This fixes a bootstrap failure due to a warning on enum values not being handled. In this

Re: [Patch, fortran] PR102689 revisited - Segfault with RESHAPE of CLASS as actual argument

Hi Paul, the patch seems to contain stuff that has already been pushed (gcc/testsuite/gfortran.dg/pr117768.f90, and the chunks in class.cc and resolve.cc). Can you please check? Cheers, Harald Am 29.11.24 um 17:34 schrieb Paul Richard Thomas: Hi All, This patch was originally pushed as r15-2

[patch,avr] Fix PR117681 build warning for libgcc/unwind-sjlj.c

This patch fixes a build warning for libgcc/unwind-sjlj.c which used word_mode for _Unwind_Word but should use Pmode. Ok for trunk? Johann -- AVR: target/117681 - Set UNWIND_WORD_MODE to Pmode. This patch fixes a build warning for libgcc/unwind-sjlj.c which used word_mode for _Unwind_Word but

Re: [patch,avr] Fix PR11768 build warning for libgcc/unwind-sjlj.c

пт, 29 нояб. 2024 г. в 21:33, Georg-Johann Lay : > > This patch fixes a build warning for libgcc/unwind-sjlj.c > which used word_mode for _Unwind_Word but should use Pmode. > > Ok for trunk? Ok. Please apply. Denis. > > Johann > > -- > > AVR: target/117681 - Set UNWIND_WORD_MODE to Pmode. > > Th

Re: [patch,avr] PR117726: Post-reload split 2-byte and 3-byte shifts

пт, 29 нояб. 2024 г. в 21:07, Georg-Johann Lay : > > This patch splits 2-byte and 3-byte shifts after reload into > a 3-operand byte shift and a residual 2-operand shift. > > The "2op" shift insn alternatives are not needed and removed because > all shift insn already have a "r,0,n" alternative tha

Re: [C PATCH] c: Set attributes for fields when forming a composite type [PR117806]

On Fri, 29 Nov 2024, Martin Uecker wrote: > It seems we also miss a decl_attributes call for the fields > when building the composite type. > > > Bootstrapped and regression tested on x86_64. > > > c: Set attributes for fields when forming a composite type [PR117806] > > We need t

[PATCH 2/2] libstdc++: Move std::monostate to for C++26 (P0472R2)

Another C++26 paper just approved in Wrocław. The std::monostate class is defined in since C++17, but for C++26 it should also be available in . libstdc++-v3/ChangeLog: * include/Makefile.am: Add bits/monostate.h. * include/Makefile.in: Regenerate. * include/std/utility:

Re: [PATCH v3 2/8] aarch64: Make C/C++ operations possible on SVE ACLE types.

Hi! On Fri, 29 Nov 2024 at 05:00, Tejas Belagod wrote: > > This patch changes the TYPE_INDIVISBLE flag to 0 to enable SVE ACLE types to > be > treated as GNU vectors and have the same semantics with operations that are > defined on GNU vectors. > > gcc/ChangeLog: > > * config/aarch64/aar

Re: [Patch, fortran] PR102689 revisited - Segfault with RESHAPE of CLASS as actual argument

Hi Harald, Sorry about that - it was the standard HEAD versus HEAD~ mistake. Thanks for pointing it out. Paul On Fri, 29 Nov 2024 at 17:31, Harald Anlauf wrote: > Hi Paul, > > the patch seems to contain stuff that has already been pushed > (gcc/testsuite/gfortran.dg/pr117768.f90, and the chu

[PATCH 1/2] libstdc++: Improve test for synopsis

libstdc++-v3/ChangeLog: * testsuite/20_util/headers/utility/synopsis.cc: Add declarations from C++11 and later. --- It's a bit messy with all the macros, but I think it's still better to have one test that runs as every -std mode than having 4+ tests that are only valid in one or

[pushed][PR117770][LRA]: Check hard regs corresponding insn operands for hard reg clobbers

The following patch solves https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117770 The patch was successfully tested and bootstrapped on x864_64, aarch64, ppc64le.

Re: gimplify: Handle void BIND_EXPR as asm input [PR100501]

On Fri, 29 Nov 2024, Richard Biener wrote: > I think we're trying to handle errorneous cases by setting TREE_VALUE > to error_mark_node > before this, so how about the following instead? Yes, that works, and also fixes the test in bug 100792 unlike my previous patch. Here's a full, tested patch

Re: [PATCH] ext-dce: Fix SIGN_EXTEND handling and cleanups [PR117360]

On 11/29/24 1:43 AM, Jakub Jelinek wrote: Hi! This is mostly a blind attempt to fix the PR + various cleanups. The PR is about a shift of a HOST_WIDE_INT by 127 invoking UB. Most of carry_backpropagate works on GET_MODE_INNER of the operand, mode is assigned enum machine_mode mode = GET_M

Re: [PATCH] PR target/117669 - RISC-V:The 'VEEWTRUNC4' iterator 'RVVMF2BF' type condition error

On Wed, 20 Nov 2024, Feng Wang wrote: > This patch fix the wrong condition for RVVMF2BF. It should be > TARGET_VECTOR_ELEN_BF_16. > gcc/ChangeLog: > > PR target/117669 > * config/riscv/vector-iterators.md: > > Signed-off-by: Feng Wang There's missing text after the ":", where one w

Re: [PATCH 1/2] c++: some further concepts cleanups

On 11/27/24 2:41 PM, Patrick Palka wrote: On Tue, 5 Nov 2024, Jason Merrill wrote: On 10/15/24 12:45 AM, Patrick Palka wrote: This patch further cleans up the concepts code following the removal of Concepts TS support: * concept-ids are now the only kind of "concept check", so we can

[PATCH] gimplefe: Error recovery for invalid declarations [PR117749]

c_parser_declarator can return null if there was an error, but c_parser_gimple_declaration was not ready for that. This fixes that oversight so we don't get an ICE after the error. Bootstrapped and tested on x86_64-linux-gnu. PR c/117749 gcc/c/ChangeLog: * gimple-parser.cc (c_pa

Re: [PATCH] gimplefe: Error recovery for invalid declarations [PR117749]

> Am 30.11.2024 um 05:44 schrieb Andrew Pinski : > > c_parser_declarator can return null if there was an error, > but c_parser_gimple_declaration was not ready for that. > This fixes that oversight so we don't get an ICE after the error. > > Bootstrapped and tested on x86_64-linux-gnu. Ok R

Go patch committed: Work around warning to fix bootstrap

This patch to the Go frontend increases the size of a temporary buffer to avoid a new warning. The warning was breaking bootstrapping with Go. GCC has a new -Wformat-truncation warning that triggers on some Go frontend code: ../../gcc/go/gofrontend/go-encode-id.cc: In function 'std::string go_en

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