Thanks for the update! Claudio Bantaloukas <claudio.bantalou...@arm.com> writes: > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index 2a4f016e2df..f7440113570 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -21957,6 +21957,18 @@ Enable the fp8 (8-bit floating point) multiply > accumulate extension. > @item ssve-fp8fma > Enable the fp8 (8-bit floating point) multiply accumulate extension in > streaming > mode. > +@item fp8dot4 > +Enable the fp8 (8-bit floating point) to single-precision 4-way dot product > +extension. > +@item ssve-fp8dot4 > +Enable the fp8 (8-bit floating point) to single-precision 4-way dot product > +extension in streaming mode. > +@item fp8dot2 > +Enable the fp8 (8-bit floating point) o half-precision 2-way dot product > +extension.
typo: s/o/to/ (and below). Since the change is so trivial, I made it locally, tweaked the ordering of the svcvt entries in patch 3, and fixed some whitespace issues that git am was complaining about. Push to trunk with those changes. Now that you've had at least two series applied, could you follow the process on https://gcc.gnu.org/gitwrite.html to get write access for future patches? (I'll sponsor.) Thanks, Richard > +@item ssve-fp8dot2 > +Enable the fp8 (8-bit floating point) o half-precision 2-way dot product > +extension in streaming mode. > @item faminmax > Enable the Floating Point Absolute Maximum/Minimum extension. > @item sve-b16b16 > diff --git > a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_1.c > b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_1.c > new file mode 100644 > index 00000000000..9ad789a8ad2 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_1.c > @@ -0,0 +1,33 @@ > +/* { dg-do compile } */ > + > +#include <arm_sve.h> > + > +#pragma GCC target ("arch=armv8.2-a+sve2+fp8dot2") > + > +void > +test (svfloat16_t f16, svmfloat8_t f8, fpm_t fpm, > + svbool_t pg, svuint8_t u8, svuint16_t u16, svint32_t s32, > + svbfloat16_t bf16, svfloat32_t f32, svfloat64_t f64, mfloat8_t f) > +{ > + svdot_fpm (f16, f8, f8, fpm); > + svdot_fpm (f32, f8, f8, fpm); > + > + svdot_fpm (f16); /* { dg-error {too few arguments to function 'svdot_fpm'} > } */ > + svdot_fpm (f16, f8); /* { dg-error {too few arguments to function > 'svdot_fpm'} } */ > + svdot_fpm (f16, f8, f8); /* { dg-error {too few arguments to function > 'svdot_fpm'} } */ > + svdot_fpm (f8, f8, fpm); /* { dg-error {too few arguments to function > 'svdot_fpm'} } */ > + svdot_fpm (f16, f8, fpm); /* { dg-error {too few arguments to function > 'svdot_fpm'} } */ > + svdot_fpm (f16, f8, f8, fpm, 0); /* { dg-error {too many arguments to > function 'svdot_fpm'} } */ > + > + svdot_fpm (0, f8, f8, fpm); /* { dg-error {passing 'int' to argument 1 of > 'svdot_fpm', which expects an SVE type rather than a scalar} } */ > + svdot_fpm (f16, f8, f, fpm); /* { dg-error {passing 'mfloat8_t' {aka > '__mfp8'} to argument 3 of 'svdot_fpm', which expects 'svmfloat8_t'} } */ > + svdot_fpm (pg, f8, f8, fpm); /* { dg-error {'svdot_fpm' has no form that > takes 'svbool_t' and 'svmfloat8_t' arguments} } */ > + svdot_fpm (u8, f8, f8, fpm); /* { dg-error {'svdot_fpm' has no form that > takes 'svuint8_t' and 'svmfloat8_t' arguments} } */ > + svdot_fpm (u16, f8, f8, fpm); /* { dg-error {'svdot_fpm' has no form that > takes 'svuint16_t' and 'svmfloat8_t' arguments} } */ > + svdot_fpm (f64, f8, f8, fpm); /* { dg-error {'svdot_fpm' has no form that > takes 'svfloat64_t' and 'svmfloat8_t' arguments} } */ > + svdot_fpm (f16, 0, f8, fpm); /* { dg-error {passing 'int' to argument 2 of > 'svdot_fpm', which expects 'svmfloat8_t'} } */ > + svdot_fpm (f16, f16, f8, fpm); /* { dg-error {passing 'svfloat16_t' to > argument 2 of 'svdot_fpm', which expects 'svmfloat8_t'} } */ > + svdot_fpm (f16, f8, 0, fpm); /* { dg-error {passing 'int' to argument 3 of > 'svdot_fpm', which expects 'svmfloat8_t'} } */ > + svdot_fpm (f16, f8, f16, fpm); /* { dg-error {passing 'svfloat16_t' to > argument 3 of 'svdot_fpm', which expects 'svmfloat8_t'} } */ > + svdot_fpm (f16, f8, f8, f8); /* { dg-error {passing 'svmfloat8_t' to > argument 4 of 'svdot_fpm', which expects 'uint64_t'} } */ > +} > diff --git > a/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_lane_group_selection_1.c > > b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_lane_group_selection_1.c > new file mode 100644 > index 00000000000..dec00e3abf1 > --- /dev/null > +++ > b/gcc/testsuite/gcc.target/aarch64/sve/acle/general-c/ternary_mfloat8_lane_group_selection_1.c > @@ -0,0 +1,49 @@ > +/* { dg-do compile } */ > + > +#include <arm_sve.h> > + > +#pragma GCC target ("arch=armv8.2-a+ssve-fp8fma+ssve-fp8dot2") > + > +void > +f1 (svfloat16_t f16, svmfloat8_t f8, fpm_t fpm, > + svbool_t pg, svuint8_t u8, svuint16_t u16, svint32_t s32, > + svbfloat16_t bf16, svfloat32_t f32, svfloat64_t f64, mfloat8_t f, int i) > + __arm_streaming > +{ > + svdot_lane_fpm (f32, f8, f8, 0, fpm); > + svdot_lane_fpm (f32, f8, f8, 3, fpm); > + svdot_lane_fpm (f16, f8, f8, 0, fpm); > + svdot_lane_fpm (f16, f8, f8, 7, fpm); > + > + svdot_lane_fpm (f32, f8, f8, -1, fpm); /* { dg-error {passing -1 to > argument 4 of 'svdot_lane_fpm', which expects a value in the range \[0, 3\]} > } */ > + svdot_lane_fpm (f32, f8, f8, 4, fpm); /* { dg-error {passing 4 to argument > 4 of 'svdot_lane_fpm', which expects a value in the range \[0, 3\]} } */ > + svdot_lane_fpm (f16, f8, f8, -1, fpm); /* { dg-error {passing -1 to > argument 4 of 'svdot_lane_fpm', which expects a value in the range \[0, 7\]} > } */ > + svdot_lane_fpm (f16, f8, f8, 8, fpm); /* { dg-error {passing 8 to argument > 4 of 'svdot_lane_fpm', which expects a value in the range \[0, 7\]} } */ > + > + svdot_lane_fpm (f16); /* { dg-error {too few arguments to function > 'svdot_lane_fpm'} } */ > + svdot_lane_fpm (f16, f8); /* { dg-error {too few arguments to function > 'svdot_lane_fpm'} } */ > + svdot_lane_fpm (f16, f8, f8); /* { dg-error {too few arguments to function > 'svdot_lane_fpm'} } */ > + svdot_lane_fpm (f16, f8, f8, 0); /* { dg-error {too few arguments to > function 'svdot_lane_fpm'} } */ > + svdot_lane_fpm (f16, f8, f8, fpm); /* { dg-error {too few arguments to > function 'svdot_lane_fpm'} } */ > + svdot_lane_fpm (f16, f8, 15, fpm); /* { dg-error {too few arguments to > function 'svdot_lane_fpm'} } */ > + svdot_lane_fpm (f8, f8, 15, fpm); /* { dg-error {too few arguments to > function 'svdot_lane_fpm'} } */ > + > + svdot_lane_fpm (f16, f8, f8, 15, 0, fpm); /* { dg-error {too many > arguments to function 'svdot_lane_fpm'} } */ > + svdot_lane_fpm (f16, f8, f8, 15, fpm, fpm); /* { dg-error {too many > arguments to function 'svdot_lane_fpm'} } */ > + svdot_lane_fpm (f16, f8, f8, f8, 15, fpm); /* { dg-error {too many > arguments to function 'svdot_lane_fpm'} } */ > + svdot_lane_fpm (f16, f16, f8, f8, 15, fpm); /* { dg-error {too many > arguments to function 'svdot_lane_fpm'} } */ > + > + svdot_lane_fpm (f32, bf16, bf16, 0, fpm); /* { dg-error {passing > 'svbfloat16_t' to argument 2 of 'svdot_lane_fpm', which expects > 'svmfloat8_t'} } */ > + svdot_lane_fpm (0, f8, f8, 0, fpm); /* { dg-error {passing 'int' to > argument 1 of 'svdot_lane_fpm', which expects an SVE type rather than a > scalar} } */ > + svdot_lane_fpm (pg, f8, f8, 0, fpm); /* { dg-error {'svdot_lane_fpm' has > no form that takes 'svbool_t' and 'svmfloat8_t' arguments} } */ > + svdot_lane_fpm (u8, f8, f8, 0, fpm); /* { dg-error {'svdot_lane_fpm' has > no form that takes 'svuint8_t' and 'svmfloat8_t' arguments} } */ > + svdot_lane_fpm (u16, f8, f8, 0, fpm); /* { dg-error {'svdot_lane_fpm' has > no form that takes 'svuint16_t' and 'svmfloat8_t' arguments} } */ > + svdot_lane_fpm (f64, f8, f8, 0, fpm); /* { dg-error {'svdot_lane_fpm' has > no form that takes 'svfloat64_t' and 'svmfloat8_t' arguments} } */ > + svdot_lane_fpm (f16, 0, f8, 0, fpm); /* { dg-error {passing 'int' to > argument 2 of 'svdot_lane_fpm', which expects 'svmfloat8_t'} } */ > + svdot_lane_fpm (f16, f32, f8, 0, fpm); /* { dg-error {passing > 'svfloat32_t' to argument 2 of 'svdot_lane_fpm', which expects 'svmfloat8_t'} > } */ > + svdot_lane_fpm (f16, f8, 0, 0, fpm); /* { dg-error {passing 'int' to > argument 3 of 'svdot_lane_fpm', which expects 'svmfloat8_t'} } */ > + svdot_lane_fpm (f16, f8, f32, 0, fpm); /* { dg-error {passing > 'svfloat32_t' to argument 3 of 'svdot_lane_fpm', which expects 'svmfloat8_t'} > } */ > + > + svdot_lane_fpm (f16, f8, f8, s32, fpm); /* { dg-error {argument 4 of > 'svdot_lane_fpm' must be an integer constant expression} } */ > + svdot_lane_fpm (f16, f8, f8, i, fpm); /* { dg-error {argument 4 of > 'svdot_lane_fpm' must be an integer constant expression} } */ > +} > diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/dot_lane_mf8.c > b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/dot_lane_mf8.c > new file mode 100644 > index 00000000000..9e54cd11c4b > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/dot_lane_mf8.c > @@ -0,0 +1,172 @@ > +/* { dg-do assemble { target aarch64_asm_fp8dot2_ok } } */ > +/* { dg-do compile { target { ! aarch64_asm_fp8dot2_ok } } } */ > +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ > + > +#include "test_sve_acle.h" > + > +#pragma GCC target "+fp8dot2" > +#ifdef STREAMING_COMPATIBLE > +#pragma GCC target "+ssve-fp8dot2" > +#endif > + > +/* > +** dot_lane_0_f16_tied1: > +** msr fpmr, x0 > +** fdot z0\.h, z4\.b, z5\.b\[0\] > +** ret > +*/ > +TEST_DUAL_Z (dot_lane_0_f16_tied1, svfloat16_t, svmfloat8_t, > + z0 = svdot_lane_f16_mf8_fpm (z0, z4, z5, 0, fpm0), > + z0 = svdot_lane_fpm (z0, z4, z5, 0, fpm0)) > + > +/* > +** dot_lane_0_f16_tied2: > +** msr fpmr, x0 > +** mov (z[0-9]+)\.d, z0\.d > +** movprfx z0, z4 > +** fdot z0\.h, \1\.b, z1\.b\[0\] > +** ret > +*/ > +TEST_DUAL_Z_REV (dot_lane_0_f16_tied2, svfloat16_t, svmfloat8_t, > + z0_res = svdot_lane_f16_mf8_fpm (z4, z0, z1, 0, fpm0), > + z0_res = svdot_lane_fpm (z4, z0, z1, 0, fpm0)) > + > +/* > +** dot_lane_0_f16_tied3: > +** msr fpmr, x0 > +** mov (z[0-9]+)\.d, z0\.d > +** movprfx z0, z4 > +** fdot z0\.h, z1\.b, \1\.b\[0\] > +** ret > +*/ > +TEST_DUAL_Z_REV (dot_lane_0_f16_tied3, svfloat16_t, svmfloat8_t, > + z0_res = svdot_lane_f16_mf8_fpm (z4, z1, z0, 0, fpm0), > + z0_res = svdot_lane_fpm (z4, z1, z0, 0, fpm0)) > + > +/* > +** dot_lane_0_f16_untied: > +** msr fpmr, x0 > +** movprfx z0, z1 > +** fdot z0\.h, z4\.b, z5\.b\[0\] > +** ret > +*/ > +TEST_DUAL_Z (dot_lane_0_f16_untied, svfloat16_t, svmfloat8_t, > + z0 = svdot_lane_f16_mf8_fpm (z1, z4, z5, 0, fpm0), > + z0 = svdot_lane_fpm (z1, z4, z5, 0, fpm0)) > + > +/* > +** dot_lane_1_f16: > +** msr fpmr, x0 > +** fdot z0\.h, z4\.b, z5\.b\[1\] > +** ret > +*/ > +TEST_DUAL_Z (dot_lane_1_f16, svfloat16_t, svmfloat8_t, > + z0 = svdot_lane_f16_mf8_fpm (z0, z4, z5, 1, fpm0), > + z0 = svdot_lane_fpm (z0, z4, z5, 1, fpm0)) > + > +/* > +** dot_lane_z8_f16: > +** ... > +** msr fpmr, x0 > +** mov (z[0-7])\.d, z8\.d > +** fdot z0\.h, z1\.b, \1\.b\[1\] > +** ldr d8, \[sp\], 32 > +** ret > +*/ > +TEST_DUAL_LANE_REG (dot_lane_z8_f16, svfloat16_t, svmfloat8_t, z8, > + z0 = svdot_lane_f16_mf8_fpm (z0, z1, z8, 1, fpm0), > + z0 = svdot_lane_fpm (z0, z1, z8, 1, fpm0)) > + > +/* > +** dot_lane_z16_f16: > +** ... > +** msr fpmr, x0 > +** mov (z[0-7])\.d, z16\.d > +** fdot z0\.h, z1\.b, \1\.b\[7\] > +** ... > +** ret > +*/ > +TEST_DUAL_LANE_REG (dot_lane_z16_f16, svfloat16_t, svmfloat8_t, z16, > + z0 = svdot_lane_f16_mf8_fpm (z0, z1, z16, 7, fpm0), > + z0 = svdot_lane_fpm (z0, z1, z16, 7, fpm0)) > + > +/* > +** dot_lane_0_f32_tied1: > +** msr fpmr, x0 > +** fdot z0\.s, z4\.b, z5\.b\[0\] > +** ret > +*/ > +TEST_DUAL_Z (dot_lane_0_f32_tied1, svfloat32_t, svmfloat8_t, > + z0 = svdot_lane_f32_mf8_fpm (z0, z4, z5, 0, fpm0), > + z0 = svdot_lane_fpm (z0, z4, z5, 0, fpm0)) > + > +/* > +** dot_lane_0_f32_tied2: > +** msr fpmr, x0 > +** mov (z[0-9]+)\.d, z0\.d > +** movprfx z0, z4 > +** fdot z0\.s, \1\.b, z1\.b\[0\] > +** ret > +*/ > +TEST_DUAL_Z_REV (dot_lane_0_f32_tied2, svfloat32_t, svmfloat8_t, > + z0_res = svdot_lane_f32_mf8_fpm (z4, z0, z1, 0, fpm0), > + z0_res = svdot_lane_fpm (z4, z0, z1, 0, fpm0)) > + > +/* > +** dot_lane_0_f32_tied3: > +** msr fpmr, x0 > +** mov (z[0-9]+)\.d, z0\.d > +** movprfx z0, z4 > +** fdot z0\.s, z1\.b, \1\.b\[0\] > +** ret > +*/ > +TEST_DUAL_Z_REV (dot_lane_0_f32_tied3, svfloat32_t, svmfloat8_t, > + z0_res = svdot_lane_f32_mf8_fpm (z4, z1, z0, 0, fpm0), > + z0_res = svdot_lane_fpm (z4, z1, z0, 0, fpm0)) > + > +/* > +** dot_lane_0_f32_untied: > +** msr fpmr, x0 > +** movprfx z0, z1 > +** fdot z0\.s, z4\.b, z5\.b\[0\] > +** ret > +*/ > +TEST_DUAL_Z (dot_lane_0_f32_untied, svfloat32_t, svmfloat8_t, > + z0 = svdot_lane_f32_mf8_fpm (z1, z4, z5, 0, fpm0), > + z0 = svdot_lane_fpm (z1, z4, z5, 0, fpm0)) > + > +/* > +** dot_lane_1_f32: > +** msr fpmr, x0 > +** fdot z0\.s, z4\.b, z5\.b\[1\] > +** ret > +*/ > +TEST_DUAL_Z (dot_lane_1_f32, svfloat32_t, svmfloat8_t, > + z0 = svdot_lane_f32_mf8_fpm (z0, z4, z5, 1, fpm0), > + z0 = svdot_lane_fpm (z0, z4, z5, 1, fpm0)) > + > +/* > +** dot_lane_z8_f32: > +** ... > +** msr fpmr, x0 > +** mov (z[0-7])\.d, z8\.d > +** fdot z0\.s, z1\.b, \1\.b\[1\] > +** ldr d8, \[sp\], 32 > +** ret > +*/ > +TEST_DUAL_LANE_REG (dot_lane_z8_f32, svfloat32_t, svmfloat8_t, z8, > + z0 = svdot_lane_f32_mf8_fpm (z0, z1, z8, 1, fpm0), > + z0 = svdot_lane_fpm (z0, z1, z8, 1, fpm0)) > + > +/* > +** dot_lane_z32_f32: > +** ... > +** msr fpmr, x0 > +** mov (z[0-7])\.d, z16\.d > +** fdot z0\.s, z1\.b, \1\.b\[3\] > +** ... > +** ret > +*/ > +TEST_DUAL_LANE_REG (dot_lane_z32_f32, svfloat32_t, svmfloat8_t, z16, > + z0 = svdot_lane_f32_mf8_fpm (z0, z1, z16, 3, fpm0), > + z0 = svdot_lane_fpm (z0, z1, z16, 3, fpm0)) > diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/dot_mf8.c > b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/dot_mf8.c > new file mode 100644 > index 00000000000..12e28e3284f > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/dot_mf8.c > @@ -0,0 +1,101 @@ > +/* { dg-do assemble { target aarch64_asm_fp8dot2_ok } } */ > +/* { dg-do compile { target { ! aarch64_asm_fp8dot2_ok } } } */ > +/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */ > + > +#include "test_sve_acle.h" > + > +#pragma GCC target "+fp8dot2" > +#ifdef STREAMING_COMPATIBLE > +#pragma GCC target "+ssve-fp8dot2" > +#endif > + > +/* > +** dot_f16_mf8_tied1: > +** msr fpmr, x0 > +** fdot z0\.h, z4\.b, z5\.b > +** ret > +*/ > +TEST_DUAL_Z (dot_f16_mf8_tied1, svfloat16_t, svmfloat8_t, > + z0 = svdot_f16_mf8_fpm (z0, z4, z5, fpm0), > + z0 = svdot_fpm (z0, z4, z5, fpm0)) > + > +/* > +** dot_f16_mf8_tied2: > +** msr fpmr, x0 > +** mov (z[0-9]+)\.d, z0\.d > +** movprfx z0, z4 > +** fdot z0\.h, \1\.b, z1\.b > +** ret > +*/ > +TEST_DUAL_Z_REV (dot_f16_mf8_tied2, svfloat16_t, svmfloat8_t, > + z0_res = svdot_f16_mf8_fpm (z4, z0, z1, fpm0), > + z0_res = svdot_fpm (z4, z0, z1, fpm0)) > + > +/* > +** dot_f16_mf8_tied3: > +** msr fpmr, x0 > +** mov (z[0-9]+)\.d, z0\.d > +** movprfx z0, z4 > +** fdot z0\.h, z1\.b, \1\.b > +** ret > +*/ > +TEST_DUAL_Z_REV (dot_f16_mf8_tied3, svfloat16_t, svmfloat8_t, > + z0_res = svdot_f16_mf8_fpm (z4, z1, z0, fpm0), > + z0_res = svdot_fpm (z4, z1, z0, fpm0)) > + > +/* > +** dot_f16_mf8_untied: > +** msr fpmr, x0 > +** movprfx z0, z1 > +** fdot z0\.h, z4\.b, z5\.b > +** ret > +*/ > +TEST_DUAL_Z (dot_f16_mf8_untied, svfloat16_t, svmfloat8_t, > + z0 = svdot_f16_mf8_fpm (z1, z4, z5, fpm0), > + z0 = svdot_fpm (z1, z4, z5, fpm0)) > + > +/* > +** dot_f32_mf8_tied1: > +** msr fpmr, x0 > +** fdot z0\.s, z4\.b, z5\.b > +** ret > +*/ > +TEST_DUAL_Z (dot_f32_mf8_tied1, svfloat32_t, svmfloat8_t, > + z0 = svdot_f32_mf8_fpm (z0, z4, z5, fpm0), > + z0 = svdot_fpm (z0, z4, z5, fpm0)) > + > +/* > +** dot_f32_mf8_tied2: > +** msr fpmr, x0 > +** mov (z[0-9]+)\.d, z0\.d > +** movprfx z0, z4 > +** fdot z0\.s, \1\.b, z1\.b > +** ret > +*/ > +TEST_DUAL_Z_REV (dot_f32_mf8_tied2, svfloat32_t, svmfloat8_t, > + z0_res = svdot_f32_mf8_fpm (z4, z0, z1, fpm0), > + z0_res = svdot_fpm (z4, z0, z1, fpm0)) > + > +/* > +** dot_f32_mf8_tied3: > +** msr fpmr, x0 > +** mov (z[0-9]+)\.d, z0\.d > +** movprfx z0, z4 > +** fdot z0\.s, z1\.b, \1\.b > +** ret > +*/ > +TEST_DUAL_Z_REV (dot_f32_mf8_tied3, svfloat32_t, svmfloat8_t, > + z0_res = svdot_f32_mf8_fpm (z4, z1, z0, fpm0), > + z0_res = svdot_fpm (z4, z1, z0, fpm0)) > + > +/* > +** dot_f32_mf8_untied: > +** msr fpmr, x0 > +** movprfx z0, z1 > +** fdot z0\.s, z4\.b, z5\.b > +** ret > +*/ > +TEST_DUAL_Z (dot_f32_mf8_untied, svfloat32_t, svmfloat8_t, > + z0 = svdot_f32_mf8_fpm (z1, z4, z5, fpm0), > + z0 = svdot_fpm (z1, z4, z5, fpm0)) > + > diff --git a/gcc/testsuite/lib/target-supports.exp > b/gcc/testsuite/lib/target-supports.exp > index a122178bd21..95acd0975bb 100644 > --- a/gcc/testsuite/lib/target-supports.exp > +++ b/gcc/testsuite/lib/target-supports.exp > @@ -12141,7 +12141,8 @@ foreach { aarch64_ext } { "fp" "simd" "crypto" "crc" > "lse" "dotprod" "sve" > "i8mm" "f32mm" "f64mm" "bf16" "sb" "sve2" "ls64" > "sme" "sme-i16i64" "sme2" "sve-b16b16" > "sme-b16b16" "sme-f16f16" "sme2p1" "fp8" "fp8fma" > - "ssve-fp8fma" } { > + "ssve-fp8fma" "fp8dot2" "ssve-fp8dot2" "fp8dot4" > + "ssve-fp8dot4"} { > eval [string map [list FUNC $aarch64_ext] { > proc check_effective_target_aarch64_asm_FUNC_ok { } { > if { [istarget aarch64*-*-*] } {
