The following adds a missing check for a NULL call LHS in the
vector pattern recognizer.
Pushed as obvious.
PR tree-optimization/107956
* tree-vect-patterns.cc (vect_recog_mask_conversion_pattern):
Check for NULL LHS on masked loads.
---
gcc/tree-vect-patterns.cc | 2 ++
contracts.h is included by cp-tree.h so needs to be installed for
plugins.
Pushed as onbvious.
PR plugins/107964
gcc/cp/
* Make-lang.in (CP_PLUGIN_HEADERS): Install contracts.h
---
gcc/cp/Make-lang.in | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/cp/Make
Hi Richard,
在 2022/12/5 15:31, Richard Biener 写道:
> I wonder if you have a testcase you can add showing this change is
> worthwhile and
> fixes a bug?
I want to enable cbranchcc4 on rs6000. But not all sub CCmode is
supported on rs6000. So the predicate check(assert) fails and it hits
ICE. I draf
On Mon, Dec 5, 2022 at 9:43 AM HAO CHEN GUI wrote:
>
> Hi Richard,
>
> 在 2022/12/5 15:31, Richard Biener 写道:
> > I wonder if you have a testcase you can add showing this change is
> > worthwhile and
> > fixes a bug?
>
> I want to enable cbranchcc4 on rs6000. But not all sub CCmode is
> supported o
On 11/29/22 10:43, Jakub Jelinek wrote:
Hi!
While for the normal cases it seems to be correct to implement
reverse multiplication (op1_range/op2_range) through division
with float_binary_op_range_finish, reverse division (op1_range)
through multiplication with float_binary_op_range_finish or
On Mon, Dec 05, 2022 at 10:20:53AM +0100, Aldy Hernandez wrote:
> > For the division, [-0., 0.] / VARYING is computed (IMHO correctly)
> > as [-0., 0.] +-NAN, because 0 / anything but 0 or NAN is still
> > 0 and 0 / 0 is NAN and ditto 0 / NAN. And then we just
> > float_binary_op_range_finish, whi
On 12/5/22 10:37, Jakub Jelinek wrote:
On Mon, Dec 05, 2022 at 10:20:53AM +0100, Aldy Hernandez wrote:
For the division, [-0., 0.] / VARYING is computed (IMHO correctly)
as [-0., 0.] +-NAN, because 0 / anything but 0 or NAN is still
0 and 0 / 0 is NAN and ditto 0 / NAN. And then we just
floa
Hi!
As reported in the PR, the following pr106805.c testcase is miscompiled
with the default -ftrapping-math, because we fold all the comparisons into
constants and don't raise any exceptions.
The match.pd pattern handles just simple comparisons, from those
EQ/NE are quiet and don't raise excepti
On Sun, Dec 4, 2022 at 9:30 PM Iain Sandoe wrote:
>
>
>
> > On 4 Dec 2022, at 20:20, Uros Bizjak via Gcc-patches
> > wrote:
> >
> > On Sun, Dec 4, 2022 at 12:51 PM Iain Sandoe wrote:
> >>
> >> This is almost a completely Darwin-local patch, but there is one (repeated)
> >> place where a general
> Am 05.12.2022 um 11:30 schrieb Jakub Jelinek via Gcc-patches
> :
>
> Hi!
>
> As reported in the PR, the following pr106805.c testcase is miscompiled
> with the default -ftrapping-math, because we fold all the comparisons into
> constants and don't raise any exceptions.
>
> The match.pd pa
Prathamesh Kulkarni writes:
> Hi,
> For the following test-case:
>
> int16x8_t foo(int16_t x, int16_t y)
> {
> return (int16x8_t) { x, y, x, y, x, y, x, y };
> }
>
> Code gen at -O3:
> foo:
> dupv0.8h, w0
> ins v0.h[1], w1
> ins v0.h[3], w1
> ins v
On Mon, 5 Dec 2022 at 09:51, Patrick Palka via Gcc-patches
wrote:
>
> These functions currently repeatedly dereference tp during the subtree
> walk, dereferences which the compiler can't CSE because it can't
> guarantee that the subtree walking doesn't modify *tp.
>
> But we already implicitly req
Richard Sandiford via Gcc-patches writes:
> Prathamesh Kulkarni writes:
>> Hi,
>> For the following test-case:
>>
>> int16x8_t foo(int16_t x, int16_t y)
>> {
>> return (int16x8_t) { x, y, x, y, x, y, x, y };
>> }
>>
>> Code gen at -O3:
>> foo:
>> dupv0.8h, w0
>> ins v0.h
"Pop, Sebastian" writes:
> Hi,
>
> Currently patchable area is at the wrong place on AArch64. It is placed
> immediately after function label, before .cfi_startproc. This patch
> adds UNSPECV_PATCHABLE_AREA for pseudo patchable area instruction and
> modifies aarch64_print_patchable_function_ent
Tamar Christina writes:
>> -Original Message-
>> From: Richard Sandiford
>> Sent: Friday, November 18, 2022 9:30 AM
>> To: Tamar Christina
>> Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw
>> ; Marcus Shawcroft
>> ; Kyrylo Tkachov
>> Subject: Re: [PATCH]AArch64 Fix vector re-interpr
On Mon, Dec 05, 2022 at 10:54:41AM +0100, Aldy Hernandez wrote:
> > Do you mind if I try that incrementally and only if it doesn't make the
> > code too large/too unreadable?
>
> Sure. And don't feel obligated to implement it either. range-ops is a
> never ending pit of possible optimizations.
Tamar Christina via Gcc-patches writes:
>> > +/* Check to see if the supplied comparison in PTEST can be performed as a
>> > + bit-test-and-branch instead. VAL must contain the original tree
>> > + expression of the non-zero operand which will be used to rewrite the
>> > + comparison in PTE
Hi Richard,
> - scalar_int_mode imode = (mode == HFmode
> - ? SImode
> - : int_mode_for_mode (mode).require ());
> + machine_mode imode = (mode == DFmode) ? DImode : SImode;
> It looks like this might mishandle DDmode, if not now the
Hi Kito,
I came across this issue while inspecting code and I have been wondering
what the reason was to downgrade current FMV.X.W and FMW.W.X instructions
to their older FMV.S.W and FMV.W.S variants here:
On Wed, 10 Aug 2022, Kito Cheng wrote:
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/c
Richard Sandiford via Gcc-patches writes:
> Tamar Christina via Gcc-patches writes:
>>> > +/* Check to see if the supplied comparison in PTEST can be performed as a
>>> > + bit-test-and-branch instead. VAL must contain the original tree
>>> > + expression of the non-zero operand which will b
On 12/5/22 12:59, Jakub Jelinek wrote:
On Mon, Dec 05, 2022 at 10:54:41AM +0100, Aldy Hernandez wrote:
Do you mind if I try that incrementally and only if it doesn't make the
code too large/too unreadable?
Sure. And don't feel obligated to implement it either. range-ops is a
never ending
Richard Biener writes:
>>
>> I think it's important to get this (and the rust frontend) into the tree
>> before
>> Christmas holidays so it gets exposed to the more weird treatment of some
>> of our users (build wise). This way we can develop either a negative or
>> positive list of host/target
Wilco Dijkstra writes:
> Hi Richard,
>
>> - scalar_int_mode imode = (mode == HFmode
>> - ? SImode
>> - : int_mode_for_mode (mode).require ());
>> + machine_mode imode = (mode == DFmode) ? DImode : SImode;
>
>> It looks like this might
Fall back to ld -r if ld -shared fails during configure. The check for
HAVE_LD_RO_RW_SECTION_MIXING can fail on targets where ld does not
support shared objects, even though the answer to the test should be
'read-write'. One such target is riscv64-unknown-elf. Failing this test
results in a libgcc
On Mon, Nov 28, 2022 at 5:53 PM Jeff Law wrote:
>
>
> On 11/28/22 06:59, Joakim Nohlgård wrote:
> > The check for HAVE_LD_RO_RW_SECTION_MIXING fails on targets where ld
> > does not support shared objects, even though the answer to the test
> > should be 'read-write'. One such target is riscv64-un
On Thu, Nov 24, 2022 at 03:09:02PM +0100, Marcel Vollweiler wrote:
> gcc/ChangeLog:
>
> * gimplify.cc (optimize_target_teams): Set initial num_teams_upper
> to "-2" instead of "1" for non-existing num_teams clause in order to
> disambiguate from the case of an existing num_teams
The testcase shows we mishandle the case where there's a pass-through
of a pointer through a function like memcpy. The following adjusts
handling of this copy case to require a taken address and adjust
the PHI case similarly.
Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.
P
Tamar Christina writes:
> Hi,
>
> I hadn't received any reply so I had implemented various ways to do this
> (about 8 of them in fact).
>
> The conclusion is that no, we cannot emit one big RTL for the final
> instruction immediately.
> The reason that all comparisons in the AArch64 backend expa
Andrea Corallo via Gcc-patches writes:
> Hi all,
>
> ping^2 for patches 9/15 7/15 11/15 12/15 and 10/15 V2 of this series.
>
> Andrea
Hello all,
PING^3 for:
[PATCH 6/12 V2] arm: Add pointer authentication for stack-unwinding runtime
[PATCH 9/15] arm: Set again stack pointer as CFA reg when po
Hi Andrea,
> -Original Message-
> From: Gcc-patches bounces+kyrylo.tkachov=arm@gcc.gnu.org> On Behalf Of Andrea
> Corallo via Gcc-patches
> Sent: Monday, December 5, 2022 2:11 PM
> To: Andrea Corallo via Gcc-patches
> Cc: Richard Earnshaw ; nd
> Subject: Re: [PING][PATCH 0/15] arm:
In commit e5cfb9cac1d7aba9a8ea73bfe7922cfaff9d61f3 I introduced tests
for strdup and strndup with leaks. Fix those leaks.
gcc/testsuite/ChangeLog:
* gcc.dg/builtin-dynamic-object-size-0.c (test_strdup,
test_strndup, test_strdup_min, test_strndup_min): Free RES
before retu
On Mon, 5 Dec 2022, Prathamesh Kulkarni wrote:
> On Mon, 5 Dec 2022 at 09:51, Patrick Palka via Gcc-patches
> wrote:
> >
> > These functions currently repeatedly dereference tp during the subtree
> > walk, dereferences which the compiler can't CSE because it can't
> > guarantee that the subtree w
Hi Uros,
> On 5 Dec 2022, at 10:37, Uros Bizjak via Gcc-patches
> wrote:
>
> On Sun, Dec 4, 2022 at 9:30 PM Iain Sandoe wrote:
>>
>> gcc/testsuite/ChangeLog:
>>
>>* gcc.target/x86_64/abi/bf16/args.h: Make xmm_regs, x87_regs extern.
>>* gcc.target/x86_64/abi/bf16/m256bf16/arg
On Fri, 2 Dec 2022, Qing Zhao wrote:
>
>
> > On Dec 2, 2022, at 2:20 AM, Richard Biener wrote:
> >
> > On Fri, 2 Dec 2022, Richard Biener wrote:
> >
> >> On Thu, 1 Dec 2022, Siddhesh Poyarekar wrote:
> >>
> >>> On 2022-12-01 11:42, Kees Cook wrote:
> On Wed, Nov 30, 2022 at 02:25:56PM +
> On Dec 5, 2022, at 10:16 AM, Richard Biener wrote:
>
> On Fri, 2 Dec 2022, Qing Zhao wrote:
>
>>
>>
>>> On Dec 2, 2022, at 2:20 AM, Richard Biener wrote:
>>>
>>> On Fri, 2 Dec 2022, Richard Biener wrote:
>>>
On Thu, 1 Dec 2022, Siddhesh Poyarekar wrote:
> On 2022-12-01 1
Hi!
On Mon, Dec 05, 2022 at 02:29:36PM +0100, Aldy Hernandez wrote:
> > So like this for multiplication op1/2_range if it passes bootstrap/regtest?
> > For division I'll need to go to a drawing board...
>
> Sure, looks good to me.
Ulrich just filed PR107972, so in the light of that PR the follow
The following fixes an issue where SSA update loses PHI argument
locations when updating PHI nodes it didn't create as part of the
SSA update. For the case where the reaching def is the same as
the current argument opt to do nothing and for the case where the
PHI argument already has a location ke
Ping x5
On 2022/11/22 12:24 上午, Chung-Lin Tang wrote:
> Ping x4
>
> On 2022/11/8 12:34 AM, Chung-Lin Tang wrote:
>> Ping x3.
>>
>> On 2022/10/31 10:18 PM, Chung-Lin Tang wrote:
>>> Ping x2.
>>>
>>> On 2022/10/17 10:29 PM, Chung-Lin Tang wrote:
Ping.
On 2022/9/21 3:45 PM, Chung-Lin
On 12/5/22 07:28, Siddhesh Poyarekar wrote:
In commit e5cfb9cac1d7aba9a8ea73bfe7922cfaff9d61f3 I introduced tests
for strdup and strndup with leaks. Fix those leaks.
gcc/testsuite/ChangeLog:
* gcc.dg/builtin-dynamic-object-size-0.c (test_strdup,
test_strndup, test_strdup_min
On 07/11/2022 08:57, Andrea Corallo via Gcc-patches wrote:
Hi all,
please find attached the lastest version of this patch incorporating some
more improvents. Feel free to ignore V3.
Best Regards
Andrea
> As part of previous upstream suggestions a test for varargs has been
> added and
On 12/2/22 02:34, Alexandre Oliva via Gcc-patches wrote:
The FP emulation on ARM doesn't take rounding modes into account. The
tests require hard_float, but that only tests for calls when adding
doubles. There are arm targets that support hardware adds, but that
emulate conversions.
Regstr
On 11/28/22 20:53, Jiufu Guo wrote:
Right, but the number of registers is target dependent, so I don't see
how using "8" or any number of that matter is correct here.
I understand. And even for the same struct type, using how many
registers to pass a parameter, it also dependends on the si
On 12/2/22 00:26, Eric Gallager via Gcc-patches wrote:
I tried turning -Wnarrowing back on earlier this year, but
unfortunately it didn't work due to triggering a bunch of new errors.
This patch silences at least some of them, but there will still be
more left even after applying it. (When com
On 2022-12-05 11:38, Jeff Law wrote:
On 12/5/22 07:28, Siddhesh Poyarekar wrote:
In commit e5cfb9cac1d7aba9a8ea73bfe7922cfaff9d61f3 I introduced tests
for strdup and strndup with leaks. Fix those leaks.
gcc/testsuite/ChangeLog:
* gcc.dg/builtin-dynamic-object-size-0.c (test_strdup,
On 28/10/2022 17:40, Andrea Corallo via Gcc-patches wrote:
Hi all,
please find attached the third iteration of this patch addresing review
comments.
Thanks
Andrea
@@ -23374,12 +23374,6 @@ output_probe_stack_range (rtx reg1, rtx reg2)
return "";
}
-static bool
-aarch_bti_enabled (
On 12/2/22 10:52, Cupertino Miranda via Gcc-patches wrote:
Changed target code to select .rodata section for 'const volatile'
defined variables.
This change is in the context of the bugzilla #170181.
gcc/ChangeLog:
v850.c(v850_select_section): Changed function.
I'm not sure this is s
On 12/2/22 07:30, Richard Biener via Gcc-patches wrote:
The following fixes a wrong-code bug caused by loop invariant motion
hoisting an expression using an uninitialized value outside of its
controlling condition causing IVOPTs to use that to rewrite a defined
value. PR107839 is a similar ca
Prathamesh Kulkarni writes:
> Hi,
> The following test:
>
> #include "arm_sve.h"
>
> svint8_t
> test_s8(int8_t *x)
> {
> return svld1rq_s8 (svptrue_b8 (), &x[0]);
> }
>
> ICE's with -march=armv8.2-a+sve -O1 -fno-tree-ccp -fno-tree-forwprop:
> during GIMPLE pass: fre
> pr107920.c: In function ‘te
On 12/2/22 10:52, Cupertino Miranda via Gcc-patches wrote:
This commit is a follow up of bugzilla #107181.
The commit /a0aafbc/ changed the default implementation of the
SELECT_SECTION hook in order to match clang/llvm behaviour w.r.t the
placement of `const volatile' objects.
However, the f
Wilco Dijkstra writes:
> A recent change only initializes the regs.how[] during Dwarf unwinding
> which resulted in an uninitialized offset used in return address signing
> and random failures during unwinding. The fix is to use REG_SAVED_OFFSET
> as the state where the return address signing bit
Hi!
Some comments on the testcases:
On Tue, Nov 29, 2022 at 09:45:07PM +0800, Jiufu Guo wrote:
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr65421-1.c
> @@ -0,0 +1,25 @@
> +/* PR target/65421 */
> +/* { dg-do compile } */
> +/* { dg-options "-O2" } */
> +/* { dg-require-effective-tar
On 12/5/22 10:33, Jakub Jelinek wrote:
Hi!
On Mon, Dec 05, 2022 at 02:29:36PM +0100, Aldy Hernandez wrote:
So like this for multiplication op1/2_range if it passes bootstrap/regtest?
For division I'll need to go to a drawing board...
Sure, looks good to me.
Ulrich just filed PR107972, so in
On Mon, Dec 5, 2022 at 3:54 PM Iain Sandoe wrote:
>
> Hi Uros,
>
> > On 5 Dec 2022, at 10:37, Uros Bizjak via Gcc-patches
> > wrote:
> >
> > On Sun, Dec 4, 2022 at 9:30 PM Iain Sandoe wrote:
> >>
>
> >> gcc/testsuite/ChangeLog:
> >>
> >>* gcc.target/x86_64/abi/bf16/args.h: Make xmm_regs
On 12/5/22 06:09, Prathamesh Kulkarni wrote:
On Mon, 5 Dec 2022 at 09:51, Patrick Palka via Gcc-patches
wrote:
These functions currently repeatedly dereference tp during the subtree
walk, dereferences which the compiler can't CSE because it can't
guarantee that the subtree walking doesn't modi
I just rebased this patch.
All good apart from the to_chars/from_chars symbols issue.
François
On 11/10/22 19:28, François Dumont wrote:
Hi
Now that pretty printer is fixed (once patch validated) I'd like
to propose this patch again.
Note that I'am adding a check on pretty printer
Hi Uros,
> On 5 Dec 2022, at 21:07, Uros Bizjak via Gcc-patches
> wrote:
>
> On Mon, Dec 5, 2022 at 3:54 PM Iain Sandoe wrote:
>>
>> Hi Uros,
>>
>>> On 5 Dec 2022, at 10:37, Uros Bizjak via Gcc-patches
>>> wrote:
>>>
>>> On Sun, Dec 4, 2022 at 9:30 PM Iain Sandoe wrote:
>>
gc
On Mon, Dec 5, 2022 at 10:17 PM Iain Sandoe wrote:
>
> Hi Uros,
>
> > On 5 Dec 2022, at 21:07, Uros Bizjak via Gcc-patches
> > wrote:
> >
> > On Mon, Dec 5, 2022 at 3:54 PM Iain Sandoe wrote:
> >>
> >> Hi Uros,
> >>
> >>> On 5 Dec 2022, at 10:37, Uros Bizjak via Gcc-patches
> >>> wrote:
> >>>
On Tue, 2022-11-29 14:30:22 +0100, Richard Biener via Gcc-patches
wrote:
> Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.
>
> PR tree-optimization/107852
> * tree-ssa-sccvn.cc (visit_phi): Use equivalences recorded
> as predicated values to elide more redundant PH
On Mon, Dec 05, 2022 at 03:43:16PM -0500, Andrew MacLeod wrote:
> Id actually prefer to avoid passing the tree code around... we're trying to
> avoid that sort of thing even though Aldy temporarily introduced them to
> range-ops. Hes suppose to remove that next stage 1 :-P Ideally anything
> "spe
Hi!
According to
https://gcc.gnu.org/pipermail/gcc-regression/2022-December/077258.html
my patch caused some ICEs, e.g. the following testcase ICEs.
The problem is that lower_bound and upper_bound methods on a france assert
that the range isn't VR_NAN or VR_UNDEFINED.
All the op1_range/op2_range
On Mon, Dec 05, 2022 at 09:54:09PM +0100, Jakub Jelinek via Gcc-patches wrote:
> On Mon, Dec 05, 2022 at 03:43:16PM -0500, Andrew MacLeod wrote:
> > Id actually prefer to avoid passing the tree code around... we're trying to
> > avoid that sort of thing even though Aldy temporarily introduced them
On 12/5/22 17:38, Jakub Jelinek wrote:
On Mon, Dec 05, 2022 at 09:54:09PM +0100, Jakub Jelinek via Gcc-patches wrote:
On Mon, Dec 05, 2022 at 03:43:16PM -0500, Andrew MacLeod wrote:
Id actually prefer to avoid passing the tree code around... we're trying to
avoid that sort of thing even thoug
Hi Palmer and all,
I have split the patches and triggerred a new thread.
https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg297206.html
Could you please review at your convenience?
Thanks & BR,
Fei
On 2022-12-01 11:07 Fei Gao wrote:
>
>On 2022-12-01 06:50 Palmer Dabbelt wrote:
>>
>>O
On Mon, 5 Dec 2022 at 16:50, Richard Sandiford
wrote:
>
> Richard Sandiford via Gcc-patches writes:
> > Prathamesh Kulkarni writes:
> >> Hi,
> >> For the following test-case:
> >>
> >> int16x8_t foo(int16_t x, int16_t y)
> >> {
> >> return (int16x8_t) { x, y, x, y, x, y, x, y };
> >> }
> >>
>
Hi Segher,
Thanks for your comments!
Segher Boessenkool writes:
> Hi!
>
> Some comments on the testcases:
>
> On Tue, Nov 29, 2022 at 09:45:07PM +0800, Jiufu Guo wrote:
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/powerpc/pr65421-1.c
>> @@ -0,0 +1,25 @@
>> +/* PR target/65421 */
>> +/* {
On Tue, 6 Dec 2022 at 00:08, Richard Sandiford
wrote:
>
> Prathamesh Kulkarni writes:
> > Hi,
> > The following test:
> >
> > #include "arm_sve.h"
> >
> > svint8_t
> > test_s8(int8_t *x)
> > {
> > return svld1rq_s8 (svptrue_b8 (), &x[0]);
> > }
> >
> > ICE's with -march=armv8.2-a+sve -O1 -fno-t
Hi,
Jeff Law writes:
> On 11/28/22 20:53, Jiufu Guo wrote:
>
>>>
>>> Right, but the number of registers is target dependent, so I don't see
>>> how using "8" or any number of that matter is correct here.
>> I understand. And even for the same struct type, using how many
>> registers to pass a p
Hi,
This patch enables "have_cbranchcc4" on rs6000 by defining
a "cbranchcc4" expander. "have_cbrnachcc4" is a flag in ifcvt.cc
to indicate if branch by CC bits is invalid or not. With this
flag enabled, some branches can be optimized to conditional
moves.
The patch relies on the former patch
On Mon, 5 Dec 2022, Jan-Benedict Glaw wrote:
> On Tue, 2022-11-29 14:30:22 +0100, Richard Biener via Gcc-patches
> wrote:
> > Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.
> >
> > PR tree-optimization/107852
> > * tree-ssa-sccvn.cc (visit_phi): Use equivalences recorded
>
On Mon, 5 Dec 2022, Jakub Jelinek wrote:
> Hi!
>
> According to
> https://gcc.gnu.org/pipermail/gcc-regression/2022-December/077258.html
> my patch caused some ICEs, e.g. the following testcase ICEs.
> The problem is that lower_bound and upper_bound methods on a france assert
> that the range is
The following adds the testcase from the description which was
fixed by r13-2894-gbe4a6551ed37c1.
Tested on x86_64-unknown-linux-gnu, pushed.
PR tree-optimization/104165
* g++.dg/warn/Warray-bounds-pr104165-1.C: New testcase.
---
.../g++.dg/warn/Warray-bounds-pr104165-1.C| 27
Prathamesh Kulkarni writes:
> On Tue, 6 Dec 2022 at 00:08, Richard Sandiford
> wrote:
>>
>> Prathamesh Kulkarni writes:
>> > Hi,
>> > The following test:
>> >
>> > #include "arm_sve.h"
>> >
>> > svint8_t
>> > test_s8(int8_t *x)
>> > {
>> > return svld1rq_s8 (svptrue_b8 (), &x[0]);
>> > }
>> >
This patch finally handles reverse offload. Due to the prep work,
it essentially only adds content to libgomp/target.c's gomp_target_rev(),
except that it additionally saves the reverse-offload-function table
in gomp_load_image_to_device.
In the comment to "[Patch] libgomp: Add reverse-offload sp
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