Re: [PATCH] RISC-V: Implment H modifier for printing the next register name

). To address this, the modifier 'H' has been added to allow users to handle the upper 32 bits of the data. While I believe the modifier 'N' (representing the next register name) might be more suitable for this functionality, 'N' is already in use. Therefore, 'H&#x

[PATCH] RISC-V: Implment H modifier for printing the next register name

For RV32 inline assembly, when handling 64-bit integer data, it is often necessary to process the lower and upper 32 bits separately. Unfortunately, we can only output the current register name (lower 32 bits) but not the next register name (upper 32 bits). To address this, the modifier 'H

Re: [RFC] RISC-V: Implment H modifier for printing the next register name

. Unfortunately, we can only output the current register name (lower 32 bits) but not the next register name (upper 32 bits). To address this, the modifier 'H' has been added to allow users to handle the upper 32 bits of the data. While I believe the modifier 'N' (representing the next

Re: [RFC] RISC-V: Implment H modifier for printing the next register name

y, we can only output the current register name > > (lower 32 bits) but not the next register name (upper 32 bits). > > > > To address this, the modifier 'H' has been added to allow users > > to handle the upper 32 bits of the data. While I believe the > > mod

Re: [RFC] RISC-V: Implment H modifier for printing the next register name

not the next register name (upper 32 bits). > > To address this, the modifier 'H' has been added to allow users > to handle the upper 32 bits of the data. While I believe the > modifier 'N' (representing the next register name) might be more > suitable for this functi

[RFC] RISC-V: Implment H modifier for printing the next register name

For RV32 inline assembly, when handling 64-bit integer data, it is often necessary to process the lower and upper 32 bits separately. Unfortunately, we can only output the current register name (lower 32 bits) but not the next register name (upper 32 bits). To address this, the modifier 'H

[PATCH 23/27] Revert "AVX10.2 ymm rounding: Support vcvtdq2p{s, h} and vcvtpd2p{s, h} intrins"

This reverts commit 85e874d19548f0dcb9a3f14f9e4b1e3411c88c4b. --- gcc/config/i386/avx10_2roundingintrin.h | 210 -- gcc/config/i386/i386-builtin-types.def| 4 - gcc/config/i386/i386-builtin.def | 4 - gcc/config/i386/i386-expand.cc|

[PATCH 18/27] Revert "AVX10.2 ymm rounding: Support vcvtqq2p{s, d, h} and vcvttpd2{, u}{dq, qq} intrins"

This reverts commit 6e231f8504874828b23bbe89f3ef4086dcc15a44. --- gcc/config/i386/avx10_2roundingintrin.h | 390 -- gcc/config/i386/i386-builtin-types.def| 3 - gcc/config/i386/i386-builtin.def | 7 - gcc/config/i386/i386-expand.cc|

[PATCH 16/27] Revert "AVX10.2 ymm rounding: Support vcvttps2{, u}{dq, qq} and vcvtu{dq, qq}2p{s, d, h} intrins"

This reverts commit b2754227139512adecb6fda067632b587ff4a017. --- gcc/config/i386/avx10_2roundingintrin.h | 492 -- gcc/config/i386/i386-builtin.def | 9 - gcc/config/i386/sse.md| 27 +- gcc/testsuite/gcc.target/i386/avx-1.c |

[PATCH 06/27] Revert "AVX10.2 ymm rounding: Support vmulp{s, d, h} and vrangep{s, d} intrins"

This reverts commit 90cc5b0c4609a9fb3257d2cce7b7abc896c6faab. --- gcc/config/i386/avx10_2roundingintrin.h | 313 -- gcc/config/i386/i386-builtin-types.def| 2 - gcc/config/i386/i386-builtin.def | 5 - gcc/config/i386/i386-expand.cc|

[PATCH 24/27] Revert "AVX10.2 ymm rounding: Support vadd{s, d, h} and vcmp{s, d, h} intrins"

This reverts commit e22e3af1954469c40b139b7cfa8e7708592f4bfd. --- gcc/config.gcc| 3 +- gcc/config/i386/avx10_2roundingintrin.h | 337 -- gcc/config/i386/i386-builtin-types.def| 6 - gcc/config/i386/i386-builtin.def |

[PATCH 08/27] Revert "AVX10.2 ymm rounding: Support vgetexpp{s, d, h} and vgetmantp{s, d, h} intrins"

This reverts commit 8d4f542935c09f40bb7fd8fd863cc8df80cc970e. --- gcc/config/i386/avx10_2roundingintrin.h | 341 -- gcc/config/i386/i386-builtin-types.def| 6 - gcc/config/i386/i386-builtin.def | 6 - gcc/config/i386/i386-expand.cc|

[PATCH 13/27] Revert "AVX10.2 ymm rounding: Support vfmadd{132, 231, 213}p{s, d, h} intrins"

This reverts commit 0683ca355a87fd36a2e7ae1721199204ceff4c4c. --- gcc/config/i386/avx10_2roundingintrin.h | 176 -- gcc/config/i386/i386-builtin.def | 9 - gcc/config/i386/sse.md| 2 +- gcc/testsuite/gcc.target/i386/avx-1.c |

[PATCH 05/27] Revert "AVX10.2 ymm rounding: Support vreducep{s, d, h} and vrndscalep{s, d, h} intrins"

This reverts commit 9afa5081212e1fc3cb2c4efc9b4f421eecf68810. --- gcc/config/i386/avx10_2roundingintrin.h | 367 -- gcc/config/i386/i386-builtin.def | 6 - gcc/config/i386/sse.md| 4 +- gcc/testsuite/gcc.target/i386/avx-1.c |

[PATCH 07/27] Revert "AVX10.2 ymm rounding: Support v{max, min}p{s, d, h} intrins"

This reverts commit cc8a7596477e9d6ac972aadabbb2fd88baa1abf4. --- gcc/config/i386/avx10_2roundingintrin.h | 360 -- gcc/config/i386/i386-builtin.def | 6 - gcc/testsuite/gcc.target/i386/avx-1.c | 6 - .../gcc.target/i386/avx10_2-rounding-3.c | 5

[PATCH 15/27] Revert "AVX10.2 ymm rounding: Support vcvt{, u}w2ph and vdivp{s, d, h} intrins"

This reverts commit 3d1b5530ea1d23e26dc5ab70aa4a2e7b9dc19b50. --- gcc/config/i386/avx10_2roundingintrin.h | 286 -- gcc/config/i386/i386-builtin-types.def| 1 - gcc/config/i386/i386-builtin.def | 5 - gcc/config/i386/i386-expand.cc|

[PATCH 10/27] Revert "AVX10.2 ymm rounding: Support vfmulcph and vfnmadd{132, 231, 213}p{s, d, h} intrins"

This reverts commit 6f0aa7add1d9177f60016b32ca9ca8b16b173a56. --- gcc/config/i386/avx10_2roundingintrin.h | 241 -- gcc/config/i386/i386-builtin.def | 11 - gcc/testsuite/gcc.target/i386/avx-1.c | 11 - .../gcc.target/i386/avx10_2-rounding-3.c | 5

[PATCH 11/27] Revert "AVX10.2 ymm rounding: Support vfm{sub, subadd}{132, 231, 213}p{s, d, h} intrins"

This reverts commit dd48acbe85ca55dd23ffafbb917ffe559d13b6a3. --- gcc/config/i386/avx10_2roundingintrin.h | 350 -- gcc/config/i386/i386-builtin.def | 18 - gcc/config/i386/sse.md| 2 +- gcc/testsuite/gcc.target/i386/avx-1.c |

[PATCH 04/27] Revert "AVX10.2 ymm rounding: Support vscalefp{s, d, h} intrins"

This reverts commit 1f86cf06c7897f6ab467443b5fe8789cc95fe0c4. --- gcc/config/i386/avx10_2roundingintrin.h | 182 -- gcc/config/i386/i386-builtin.def | 3 - gcc/config/i386/sse.md| 2 +- gcc/testsuite/gcc.target/i386/avx-1.c |

[PATCH 09/27] Revert "AVX10.2 ymm rounding: Support vfnmsub{132, 231, 213}p{s, d, h} intrins"

This reverts commit 0983d406ae2e84394b25248865f51c686b119a57. --- gcc/config/i386/avx10_2roundingintrin.h | 181 -- gcc/config/i386/i386-builtin.def | 9 - gcc/config/i386/sse.md| 2 +- gcc/testsuite/gcc.target/i386/avx-1.c |

[PATCH 12/27] Revert "AVX10.2 ymm rounding: Support vfmaddcph and vfmaddsub{132, 231, 213}p{s, d, h} intrins"

This reverts commit cfbc94eaf167ae7aecd21ee6054556e1cf9d7143. --- gcc/config/i386/avx10_2roundingintrin.h | 238 -- gcc/config/i386/i386-builtin.def | 13 - gcc/config/i386/sse.md| 4 +- gcc/testsuite/gcc.target/i386/avx-1.c |

[PATCH 03/27] Revert "AVX10.2 ymm rounding: Support vsqrtp{s, d, h} and vsubp{s, d, h} intrins"

This reverts commit 7f62e7104ebc11c4570745972a023579922ef265. --- gcc/config/i386/avx10_2roundingintrin.h | 339 -- gcc/config/i386/i386-builtin.def | 6 - gcc/testsuite/gcc.target/i386/avx-1.c | 6 - .../gcc.target/i386/avx10_2-rounding-3.c | 5

[PATCH 10/13] i386: Change mnemonics from VCVTNE2PH2[B, H]F8 to VCVT2PH2[B, H]F8

gcc/ChangeLog: PR target/118270 * config/i386/avx10_2-512convertintrin.h: Change intrin and builtin name according to new mnemonics. * config/i386/avx10_2convertintrin.h: Ditto. * config/i386/i386-builtin.def (BDESC): Ditto. * config/i386/sse.md

[PATCH 11/13] i386: Change mnemonics from VCVTNEPH2[B, H]F8 to VCVTPH2[B, H]F8

gcc/ChangeLog: PR target/118270 * config/i386/avx10_2-512convertintrin.h: Change intrin and builtin name according to new mnemonics. * config/i386/avx10_2convertintrin.h: Ditto. * config/i386/i386-builtin.def (BDESC): Ditto. * config/i386/sse.md

RE: [PATCH] i386: Change mnemonics from TCVTROWPS2PBF16[H,L] to TCVTROWPS2BF16[H,L]

> From: Liu, Hongtao > Sent: Friday, January 3, 2025 6:33 PM > > > From: Jiang, Haochen > > Sent: Friday, January 3, 2025 4:55 PM > > > > Hi all, > > > > The mnemonics for TCVTROWPS2PBF16[H,L] has been changed to > > TCVTROWPS2BF16[H,L] in ISE0

RE: [PATCH] i386: Change mnemonics from TCVTROWPS2PBF16[H,L] to TCVTROWPS2BF16[H,L]

> -Original Message- > From: Jiang, Haochen > Sent: Friday, January 3, 2025 4:55 PM > To: gcc-patches@gcc.gnu.org > Cc: Liu, Hongtao ; ubiz...@gmail.com > Subject: [PATCH] i386: Change mnemonics from TCVTROWPS2PBF16[H,L] to > TCVTROWPS2BF16[H,L] > > Hi

[PATCH] i386: Change mnemonics from TCVTROWPS2PBF16[H, L] to TCVTROWPS2BF16[H, L]

Hi all, The mnemonics for TCVTROWPS2PBF16[H,L] has been changed to TCVTROWPS2BF16[H,L] in ISE056. There will be also some more BF16 mnemonics change upcoming, which will fix the regression in PR118270. Bootstraped and tested on x86_64-pc-linux-gnu. Ok for trunk? Ref: https://cdrdv2.intel.com/v1

Re:[pushed] [PATCH] LoongArch: Fix bugs in insn patterns lasx_xvrepl128vei_b/h/w/d_internal

Pushed to r15-6489. 在 2024/12/30 上午10:37, Guo Jie 写道: There are two aspects that affect the matching of instruction templates: 1. vec_duplicate is redundant in the following operations. set (match_operand:V4DI ...) (vec_duplicate:V4DI (vec_select:V4DI ...)) 2. The range of values

[PATCH] LoongArch: Fix bugs in insn patterns lasx_xvrepl128vei_b/h/w/d_internal

There are two aspects that affect the matching of instruction templates: 1. vec_duplicate is redundant in the following operations. set (match_operand:V4DI ...) (vec_duplicate:V4DI (vec_select:V4DI ...)) 2. The range of values for testing predicate const_8_to_15_operand and const_16_t

[PATCH 3/4] libstdc++: Use alias-declarations in bits/hashtable_policy, h

This file is only for C++11 and later, so replace typedefs with alias-declarations for clarity. Also remove redundant std:: qualification on size_t, ptrdiff_t etc. We can also remove the result_type, first_argument_type and second_argument_type typedefs from the range hashers. We don't need those

gccrs: Remove unused files 'gcc/rust/typecheck/rust-hir-type-check-toplevel.{cc,h}' (was: [PATCH] gccrs: Remove unused files)

added a bit more context to your Git commit log, and then pushed to trunk branch in commit 8173d0a4b75ae2b25e9ed8b4ed8bdc39c3438560 "gccrs: Remove unused files 'gcc/rust/typecheck/rust-hir-type-check-toplevel.{cc,h}'", see attached. Grüße Thomas >From 8173d0a4b75ae2b

[pushed] libstdc++: stdc++.h and

section (including ), but most were left in place, so we have redundant includes of most hosted headers. libstdc++-v3/ChangeLog: * include/precompiled/stdc++.h: is C++20. --- libstdc++-v3/include/precompiled/stdc++.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff

Re: [PATCH] i386: Fix up ix86_expand_int_compare with TImode comparisons of SUBREGs from V8{H,B}Fmode against zero [PR116921]

On Fri, Oct 4, 2024 at 12:12 PM Jakub Jelinek wrote: > > Hi! > > The following testcase ICEs, because the ix86_expand_int_compare > optimization to use {,v}ptest assumes there are instructions for all > 16-byte vector modes. That isn't the case, we only have one for > V16QI, V8HI, V4SI, V2DI, V1T

[PATCH] i386: Fix up ix86_expand_int_compare with TImode comparisons of SUBREGs from V8{H,B}Fmode against zero [PR116921]

Hi! The following testcase ICEs, because the ix86_expand_int_compare optimization to use {,v}ptest assumes there are instructions for all 16-byte vector modes. That isn't the case, we only have one for V16QI, V8HI, V4SI, V2DI, V1TI, V4SF and V2DF, not for V8HF nor V8BF. The following patch fixes

[pushed] diagnostics: move output formats from diagnostic.{c, h} to their own files

In particular, move the classic text output code to a diagnostic-text.cc (analogous to -json.cc and -sarif.cc). No functional change intended. Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to trunk as r15-3201-g92c5265d22afaa. gcc/ChangeLog: * Makefile.in (OBJS-li

[PATCH 22/22] AVX10.2 ymm rounding: Support vsqrtp{s, d, h} and vsubp{s, d, h} intrins

From: "Hu, Lin1" gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin.def (BDESC): Add new builtins. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add new builtin test. * gcc.target/i386/sse-13.c: Ditto. * g

[PATCH 17/22] AVX10.2 ymm rounding: Support vgetexpp{s, d, h} and vgetmantp{s, d, h} intrins

From: "Hu, Lin1" gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-expand.cc (ix86_expand_round_builtin):

[PATCH 20/22] AVX10.2 ymm rounding: Support vreducep{s, d, h} and vrndscalep{s, d, h} intrins

From: "Hu, Lin1" gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/sse.md: (reducep): Add condition check. (_rndscale): Ditto. gcc/testsuite/ChangeLog:

[PATCH 21/22] AVX10.2 ymm rounding: Support vscalefp{s,d,h} intrins

From: "Hu, Lin1" gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. * config/i386/sse.md: (_scalef): Add condition check. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c:

[PATCH 14/22] AVX10.2 ymm rounding: Support vfm{sub, subadd}{132, 231, 213}p{s, d, h} intrins

From: "Hu, Lin1" gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/sse.md: (_fmsub__mask): Add conditi

[PATCH 01/22] AVX10.2 ymm rounding: Support vadd{s, d, h} and vcmp{s, d, h} intrins

From: "Hu, Lin1" gcc/ChangeLog: * config.gcc: Add avx10_2roundingintrin.h. * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle

[PATCH 18/22] AVX10.2 ymm rounding: Support v{max, min}p{s, d, h} intrins

From: "Hu, Lin1" gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin.def (BDESC): Add new builtins. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add new builtin test. * gcc.target/i386/sse-13.c: Ditto. * g

[PATCH 19/22] AVX10.2 ymm rounding: Support vmulp{s, d, h} and vrangep{s, d} intrins

From: "Hu, Lin1" gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-expand.cc (ix86_expand_round_builtin):

[PATCH 15/22] AVX10.2 ymm rounding: Support vfmulcph and vfnmadd{132, 231, 213}p{s, d, h} intrins

From: "Hu, Lin1" gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin.def (BDESC): Add new builtins. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add new builtin test. * gcc.target/i386/sse-13.c: Ditto. * g

[PATCH 16/22] AVX10.2 ymm rounding: Support vfnmsub{132, 231, 213}p{s, d, h} intrins

From: "Hu, Lin1" gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/sse.md: (_fnmsub__mask3): Add condition check. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c:

[PATCH 09/22] AVX10.2 ymm rounding: Support vcvttps2{, u}{dq, qq} and vcvtu{dq, qq}2p{s, d, h} intrins

From: "Hu, Lin1" gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/sse.md (unspec_fix_truncv8sfv8si2):

[PATCH 07/22] AVX10.2 ymm rounding: Support vcvtqq2p{s, d, h} and vcvttpd2{, u}{dq, qq} intrins

From: "Hu, Lin1" gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-expand.cc (ix86_expand_round_builtin):

[PATCH 13/22] AVX10.2 ymm rounding: Support vfmaddcph and vfmaddsub{132, 231, 213}p{s, d, h} intrins

From: "Hu, Lin1" gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/sse.md: (_fmaddsub__mask): Add cond

[PATCH 10/22] AVX10.2 ymm rounding: Support vcvt{, u}w2ph and vdivp{s, d, h} intrins

From: "Hu, Lin1" gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-expand.cc (ix86_expand_round_builtin):

[PATCH 02/22] AVX10.2 ymm rounding: Support vcvtdq2p{s, h} and vcvtpd2p{s, h} intrins

From: "Hu, Lin1" gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: Add new intrins. * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-expand.cc (ix86_expand_round_built

[PATCH 12/22] AVX10.2 ymm rounding: Support vfmadd{132, 231, 213}p{s, d, h} intrins

From: "Hu, Lin1" gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: New intrins. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/sse.md: (_fmadd__mask3): Add condition check. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c:

[PATCH 1/7] diagnostics: move simple_diagnostic_{path, thread, event} to their own .h/cc

As work towards eliminating the dependency on "tree" from path-printing, move these classes to a new simple-diagnostic-path.h/cc. No functional change intended. gcc/analyzer/ChangeLog: * checker-path.h: Include "simple-diagnostic-path.h". gcc/ChangeLog: * Makefile.in (OBJS): Add

Re: [PATCH] s390: testsuite: Remove xfail for vpopct{b,h}

On 4/22/24 08:01, Stefan Schulze Frielinghaus wrote: > Starting with r14-9316-g7890836de20912 patterns for vpopct{b,h} are also > detected. Thus, remove xfails. > > gcc/testsuite/ChangeLog: > > * gcc.target/s390/vxe/popcount-1.c: Remove xfail. Ok. Thanks! Andrea

[PATCH] s390: testsuite: Remove xfail for vpopct{b,h}

Starting with r14-9316-g7890836de20912 patterns for vpopct{b,h} are also detected. Thus, remove xfails. gcc/testsuite/ChangeLog: * gcc.target/s390/vxe/popcount-1.c: Remove xfail. --- Ok for mainline? gcc/testsuite/gcc.target/s390/vxe/popcount-1.c | 4 ++-- 1 file changed, 2

[PATCH] Fix testcase for platform without gnu/stubs-x32.h

target maybe_x32 doesn't check if platform has gnu/stubs-x32.h, but it's included by stdint.h in the testcase. Adjust testcase: remove stdint.h, use 'typedef long long int64_t' instead. Commit as an obvious patch. gcc/testsuite/ChangeLog: PR target/113711 *

[committed] libgomp.c/declare-variant-4.h: Fix used variant function for gfx1030/gfx1100

scan-amdgcn-amdhsa-offload-tree-dump optimized "= gfx1100 \\(\\);" Committed as obvious as r14-8488-gcb366731e767e2 Tobias commit cb366731e767e2dec158c8c4a495fe2ccbd550ff Author: Tobias Burnus Date: Mon Jan 29 11:06:15 2024 +0100 libgomp.c/declare-variant-4.h: Fix used varian

Re: [PATCH] libstdc++: Add and to stdc++.h

* include/precompiled/stdc++.h [_GLIBCXX_HOSTED]: Include > and for C++23 and C++26 respectively. > --- > libstdc++-v3/include/precompiled/stdc++.h | 5 + > 1 file changed, 5 insertions(+) > > diff --git a/libstdc++-v3/include/precompiled/stdc++.h > b/l

[PATCH] libstdc++: Add and to stdc++.h

Tested on x86_64-pc-linux-gnu, does this look OK for trunk? -- >8 -- libstdc++-v3/ChangeLog: * include/precompiled/stdc++.h [_GLIBCXX_HOSTED]: Include and for C++23 and C++26 respectively. --- libstdc++-v3/include/precompiled/stdc++.h | 5 + 1 file changed, 5 inserti

[committed] c++: testsuite: Remove testsuite_tr1.h includes

This patch removes the testsuite_tr1.h dependency from g++.dg/ext/is_*.C tests since the header is supposed to be used only by libstdc++, not front-end. This also includes test code consistency fixes. For the record this fixes the test failures reported at https://gcc.gnu.org/pipermail/gcc

Re: [PATCH] testsuite: Remove testsuite_tr1.h

On Thu, Dec 21, 2023 at 11:38 AM Jason Merrill wrote: > > On 12/21/23 10:52, Patrick Palka wrote: > > On Thu, Dec 21, 2023 at 8:29 AM Patrick Palka wrote: > >> > >> On Wed, 20 Dec 2023, Ken Matsui wrote: > >> > >>> This patch removes th

Re: [PATCH] testsuite: Remove testsuite_tr1.h

On 12/21/23 10:52, Patrick Palka wrote: On Thu, Dec 21, 2023 at 8:29 AM Patrick Palka wrote: On Wed, 20 Dec 2023, Ken Matsui wrote: This patch removes the testsuite_tr1.h dependency from g++.dg/ext/is_*.C tests since the header is supposed to be used only by libstdc++, not front-end. This

Re: [PATCH] testsuite: Remove testsuite_tr1.h

On Thu, Dec 21, 2023 at 8:29 AM Patrick Palka wrote: > > On Wed, 20 Dec 2023, Ken Matsui wrote: > > > This patch removes the testsuite_tr1.h dependency from g++.dg/ext/is_*.C > > tests since the header is supposed to be used only by libstdc++, not > > front-end. T

Re: [PATCH] testsuite: Remove testsuite_tr1.h

On Wed, 20 Dec 2023, Ken Matsui wrote: > This patch removes the testsuite_tr1.h dependency from g++.dg/ext/is_*.C > tests since the header is supposed to be used only by libstdc++, not > front-end. This also includes test code consistency fixes. LGTM > > gcc/test

[PATCH] testsuite: Remove testsuite_tr1.h

This patch removes the testsuite_tr1.h dependency from g++.dg/ext/is_*.C tests since the header is supposed to be used only by libstdc++, not front-end. This also includes test code consistency fixes. gcc/testsuite/ChangeLog: * g++.dg/ext/is_array.C: Remove testsuite_tr1.h. Add

Re: [PATCH 1/3] s390: Recognize further vpdi and vmr{l,h} pattern

On 11/9/23 09:22, Stefan Schulze Frielinghaus wrote: > Deal with cases where vpdi and vmr{l,h} are still applicable if the > operands of those instructions are swapped. For example, currently for > > V2DI foo (V2DI x) > { > return (V2DI) {x[1], x[0]}; > } > > the as

[PATCH 1/3] s390: Recognize further vpdi and vmr{l,h} pattern

Deal with cases where vpdi and vmr{l,h} are still applicable if the operands of those instructions are swapped. For example, currently for V2DI foo (V2DI x) { return (V2DI) {x[1], x[0]}; } the assembler sequence vlgvg %r1,%v24,1 vzero %v0 vlvgg %v0,%r1,0 vmrhg %v24,%v0,%v24 is

[pushed] analyzer: move class record_layout to its own .h/.cc

d on material in region-model.cc. * record-layout.h: Likewise. * region-model.cc: Include "analyzer/record-layout.h". (class record_layout): Move to record-layout.cc and .h --- gcc/Makefile.in | 1 + gcc/analyzer/record-l

Re: [PATCH] RISC-V: Prohibit combination of 'E' and 'H'

On 10/21/23 19:33, Tsukasa OI wrote: Hmm, I generally agree with your opinion and I made a board file for DejaGnu (running qemu-riscv64) to run "make check-gcc RUNTESTFLAGS='--target_board=riscv-sim riscv.exp'" because it already contains many execute tests (and annoys me if I don't do that)

Re: [PATCH] RISC-V: Prohibit combination of 'E' and 'H'

; base integer ISA with 32 x >>> registers (RV32I or RV64I), not RV32E, which has only 16 x registers. >> >> Also in the latest draft, it also prohibits RV64E with the 'H' extension. >> This commit prohibits the combination of 'E' and '

Re: [PATCH] RISC-V: Prohibit combination of 'E' and 'H'

lso in the latest draft, it also prohibits RV64E with the 'H' extension. This commit prohibits the combination of 'E' and 'H' extensions. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse): Prohibit 'E&#x

[PATCH] RISC-V: Prohibit combination of 'E' and 'H'

prohibits RV64E with the 'H' extension. This commit prohibits the combination of 'E' and 'H' extensions. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_subset_list::parse): Prohibit 'E' and 'H' combinations. gcc/te

Re: [PATCH] testsuite: Improve test in dg-require-python-h

Eric Feng writes: > Thanks for the patch, Thiago. I've pushed it to trunk: > https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=6785917c9103e18bba0d718ac3b65a386d9a14f7. Thank you, Eric and Dave. > On Fri, Aug 18, 2023 at 2:11 PM David Malcolm wrote: >> >> On Thu,

Re: [PATCH] testsuite: Improve test in dg-require-python-h

Thanks for the patch, Thiago. I've pushed it to trunk: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=6785917c9103e18bba0d718ac3b65a386d9a14f7. Best, Eric On Fri, Aug 18, 2023 at 2:11 PM David Malcolm wrote: > > On Thu, 2023-08-17 at 23:30 -0300, Thiago Jung Bauermann wrote: > >

Re: [PATCH] testsuite: Improve test in dg-require-python-h

Excess errors: > /usr/include/python3.10/pyconfig.h:9:12: fatal error: aarch64-linux- > gnu/python3.10/pyconfig.h: No such file or directory > compilation terminated. > > So try to compile a test file so that the testcase can be marked as > unsupported instead. > > gcc/

[PATCH] testsuite: Improve test in dg-require-python-h

-gnu/python3.10/pyconfig.h: No such file or directory compilation terminated. So try to compile a test file so that the testcase can be marked as unsupported instead. gcc/testsuite/ChangeLog: * gcc/testsuite/lib/target-supports.exp (dg-require-python-h): Test whether Python.h can

Re: [PATCH ver 3] rs6000: Fix __builtin_altivec_vcmpne{b,h,w} implementation

ions, > > execute_test_functions) moved to vec-cmpne.h. Added > > scan-assembler-times for vcmpequb, vcmpequh, vcmpequw. > > s/ moved/: Move/ => "... execute_test_functions): Move " > > s/Added/Add/ Fixed both issues.

Re: [PATCH ver 3] rs6000: Fix __builtin_altivec_vcmpne{b,h,w} implementation

t; built-in functionality. Retested the patch on Power 8 LE/BE, Power > 9LE/BE and Power 10 LE with no regressions. > > The following patch cleans up the definition for the > __builtin_altivec_vcmpne{b,h,w}. The current implementation implies > that the built-in is only supported

[PATCH ver 3] rs6000: Fix __builtin_altivec_vcmpne{b,h,w} implementation

regressions. The following patch cleans up the definition for the __builtin_altivec_vcmpne{b,h,w}. The current implementation implies that the built-in is only supported on Power 9 since it is defined under the Power 9 stanza. However the built-in has no ISA restrictions as stated in the Power Vector

Re: [PATCH v2] rs6000: Fix __builtin_altivec_vcmpne{b,h,w} implementation

he instruction generation and a runnable test to verify the > > built-in functionality. Retested the patch on Power 8 LE/BE, Power > > 9LE/BE and Power 10 LE with no regressions. > > > > The following patch cleans up the definition for the > > __builtin_altivec_vcmp

Re: [PATCH v2] rs6000: Fix __builtin_altivec_vcmpne{b,h,w} implementation

e patch on Power 8 LE/BE, Power 9LE/BE > and Power 10 LE with no regressions. > > The following patch cleans up the definition for the > __builtin_altivec_vcmpne{b,h,w}. The current implementation implies > that the built-in is only supported on Power 9 since it is defined > un

[PATCH v2] rs6000: Fix __builtin_altivec_vcmpne{b,h,w} implementation

up the definition for the __builtin_altivec_vcmpne{b,h,w}. The current implementation implies that the built-in is only supported on Power 9 since it is defined under the Power 9 stanza. However the built-in has no ISA restrictions as stated in the Power Vector Intrinsic Programming Reference

Re: [PATCH] rs6000: Fix __builtin_altivec_vcmpne{b,h,w} implementation

Power 8 LE/BE, Power 9 LE/BE and Power > > 10 > > LE with no regressions. > > > > Please let me know if the patch is acceptable for > > mainline. Thanks. > > > > Carl > > > > -- > > rs6000:

Re: [PATCH] rs6000: Fix __builtin_altivec_vcmpne{b,h,w} implementation

h has been tested on Power 8 LE/BE, Power 9 LE/BE and Power 10 > LE with no regressions. > > Please let me know if the patch is acceptable for mainline. Thanks. > > Carl > > ------ > rs6000: Fix __builtin_altivec_v

[PATCH] rs6000: Fix __builtin_altivec_vcmpne{b,h,w} implementation

Carl -- rs6000: Fix __builtin_altivec_vcmpne{b,h,w} implementation The current built-in definitions for vcmpneb, vcmpneh, vcmpnew are defined under the Power 9 section of r66000-builtins. This implies they are only supported on Power 9 and above when in fact they are de

RE: [PATCH] RISC-V: Fix typo of multiple_rgroup-2.h

@gmail.com; Li, Pan2 Subject: Re: [PATCH] RISC-V: Fix typo of multiple_rgroup-2.h ok On Mon, May 22, 2023 at 6:02 PM wrote: > > From: Juzhe-Zhong > > Just notice this following fail in the regression: > FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.c (test for

Re: [PATCH] RISC-V: Fix typo of multiple_rgroup-2.h

oup_run-2.c (test for > excess errors) > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.h: Fix typo > > --- > .../gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.h| 2 +- > 1 file changed, 1 insertion(+), 1 deletion

[PATCH] RISC-V: Fix typo of multiple_rgroup-2.h

: * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.h: Fix typo --- .../gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.h| 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup-2.h b/gcc/testsuite/gcc.target

Re: RISC-V: Added support clmul[r,h] instructions for Zbc extension.

On 4/27/23 08:29, Karen Sargsyan via Gcc-patches wrote: clmul[h] instructions were added only for the ZBKC extension. This patch includes them in the ZBC extension too. Besides, added support of 'clmulr' instructions for ZBC extension. gcc/ChangeLog: * config/riscv/bitmanip

RISC-V: Added support clmul[r,h] instructions for Zbc extension.

clmul[h] instructions were added only for the ZBKC extension. This patch includes them in the ZBC extension too. Besides, added support of 'clmulr' instructions for ZBC extension. gcc/ChangeLog: * config/riscv/bitmanip.md: Added clmulr instruction. * config/riscv/riscv-b

Re: [PATCH] RISC-V: Add h extension support

Thanks for the review, committed :) On Mon, Oct 24, 2022 at 11:05 PM Jeff Law via Gcc-patches wrote: > > > On 10/24/22 03:55, Kito Cheng wrote: > > `h` was the prefix of multi-letter extension name, but it become a > > extension in later RISC-V isa spec. > > > &

Re: [PATCH] RISC-V: Add h extension support

On 10/24/22 03:55, Kito Cheng wrote: `h` was the prefix of multi-letter extension name, but it become a extension in later RISC-V isa spec. Fortunately we don't have any extension really defined is prefixed with `h`, so we can just change that. gcc/ChangeLog: * common/config/

[PATCH] RISC-V: Add h extension support

`h` was the prefix of multi-letter extension name, but it become a extension in later RISC-V isa spec. Fortunately we don't have any extension really defined is prefixed with `h`, so we can just change that. gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_version_

Re: [PATCH] RISC-V: move struct vector_type_info from *.h to *.cc and change "user_name" into "name".

Committed, thanks :) On Mon, Oct 10, 2022 at 9:58 PM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config/riscv/riscv-vector-builtins.cc (struct vector_type_info): > Move from config/riscv/riscv-vector-builtins.h. > (DEF_RVV_TYPE): Change USER_NAME to NAME. > (r

Re: [PATCH] RISC-V: move struct vector_type_info from *.h to *.cc.

RISC-V: move struct vector_type_info from *.h to *.cc. From: Ju-Zhe Zhong gcc/ChangeLog: * config/riscv/riscv-vector-builtins.cc (struct vector_type_info): Move from riscv-vector-builtins.h. * config/riscv/riscv-vector-builtins.h (struct vector_type_info): Move to riscv-vecto

[PATCH] RISC-V: move struct vector_type_info from *.h to *.cc and change "user_name" into "name".

From: Ju-Zhe Zhong gcc/ChangeLog: * config/riscv/riscv-vector-builtins.cc (struct vector_type_info): Move from config/riscv/riscv-vector-builtins.h. (DEF_RVV_TYPE): Change USER_NAME to NAME. (register_vector_type): Change user_name to name. * config/riscv/riscv-v

[PATCH] RISC-V: move struct vector_type_info from *.h to *.cc.

From: Ju-Zhe Zhong gcc/ChangeLog: * config/riscv/riscv-vector-builtins.cc (struct vector_type_info): Move from riscv-vector-builtins.h. * config/riscv/riscv-vector-builtins.h (struct vector_type_info): Move to riscv-vector-builtins.cc. --- gcc/config/riscv/riscv-vector-builti

Re: [PATCH] dwarf2.h (enum dwarf_source_language): Add new DWARF5 language codes.

On 7/12/22 10:43, Meghan Denny wrote: Updated constants from <https://dwarfstd.org/Languages.php> diff --git a/include/dwarf2.h b/include/dwarf2.h index 40aa5a54f01..87bf764a4fb 100644 --- a/include/dwarf2.h +++ b/include/dwarf2.h [ ... ] I fixed the formatting on the patch and pus

[PATCH] dwarf2.h (enum dwarf_source_language): Add new DWARF5 language codes.

Updated constants from <https://dwarfstd.org/Languages.php> diff --git a/include/dwarf2.h b/include/dwarf2.h index 40aa5a54f01..87bf764a4fb 100644 --- a/include/dwarf2.h +++ b/include/dwarf2.h @@ -373,6 +373,16 @@ enum dwarf_source_language DW_LANG_Fortran03 = 0x0022, DW_LANG_Fortran08 =

Re: [PATCH] testsuite/s390: Change nle -> h in ifcvt tests.

ite/ChangeLog: > > * gcc.target/s390/ifcvt-two-insns-bool.c: Change nle to h. > * gcc.target/s390/ifcvt-two-insns-int.c: Dito. > * gcc.target/s390/ifcvt-two-insns-long.c: Dito. Ok. Thanks! Andreas

[PATCH] testsuite/s390: Change nle -> h in ifcvt tests.

Hi, we have been emitting the "higher" variantes instead of the "not less or equal" ones for a while. Change the test expectations accordingly. OK for trunk? Regards Robin gcc/testsuite/ChangeLog: * gcc.target/s390/ifcvt-two-insns-bool.c: Change nle to h.

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