Committed, thanks :)
On Mon, Oct 10, 2022 at 9:58 PM <juzhe.zh...@rivai.ai> wrote:
>
> From: Ju-Zhe Zhong <juzhe.zh...@rivai.ai>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins.cc (struct vector_type_info):
> Move from config/riscv/riscv-vector-builtins.h.
> (DEF_RVV_TYPE): Change USER_NAME to NAME.
> (register_vector_type): Change user_name to name.
> * config/riscv/riscv-vector-builtins.def (DEF_RVV_TYPE): Change
> USER_NAME to NAME.
> * config/riscv/riscv-vector-builtins.h (struct vector_type_info):
> Move to riscv-vector-builtins.cc.
> (DEF_RVV_TYPE): Change USER_NAME to NAME.
>
> ---
> gcc/config/riscv/riscv-vector-builtins.cc | 28 +++++++++++++++++-----
> gcc/config/riscv/riscv-vector-builtins.def | 2 +-
> gcc/config/riscv/riscv-vector-builtins.h | 20 ++--------------
> 3 files changed, 25 insertions(+), 25 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
> b/gcc/config/riscv/riscv-vector-builtins.cc
> index 0096e32f5e4..7033b1fc176 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> @@ -50,10 +50,26 @@ using namespace riscv_vector;
>
> namespace riscv_vector {
>
> +/* Static information about each vector type. */
> +struct vector_type_info
> +{
> + /* The name of the type as declared by riscv_vector.h
> + which is recommend to use. For example: 'vint32m1_t'. */
> + const char *name;
> +
> + /* ABI name of vector type. The type is always available
> + under this name, even when riscv_vector.h isn't included.
> + For example: '__rvv_int32m1_t'. */
> + const char *abi_name;
> +
> + /* The C++ mangling of ABI_NAME. */
> + const char *mangled_name;
> +};
> +
> /* Information about each RVV type. */
> static CONSTEXPR const vector_type_info vector_types[] = {
> -#define DEF_RVV_TYPE(USER_NAME, NCHARS, ABI_NAME, ARGS...) \
> - {#USER_NAME, #ABI_NAME, "u" #NCHARS #ABI_NAME},
> +#define DEF_RVV_TYPE(NAME, NCHARS, ABI_NAME, ARGS...) \
> + {#NAME, #ABI_NAME, "u" #NCHARS #ABI_NAME},
> #include "riscv-vector-builtins.def"
> };
>
> @@ -151,14 +167,14 @@ register_builtin_types ()
> = TARGET_64BIT ? unsigned_intSI_type_node : long_unsigned_type_node;
>
> machine_mode mode;
> -#define DEF_RVV_TYPE(USER_NAME, NCHARS, ABI_NAME, SCALAR_TYPE, VECTOR_MODE,
> \
> +#define DEF_RVV_TYPE(NAME, NCHARS, ABI_NAME, SCALAR_TYPE, VECTOR_MODE, \
> VECTOR_MODE_MIN_VLEN_32)
> \
> mode = TARGET_MIN_VLEN > 32 ? VECTOR_MODE##mode
> \
> : VECTOR_MODE_MIN_VLEN_32##mode;
> \
> - scalar_types[VECTOR_TYPE_##USER_NAME]
> \
> + scalar_types[VECTOR_TYPE_##NAME] \
> = riscv_v_ext_enabled_vector_mode_p (mode) ? SCALAR_TYPE##_type_node
> \
> : NULL_TREE;
> \
> - vector_modes[VECTOR_TYPE_##USER_NAME]
> \
> + vector_modes[VECTOR_TYPE_##NAME] \
> = riscv_v_ext_enabled_vector_mode_p (mode) ? mode : VOIDmode;
> #include "riscv-vector-builtins.def"
>
> @@ -198,7 +214,7 @@ register_vector_type (vector_type_index type)
> is disabled according to '-march'. */
> if (!vectype)
> return;
> - tree id = get_identifier (vector_types[type].user_name);
> + tree id = get_identifier (vector_types[type].name);
> tree decl = build_decl (input_location, TYPE_DECL, id, vectype);
> decl = lang_hooks.decls.pushdecl (decl);
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins.def
> b/gcc/config/riscv/riscv-vector-builtins.def
> index a9001b3b496..664734b881b 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.def
> +++ b/gcc/config/riscv/riscv-vector-builtins.def
> @@ -32,7 +32,7 @@ along with GCC; see the file COPYING3. If not see
> TARGET_MIN_VLEN > 32. Otherwise the machine mode is VNx1SImode. */
>
> #ifndef DEF_RVV_TYPE
> -#define DEF_RVV_TYPE(USER_NAME, NCHARS, ABI_NAME, SCALAR_TYPE, VECTOR_MODE,
> \
> +#define DEF_RVV_TYPE(NAME, NCHARS, ABI_NAME, SCALAR_TYPE, VECTOR_MODE, \
> VECTOR_MODE_MIN_VLEN_32)
> #endif
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins.h
> b/gcc/config/riscv/riscv-vector-builtins.h
> index 6ca0b073964..ec85e0b1320 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.h
> +++ b/gcc/config/riscv/riscv-vector-builtins.h
> @@ -26,28 +26,12 @@ namespace riscv_vector {
> /* This is for segment instructions. */
> const unsigned int MAX_TUPLE_SIZE = 8;
>
> -/* Static information about each vector type. */
> -struct vector_type_info
> -{
> - /* The name of the type as declared by riscv_vector.h
> - which is recommend to use. For example: 'vint32m1_t'. */
> - const char *user_name;
> -
> - /* ABI name of vector type. The type is always available
> - under this name, even when riscv_vector.h isn't included.
> - For example: '__rvv_int32m1_t'. */
> - const char *abi_name;
> -
> - /* The C++ mangling of ABI_NAME. */
> - const char *mangled_name;
> -};
> -
> /* Enumerates the RVV types, together called
> "vector types" for brevity. */
> enum vector_type_index
> {
> -#define DEF_RVV_TYPE(USER_NAME, ABI_NAME, NCHARS, ARGS...) \
> - VECTOR_TYPE_##USER_NAME,
> +#define DEF_RVV_TYPE(NAME, ABI_NAME, NCHARS, ARGS...) \
> + VECTOR_TYPE_##NAME,
> #include "riscv-vector-builtins.def"
> NUM_VECTOR_TYPES
> };
> --
> 2.36.1
>
