Re: [PATCH v2] RISCV: MIPS prefetch extensions for MIPS RV64 P8700 and can be enabled with xmipscbop.

Hi All, Please do needful with reviewing the below changes (that enable mips custom prefetch instruction ) and your comments helps us to push more changes and stabilize the changes . Thank you ~U On Mon, Jul 21, 2025 at 9:04 AM Umesh Kalappa wrote: > Hi @Jeff Law , > > Please s

Re: [PATCH v2] RISCV: MIPS prefetch extensions for MIPS RV64 P8700 and can be enabled with xmipscbop.

Hi @Jeff Law , Please share your feedback and comments on the below changes . https://patchwork.sourceware.org/project/gcc/patch/20250717051448.733449-1-ukalappa.m...@gmail.com/ Thank you ~U On Thu, Jul 17, 2025 at 10:44 AM Umesh Kalappa wrote: > Updated the testcase for the prefe

[PATCH v2] RISCV: MIPS prefetch extensions for MIPS RV64 P8700 and can be enabled with xmipscbop.

Updated the testcase for the prefetch write too. gcc/ChangeLog: * config/riscv/riscv-ext-mips.def (DEFINE_RISCV_EXT): Added mips prefetch extension. * config/riscv/riscv-ext.def: Likewise. * config/riscv/riscv-ext.opt: Generated file. * config/riscv/riscv.md (prefet

[PATCH v1]RISCV: MIPS prefetch extensions for MIPS RV64 P8700 and can be enabled with xmipscbop.

Fixed the regress that caused "pr118241.c" failure and tested "runtest --tool gcc --target_board='riscv-sim/-march=rv64gc_zba_zbb_zbc_zbs/-mabi=lp64/-mcmodel=medlow' riscv.exp" and 32 bit too lint warnings can be ignored for riscv-ext.opt. gcc/ChangeLog: * config/riscv/riscv-e

[PATCH v0]RISCV: MIPS prefetch extensions for MIPS RV64 P8700 and can be enabled with xmipscbop.

Please refer "MIPS RV64 P8700/P8700-F Multiprocessing System Programmer’s Guide" for more info on the extension at https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf lint warnings can be ignored for riscv-ext.opt. gcc/ChangeLog: * confi

Re: [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.

ich still looks like it needs modification to adhere to the latest GNU code style standrad . Thank you again, ~U On Tue, Jul 15, 2025 at 10:08 PM Jeff Law wrote: > > > On 7/14/25 11:34 PM, Umesh Kalappa wrote: > > Updated the test for rv32 accordingly and no regress found for runs

Re: [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.

Hi @Jeff Law and all, https://patchwork.sourceware.org/project/gcc/patch/20250715053410.557741-1-ukalappa.m...@gmail.com/ looks ok to us ,please let me any comments for your end , Thank you ~U On Tue, Jul 15, 2025 at 11:04 AM Umesh Kalappa wrote: > Updated the test for rv32 accordingly

[PATCH v5] RISC-V: Mips P8700 Conditional Move Support.

Updated the test for rv32 accordingly and no regress found for runs like "runtest --tool gcc --target_board='riscv-sim/-march=rv32gc_zba_zbb_zbc_zbs/-mabi=ilp32d/-mcmodel=medlow' riscv.exp" and "runtest --tool gcc --target_board='riscv-sim/-march=rv64gc_zba_zbb_zbc_zbs/-mabi=lp64d/-mcmodel=med

[PATCH v4] RISC-V: Mips P8700 Conditional Move Support.

Fixed the testcase for the commandline typo error and no regress found for "runtest --tool gcc --target_board='riscv-sim/-mtune=mips-p8700 ' riscv.exp" run. gcc/ChangeLog: *config/riscv/riscv-cores.def(RISCV_CORE): Updated the supported march. *config/riscv/riscv-ext-mips.def(DEF

Re: [PATCH v3] RISC-V: Mips P8700 Conditional Move Support.

Hi Jeff and others , Sent the latest update patch and the issue with testcase for the types like long long and unsigned long long . Please pass your comments and the suggestions . Thank you ~U On Mon, Jul 14, 2025 at 5:42 PM Umesh Kalappa wrote: > Thank you Jeff and let us verify from

[PATCH v4] RISC-V: Mips P8700 Conditional Move Support.

Please ignore the previous changes and Jeff thank you for the info and issue with the testcase. Updated testcase(long long is not supported in C90) and lint warnings. gcc/ChangeLog: *config/riscv/riscv-cores.def(RISCV_CORE): Updated the supported march. *config/riscv/riscv-ext-

[PATCH v4] RISC-V: Mips P8700 Conditional Move Support.

Jeff thank you for the info and issue with the testcase. Updated testcase(long long is not supported in C90) and lint warnings. gcc/ChangeLog: *config/riscv/riscv-cores.def(RISCV_CORE): Updated the supported march. *config/riscv/riscv-ext-mips.def(DEFINE_RISCV_EXT): New f

Re: [PATCH v3] RISC-V: Mips P8700 Conditional Move Support.

Thank you Jeff and let us verify from our end and come back . ~U On Mon, Jul 14, 2025 at 5:36 PM Jeff Law wrote: > > > On 7/14/25 5:58 AM, Umesh Kalappa wrote: > > Hi Jeff and Marco, > > > > Please pass your comments on the below changes and do needful. > The

Re: [PATCH v3] RISC-V: Mips P8700 Conditional Move Support.

Hi Jeff and Marco, Please pass your comments on the below changes and do needful. Thank you ~U On Sun, Jul 6, 2025 at 12:56 PM Umesh Kalappa wrote: > Hi @Jeff Law and @ma...@orcam.me.uk > , > > Please have a look at the updated patch for conditional move support and >

Re: [PATCH v3] RISC-V: Mips P8700 Conditional Move Support.

Hi @Jeff Law and @ma...@orcam.me.uk , Please have a look at the updated patch for conditional move support and any comments or suggestions please let us know ? Thank you ~U On Wed, Jul 2, 2025 at 12:46 PM Umesh Kalappa wrote: > Indentation are updated accordingly and no regress fo

[PATCH v3] RISC-V: Mips P8700 Conditional Move Support.

Indentation are updated accordingly and no regress found. gcc/ChangeLog: *config/riscv/riscv-cores.def(RISCV_CORE): Updated the supported march. *config/riscv/riscv-ext-mips.def(DEFINE_RISCV_EXT): New file added for mips conditional mov extension. *config/riscv/ris

[PATCH v2] RISC-V: Updated march , that aligned with mips-p8700

Refactored ccmov insn rtl template to use code_iterator and fixed the indentation. No regressions are found for "runtest --tool gcc --target_board='riscv-sim/-mabi=lp64d/-mtune=mips-p8700/-O2 ' riscv.exp" *config/riscv/riscv-cores.def(RISCV_CORE):Updated the supported march. *con

Re: [PATCH V1] RISC-V:Add the MIPS P8700 conditional move extension instruction support.

>>Look in contrib/ I think his work is still in there. thank you @Jeff Law ,the check_GNU_style.sh was helpful to fix the indent/spaces issues : ~U On Tue, Jul 1, 2025 at 4:03 AM Jeff Law wrote: > > > On 6/30/25 12:04 AM, Umesh Kalappa wrote: > > Thank you @Jeff

Re: [PATCH V1] RISC-V:Add the MIPS P8700 conditional move extension instruction support.

Thank you @Jeff Law for the comments and >>I suspect there's something goofy in the indentation in the block above. like clang-format ,does gcc have a code formatter we can use ? Thank you again ~U On Mon, Jun 30, 2025 at 12:33 AM Jeff Law wrote: > > > On 6/13/25 9:

Re: [PATCH V1] RISC-V:Add the MIPS P8700 conditional move extension instruction support.

Hi @Jeff Lawand all, Please have a look at the below changes that were suggested and tested. Thank you ~U On Fri, Jun 13, 2025 at 8:31 PM Umesh Kalappa wrote: > Addressed the most of comments and tried to refactor the > riscv_expand_conditional_move() to some extent. > > No

Re: [PATCH] RISC-V: Use scratch reg for Rd ,so that src/rs2 is not clobbered for Store-Conditional.

Agree @Jeff and updated the testcase . Thank you ~Y On Tue, Jun 17, 2025 at 8:46 AM Jeff Law wrote: > > > On 6/11/25 2:47 AM, Umesh Kalappa wrote: > > gcc/ChangeLog: > > > > * config/riscv/sync.md (lrsc_atomic_exchange): > > Use the scratch

[PATCH v1] RISC-V: Use scratch reg for Rd , so that src/rs2 is not clobbered for Store-Conditional.

Testcase update with no regressed found for the following the changes. gcc/ChangeLog: * config/riscv/sync.md (lrsc_atomic_exchange): Use the scratch reg for rd. gcc/testsuite/ChangeLog: * gcc.target/riscv/zalrsc.c: New test. --- gcc/config/riscv/sync.md

[PATCH V1] RISC-V:Add the MIPS P8700 conditional move extension instruction support.

Addressed the most of comments and tried to refactor the riscv_expand_conditional_move() to some extent. No regressions are found for "runtest --tool gcc --target_board='riscv-sim/-mabi=lp64d/-mtune=mips-p8700/-O2 ' riscv.exp" *config/riscv/riscv-cores.def(RISCV_CORE):Updated the suppor

Re: [PATCH] RISC-V: Use scratch reg for Rd , so that src/rs2 is not clobbered for Store-Conditional.

thank you @kito.ch...@sifive.com and @Jeff Law ,can you someone please commit the same for us ,if others don't have any comments on these changes . ~U On Thu, Jun 12, 2025 at 4:24 AM Jeff Law wrote: > > > On 6/11/25 3:25 AM, Kito Cheng wrote: > > LGTM, but I would like to make sure either

[PATCH] RISC-V: Use scratch reg for Rd , so that src/rs2 is not clobbered for Store-Conditional.

gcc/ChangeLog: * config/riscv/sync.md (lrsc_atomic_exchange): Use the scratch reg for rd. gcc/testsuite/ChangeLog: * gcc.target/riscv/zalrsc.c: New test. --- gcc/config/riscv/sync.md| 11 +-- gcc/testsuite/gcc.target/riscv/zalrsc.c | 13 ++

Re: [PATCH] RISC-V:Add the MIPS P8700 conditional move extension instruction support.

;>then have two subroutines, Well ,it makes sense to refactor to have two subroutines . Thank you again for your time ,we will make changes and will send the updated patch soon . ~U On Wed, Jun 4, 2025 at 8:22 PM Jeff Law wrote: > > > On 5/27/25 5:06 AM, Umesh Kalappa wro

Re: [PATCH] RISC-V:Add the MIPS P8700 conditional move extension instruction support.

Hi @Jeff Law , @pal...@dabbelt.com and all , Please can you pass your comments on the below changes ,thank you ~U On Tue, May 27, 2025 at 4:36 PM Umesh Kalappa wrote: > The P8700 is a high-performance processor from MIPS by extending RISCV with > the MIPS custom instruction a

Re: [PATCH] RISC-V:Add the MIPS P8700 conditional move extension instruction support.

Hi all, Sorry for the noise ,looks like patch was truncated and will be sending a new email with proper patch for the same. Thank you and again my apologies for the noise. ~U On Tue, May 27, 2025 at 3:41 PM Umesh Kalappa wrote: > The P8700 is a high-performance processor from MIPS

[PATCH] RISC-V:Add the MIPS P8700 conditional move extension instruction support.

The P8700 is a high-performance processor from MIPS by extending RISCV with the MIPS custom instruction and the following changes are added to enable the conditional move support from mips No regressions are found for "runtest --tool gcc --target_board='riscv-sim/-mabi=lp64d/-mcmodel=medlow/-mtu

[PATCH] RISC-V:Add the MIPS P8700 conditional move extension instruction support.

The P8700 is a high-performance processor from MIPS by extending RISCV with the MIPS custom instruction and the following changes are added to enable the conditional move support from mips. No regression found for "runtest --tool gcc --target_board='riscv-sim/-mabi=lp64d/-mcmodel=medlow/-mtune=m

Re: [PATCH v2 1/2] The following changes enable P8700 processor for RISCV and P8700 is a high-performance processor from MIPS by extending RISCV with custom instructions.

Tue, May 20, 2025 at 11:26 PM Jeff Law wrote: > > > On 5/19/25 1:02 AM, Umesh Kalappa wrote: > > --- > > gcc/config/riscv/mips-p8700.md | 139 +++ > > gcc/config/riscv/riscv-cores.def | 5 ++ > > gcc/config/riscv/riscv-opts.

Re: [PATCH v2 2/2] MIPS p8700 doesn't have vector extension and added the dummies reservation for the same.

>> I've pushed this to the trunk as well. Thank you Jeff , ~U On Tue, May 20, 2025 at 11:29 PM Jeff Law wrote: > > > On 5/19/25 1:03 AM, Umesh Kalappa wrote: > > --- > > gcc/config/riscv/mips-p8700.md | 28 > > 1 file change

[PATCH v2 1/2] The following changes enable P8700 processor for RISCV and P8700 is a high-performance processor from MIPS by extending RISCV with custom instructions.

--- gcc/config/riscv/mips-p8700.md | 139 +++ gcc/config/riscv/riscv-cores.def | 5 ++ gcc/config/riscv/riscv-opts.h| 3 +- gcc/config/riscv/riscv.cc| 22 + gcc/config/riscv/riscv.md| 3 +- 5 files changed, 170 insertions(+), 2 deletions

[PATCH v2 2/2] MIPS p8700 doesn't have vector extension and added the dummies reservation for the same.

--- gcc/config/riscv/mips-p8700.md | 28 1 file changed, 28 insertions(+) diff --git a/gcc/config/riscv/mips-p8700.md b/gcc/config/riscv/mips-p8700.md index 11d0b1ca793..ae0ea8dc896 100644 --- a/gcc/config/riscv/mips-p8700.md +++ b/gcc/config/riscv/mips-p8700.md @@ -3

[PATCH v2 0/1]RISC-V :The following changes enable P8700 MIPS processor for RISC-V.

>>Every type listed in that attribute must have a mapping to a function unit in >>your scheduler model Thank you Jeff and added the dummies reservation for the leftout attributes and tested with dejagnu riscv.exp. Thank you again for reference ~U

RE: [EXTERNAL]RE: [PATCH ]RISCV :Added MIPS P8700 Subtarget

Sure @Palmer Dabbelt ,sent in a different thread email with updated patch. Thank you ~U -Original Message- From: Palmer Dabbelt Sent: 08 May 2025 23:38 To: Umesh Kalappa Cc: jeffreya...@gmail.com; gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; jesse.hu...@sifive.com; Andrew

[PATCH v1 0/1]RISC-V :The following changes enable P8700 MIPS processor for RISC-V.

--- gcc/config/riscv/mips-p8700.md | 139 +++ gcc/config/riscv/riscv-cores.def | 5 ++ gcc/config/riscv/riscv-opts.h| 3 +- gcc/config/riscv/riscv.cc| 22 + gcc/config/riscv/riscv.md| 3 +- 5 files changed, 170 insertions(+), 2 deletions

RE: [PATCH ]RISCV :Added MIPS P8700 Subtarget

Hi All , We have couple of patch series that enables the P8700 tune for RISCV core to upstream for GCC mainline. It will be good to hear from you guys on the patch feedback Thank you in advance ~U -Original Message- From: Umesh Kalappa Sent: 03 May 2025 11:27 To: Jeff Law ; gcc

Ignore me ..

Re: [PATCH]RISCV :Added MIPS P8700 Subtarget

Hi @Jeff Law and @pal...@dabbelt.com , Please do needful by reviewing the below changes and helps us to upstream the same . Thank you ~U -Original Message- From: Umesh Kalappa Sent: 29 April 2025 16:16 To: Umesh Kalappa ; Jeff Law ; gcc-patches@gcc.gnu.org Cc: kito.ch...@sifive.com

RE: [EXTERNAL]Re: [PATCH]RISCV :Added MIPS P8700 Subtarget

/* int_mul */ + {COSTS_N_INSNS (8), COSTS_N_INSNS (8)}, /* int_div */ + 4,/* issue_rate */ + 8,/* branch_cost */ + 4, /* memory_cost */ + 8,/* fmv_cost */ + true, /* slow_unaligned_access */ + false,/* vector_unaligned_access *

RE: [EXTERNAL]Re: [PATCH]RISCV :Added MIPS P8700 Subtarget

s more closely. If you have questions >> about how the compiler uses them to make decisions, just ask Sure ,and lets us tune the same and reach out here for future questions . ~U -Original Message- From: Jeff Law Sent: 18 April 2025 22:42 To: Umesh Kalappa ; gcc-patches@gcc.gnu.

[PATCH]RISCV :Added MIPS P8700 Subtarget

This is the first patch from the two-patch series, where configured gcc for P8700 micro architecture in the first patch and Tested with dejagnu riscv.exp tests for --mtune=mips-p8700. P8700 is a high-performance processor from MIPS by extending RISCV. The following changes enable P8700 proces

RE: [EXTERNAL]Re: [PATCH] RISCV :Added MIPS P8700 Subtarget.

Thank you @Kito Cheng for early suggestions ,we will break down the patch like suggested and address the below comments . ~U -Original Message- From: Kito Cheng Sent: 11 April 2025 12:37 To: Umesh Kalappa Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; Jesse Huang ; pal

[PATCH] RISCV :Added MIPS P8700 Subtarget.

/riscv/mips-insn.md create mode 100644 gcc/config/riscv/mips-p8700.md create mode 100644 gcc/testsuite/gcc.target/riscv/mipscondmov.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1326c67563a..d2642390b2a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,24 @@ +2025-04-09 Umesh Kalappa

Re: [Patch]Bug 89057 - [8/9/10 Regression] AArch64 ld3 st4 less optimized

>>Before getting started with reviewing the patch , the first question is whether you have a copyright assignment on file or does your employer have one on record with the FSF ? Ramana, We asked for copyright assignment form ,with details asked by copyright-cl...@fsf.org(craig) @ ass...@gnu.org.

Re: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84762

Thank you Segher, will work on your suggestions. Umesh On Tue, Dec 11, 2018, 19:23 Segher Boessenkool Hi Umesh, > > On Tue, Dec 11, 2018 at 05:30:48PM +0530, Umesh Kalappa wrote: > > Please find the attached patch for the subjected issue . > > > > Do please let m

Re: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84762

Thank you Jakub for the information. Will make a note of it. Umesh On Tue, Dec 11, 2018, 17:58 Jakub Jelinek On Tue, Dec 11, 2018 at 05:30:48PM +0530, Umesh Kalappa wrote: > > Hi All, > > > > Please find the attached patch for the subjected issue . > > > > Do pl

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84762

Hi All, Please find the attached patch for the subjected issue . Do please let me know your thoughts and comments on the same . Thank you ~Umesh pr84762.patch Description: Binary data

Re: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=54589

you ~Umesh On Fri, Nov 23, 2018 at 3:56 PM Umesh Kalappa wrote: > > Hi Richard, > > for the subjected issue , we found few suggestions to handle the issue like > > 1. be more conservative(target specific) and defining the peephole in > the md file to handle the patterns like a

Re: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87626

Hi Jakub and All, We don't have the commit access ,can someone please commit for us ? ~Umesh On Wed, Nov 21, 2018, 18:37 Jakub Jelinek On Wed, Nov 21, 2018 at 06:06:41PM +0530, Umesh Kalappa wrote: > > Thank you for the inputs and please find the attachment for the update > p

Re: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87626

Thank you for the inputs and please find the attachment for the update patch. Do please let us know your comments on the same ~Umesh On Tue, Nov 20, 2018 at 3:03 PM Jakub Jelinek wrote: > > On Mon, Nov 19, 2018 at 04:08:29PM +0530, Lokesh Janghel wrote: > diff --git a/gcc/ChangeLog b/gcc/ChangeL

Re: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87626

; On Fri, Nov 16, 2018 at 4:57 PM Jakub Jelinek wrote: >> >> On Fri, Nov 16, 2018 at 04:21:25PM +0530, Umesh Kalappa wrote: >> > My bad , >> > attached the same now . >> >> +2018-11-15 Lokesh Janghel >> >> Two spaces before < instead of

Re: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87626

My bad , attached the same now . ~Umesh On Fri, Nov 16, 2018 at 2:38 PM Richard Biener wrote: > > On Fri, Nov 16, 2018 at 9:07 AM Umesh Kalappa > wrote: > > > > Thank you Richard, > > > > Made the required changes ,ok to commit ? > > Can you attach th

Re: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87626

Thank you Richard, Made the required changes ,ok to commit ? Thank you ~Umesh On Thu, Nov 15, 2018 at 4:02 PM Richard Biener wrote: > > On Thu, Nov 15, 2018 at 10:02 AM Umesh Kalappa > wrote: > > > > Hi All, > > > > The attached patch (pr85667.patch) fixes th

Re: Bug 52869 - [DR 1207] "this" not being allowed in noexcept clauses

Thank you Marek,Appreciate your valuable feedback on the patch . Attached the latest ,please do let us know your thoughts. ~Umesh On Thu, Nov 15, 2018 at 9:26 PM Marek Polacek wrote: > > On Thu, Nov 15, 2018 at 02:26:24PM +0530, Umesh Kalappa wrote: > > Thank you Marek fo

Re: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85667

Edited the subjected for the proper PR no. ~Umesh On Thu, Nov 15, 2018 at 2:32 PM Umesh Kalappa wrote: > > Hi All, > > The attached patch (pr85667.patch) fixes the subjected issue . > we tested on x86_64(linux and windows both) and no regress found . > > ok to commit ? > > Thank you > ~Umesh

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87626

Hi All, The attached patch (pr85667.patch) fixes the subjected issue . we tested on x86_64(linux and windows both) and no regress found . ok to commit ? Thank you ~Umesh pr85667.patch Description: Binary data

Re: Bug 52869 - [DR 1207] "this" not being allowed in noexcept clauses

> > On Wed, Nov 14, 2018 at 09:55:39PM +0530, Umesh Kalappa wrote: > > My bad Marek and thank you for pointing that out. > > > > Please find the attached correct one (pr52869.patch) . > > Index: gcc/cp/ChangeLog > ===

Re: Bug 52869 - [DR 1207] "this" not being allowed in noexcept clauses

My bad Marek and thank you for pointing that out. Please find the attached correct one (pr52869.patch) . ~Umesh pr52869.patch Description: Binary data

Re: Bug 52869 - [DR 1207] "this" not being allowed in noexcept clauses

>>We are runing the make check-gcc(x86_64) and will let know for any >>regressions . No regress found . ~Umesh On Wed, Nov 14, 2018 at 5:18 PM Umesh Kalappa wrote: > > Thank you Jason and Marek for the suggestions . > > Attached patch(pr86512.patch) along the Changel

Re: Bug 52869 - [DR 1207] "this" not being allowed in noexcept clauses

t know for any regressions . Meanwhile ,Please let us know your thoughts on the patch. Thank you ~Umesh On Wed, Nov 14, 2018 at 2:55 AM Jason Merrill wrote: > > On Tue, Nov 13, 2018 at 10:40 AM Marek Polacek wrote: > > On Tue, Nov 13, 2018 at 11:49:55AM +0530, Umesh Kalap

Bug 52869 - [DR 1207] "this" not being allowed in noexcept clauses

Hi All, the following patch fix the subjected issue Index: gcc/cp/parser.c === --- gcc/cp/parser.c (revision 266026) +++ gcc/cp/parser.c (working copy) @@ -24615,6 +24615,8 @@ { tree expr; cp_lexer_consume_

Re: [Patch-86512]: Subnormal float support in armv7(with -msoft-float) for intrinsics

Hi, Any more suggestions or comments on the patch ? Thank you ~Umesh On Tue, Jul 24, 2018, 2:08 PM Umesh Kalappa wrote: > Thank you All for the suggestions and we tried runing the GCC > testsuite and found that no regression with the fix and also ran the > our regressions

Re: [Patch-86512]: Subnormal float support in armv7(with -msoft-float) for intrinsics

Umesh Kalappa + + PR libgcc/86512 + * config/arm/ieee754-df.S :Don't normalise the denormal result. + * config/arm/ieee754-sf.S:Likewise. + + +++ gcc/testsuite/ChangeLog (working copy) @@ -1,3 +1,8 @@ +2018-07-18 Umesh Kalappa + + PR libgcc/86512 + * gcc.targe

Re: [Patch-86512]: Subnormal float support in armv7(with -msoft-float) for intrinsics

> R. > > On 23/07/18 08:46, Umesh Kalappa wrote: >> Thank you Wilco for the inputs and we agree that the fix break down >> for the case. >> >> Meanwhile ,attached patch will take care the inputs and we are testing >> the patch vigorously ,would you r

Re: [Patch-86512]: Subnormal float support in armv7(with -msoft-float) for intrinsics

Dijkstra wrote: > Umesh Kalappa wrote: > >> We tried some of the normalisation numbers and the fix works and please >> could you help us with the input ,where if you see that fix breaks down. > > Well try any set of inputs which require normalisation. You'll find the

Re: [Patch-86512]: Subnormal float support in armv7(with -msoft-float) for intrinsics

Thank you all for your comments . Wilco, We tried some of the normalisation numbers and the fix works and please could you help us with the input ,where if you see that fix breaks down. Thank you again ~Umesh On Fri, Jul 20, 2018, 7:07 PM Wilco Dijkstra wrote: > Hi Umesh, > > Looking at your p

Re: [Patch-86512]: Subnormal float support in armv7(with -msoft-float) for intrinsics

Reminder !!! ~Umesh On Wed, Jul 18, 2018 at 6:01 PM, Umesh Kalappa wrote: > Hi Nagy/Ramana, > > Please help us to review the attached patch and do let me know your comments . > > No regress in the gcc.target suite for arm target. > > Thank you > ~Umesh > > O

[Patch-86512]: Subnormal float support in armv7(with -msoft-float) for intrinsics

Hi Nagy/Ramana, Please help us to review the attached patch and do let me know your comments . No regress in the gcc.target suite for arm target. Thank you ~Umesh On Tue, Jul 17, 2018 at 4:01 PM, Umesh Kalappa wrote: > Will do, thanks. > Thanks > > On Tue, Jul 17, 2018, 3: