Hi all, Sorry for the noise ,looks like patch was truncated and will be sending a new email with proper patch for the same.
Thank you and again my apologies for the noise. ~U On Tue, May 27, 2025 at 3:41 PM Umesh Kalappa <ukalappa.m...@gmail.com> wrote: > The P8700 is a high-performance processor from MIPS by extending RISCV with > the MIPS custom instruction and the following changes are added to enable > the conditional move support from mips. > > No regression found for "runtest --tool gcc > --target_board='riscv-sim/-mabi=lp64d/-mcmodel=medlow/-mtune=mips-p8700/-O2 > ' riscv.exp" > > gcc/ChangeLog: > > *common/config/riscv/riscv-common.cc (riscv_ext_version_table) : > Added MIPS specific insns for P8700. > *config/riscv/riscv-cores.def(RISCV_CORE):Updated the march for > mips-p8700 tune. > *config/riscv/riscv-ext-mips.def(DEFINE_RISCV_EXT): > New file added the mips conditional mov extension. > *config/riscv/riscv-ext.def: Likewise. > *config/riscv/t-riscv:Generates riscv-ext.opt > *config/riscv/riscv-ext.opt: Generated file. > *config/riscv/riscv.cc(riscv_expand_conditional_move):Updated for > mips cmov. > *config/riscv/riscv.md(mov<mode>cc):updated expand for MIPS CCMOV. > *config/riscv/mips-insn.md:New file for mips-p8700 ccmov insn. > *testsuite/gcc.target/riscv/mipscondmov.c:New file to test the > ccmov insn. > *gcc/doc/riscv-ext.texi:Updated for mips cmov. > --- > gcc/config/riscv/mips-insn.md | 37 ++++++++++++++++++++ > gcc/config/riscv/riscv-ext-mips.def | 35 ++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/mipscondmov.c | 30 ++++++++++++++++ > 3 files changed, 102 insertions(+) > create mode 100644 gcc/config/riscv/mips-insn.md > create mode 100644 gcc/config/riscv/riscv-ext-mips.def > create mode 100644 gcc/testsuite/gcc.target/riscv/mipscondmov.c > > diff --git a/gcc/config/riscv/mips-insn.md b/gcc/config/riscv/mips-insn.md > new file mode 100644 > index 00000000000..ee106c4221e > --- /dev/null > +++ b/gcc/config/riscv/mips-insn.md > @@ -0,0 +1,37 @@ > +;; Machine description for MIPS custom instructioins. > +;; Copyright (C) 2025 Free Software Foundation, Inc. > + > +;; This file is part of GCC. > + > +;; GCC is free software; you can redistribute it and/or modify > +;; it under the terms of the GNU General Public License as published by > +;; the Free Software Foundation; either version 3, or (at your option) > +;; any later version. > + > +;; GCC is distributed in the hope that it will be useful, > +;; but WITHOUT ANY WARRANTY; without even the implied warranty of > +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +;; GNU General Public License for more details. > + > +;; You should have received a copy of the GNU General Public License > +;; along with GCC; see the file COPYING3. If not see > +;; <http://www.gnu.org/licenses/>. > + > +(define_insn "*mov<GPR:mode><X:mode>cc_bitmanip" > + [(set (match_operand:GPR 0 "register_operand" "=r") > + (if_then_else:GPR > + (match_operator 5 "equality_operator" > + [(match_operand:X 1 "register_operand" "r") > + (match_operand:X 2 "const_0_operand" "J")]) > + (match_operand:GPR 3 "reg_or_0_operand" "rJ") > + (match_operand:GPR 4 "reg_or_0_operand" "rJ")))] > + "TARGET_XMIPSCMOV" > +{ > + enum rtx_code code = GET_CODE (operands[5]); > + if (code == NE) > + return "mips.ccmov\t%0,%1,%z3,%z4"; > + else > + return "mips.ccmov\t%0,%1,%z4,%z3"; > +} > + [(set_attr "type" "condmove") > + (set_attr "mode" "<GPR:MODE>")]) > diff --git a/gcc/config/riscv/riscv-ext-mips.def > b/gcc/config/riscv/riscv-ext-mips.def > new file mode 100644 > index 00000000000..86492223cb3 > --- /dev/null > +++ b/gcc/config/riscv/riscv-ext-mips.def > @@ -0,0 +1,35 @@ > +/* MIPS extension definition file for RISC-V. > + Copyright (C) 2025 Free Software Foundation, Inc. > + > +This file is part of GCC. > + > +GCC is free software; you can redistribute it and/or modify > +it under the terms of the GNU General Public License as published by > +the Free Software Foundation; either version 3, or (at your option) > +any later version. > + > +GCC is distributed in the hope that it will be useful, > +but WITHOUT ANY WARRANTY; without even the implied warranty of > +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +GNU General Public License for more details. > + > +You should have received a copy of the GNU General Public License > +along with GCC; see the file COPYING3. If not see > +<http://www.gnu.org/licenses/>. > + > +Please run `make riscv-regen` in build folder to make sure updated > anything. > + > +Format of DEFINE_RISCV_EXT, please refer to riscv-ext.def. */ > + > +DEFINE_RISCV_EXT( > + /* NAME */ xmipscmov, > + /* UPPERCAE_NAME */ XMIPSCMOV, > + /* FULL_NAME */ "Mips conditional move extension", > + /* DESC */ "", > + /* URL */ , > + /* DEP_EXTS */ ({}), > + /* SUPPORTED_VERSIONS */ ({{1, 0}}), > + /* FLAG_GROUP */ xmips, > + /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED, > + /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED, > + /* EXTRA_EXTENSION_FLAGS */ 0) > diff --git a/gcc/testsuite/gcc.target/riscv/mipscondmov.c > b/gcc/testsuite/gcc.target/riscv/mipscondmov.c > new file mode 100644 > index 00000000000..144a6b718ef > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/mipscondmov.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64imafd_xmipscmov -mabi=lp64d" { target { rv64 > } } } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ > + > +#define MYTEST(name, mytype) \ > +mytype test1_ ## name (mytype a, mytype b, mytype c, mytype d) { return > (a == b) ? c : d; } \ > +mytype test2_ ## name (mytype a, mytype b, mytype c, mytype d) { return > (a != b) ? c : d; } \ > +mytype test3_ ## name (mytype a, mytype b, mytype c, mytype d) { return > (a > b) ? c : d; } \ > +mytype test4_ ## name (mytype a, mytype b, mytype c, mytype d) { return > (a >= b) ? c : d; } \ > +mytype test5_ ## name (mytype a, mytype b, mytype c, mytype d) { return > (a < b) ? c : d; } \ > +mytype test6_ ## name (mytype a, mytype b, mytype c, mytype d) { return > (a <= b) ? c : d; } \ > +mytype test7_ ## name (mytype a, mytype b, mytype c, mytype d) { return > (a == 1) ? c : d; } \ > +mytype test8_ ## name (mytype a, mytype b, mytype c, mytype d) { return > (a != 1) ? c : d; } \ > +mytype test9_ ## name (mytype a, mytype b, mytype c, mytype d) { return > (a > 1) ? c : d; } \ > +mytype test10_ ## name (mytype a, mytype b, mytype c, mytype d) { return > (a >= 1) ? c : d; } \ > +mytype test11_ ## name (mytype a, mytype b, mytype c, mytype d) { return > (a < 1) ? c : d; } \ > +mytype test12_ ## name (mytype a, mytype b, mytype c, mytype d) { return > (a <= 1) ? c : d; } > + > +MYTEST(1, long long); > +MYTEST(2, unsigned long long); > +MYTEST(3, long); > +MYTEST(4, unsigned long); > +MYTEST(5, int); > +MYTEST(6, unsigned int); > +MYTEST(7, short); > +MYTEST(8, unsigned short); > +MYTEST(9, signed char); > +MYTEST(10, unsigned char); > + > +/* { dg-final { scan-assembler-times "mips.ccmov" 120 } } */ > > base-commit: a91679a3d9f7cbc079880f201fd8292c1d54baa7 > -- > 2.43.0 > >
