Thank you @Kito Cheng for early suggestions ,we will break down the patch like suggested and address the below comments .
~U -----Original Message----- From: Kito Cheng <kito.ch...@gmail.com> Sent: 11 April 2025 12:37 To: Umesh Kalappa <ukala...@mips.com> Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; Jesse Huang <jesse.hu...@sifive.com>; pal...@dabbelt.com; and...@sifive.com; j...@sifive.com Subject: [EXTERNAL]Re: [PATCH] RISCV :Added MIPS P8700 Subtarget. [You don't often get email from kito.ch...@gmail.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ] Could you break this patch into two pieces: 1) Add new extensions. 2) Add new core (for -mcpu), pipeline model and cost model > diff --git a/gcc/ChangeLog b/gcc/ChangeLog index > 1326c67563a..d2642390b2a 100644 > --- a/gcc/ChangeLog > +++ b/gcc/ChangeLog > @@ -1,3 +1,24 @@ > +2025-04-09 Umesh Kalappa <ukalappa.m...@gmail.com> > + > + P8700 is a high-performance processor from MIPS by extending RISCV > + with the MIPS custom instructions. > + The following changes enable P8700 processor for RISCV and > + added MIPS specific insns. GCC does not require editing the changelog directly, put that on the git commit log instead, and then there is a script that will update that automatically. > index b34409adf39..c8467016c87 100644 > --- a/gcc/common/config/riscv/riscv-common.cc > +++ b/gcc/common/config/riscv/riscv-common.cc > @@ -442,6 +442,11 @@ static const struct riscv_ext_version > riscv_ext_version_table[] = > {"xsfvqmaccdod", ISA_SPEC_CLASS_NONE, 1, 0}, > {"xsfvfnrclipxfqf", ISA_SPEC_CLASS_NONE, 1, 0}, > > + {"xmipscbop", ISA_SPEC_CLASS_NONE, 1, 0}, {"xmipscmov", > + ISA_SPEC_CLASS_NONE, 1, 0}, {"xmipsexectl", ISA_SPEC_CLASS_NONE, 1, > + 0}, {"xmipslsp", ISA_SPEC_CLASS_NONE, 1, 0}, one extension one line > diff --git a/gcc/config/riscv/mips-insn.md > b/gcc/config/riscv/mips-insn.md new file mode 100644 index > 00000000000..0c92a9d9e94 > --- /dev/null > +++ b/gcc/config/riscv/mips-insn.md > @@ -0,0 +1,37 @@ > +;; Machine description for MIPS custom instructioins. s/instructioins/instructions/ > +;; Copyright (C) 2021-2025 Free Software Foundation, Inc. 2025 rather than 2021-2025 > + > +;; This file is part of GCC. > + > +;; GCC is free software; you can redistribute it and/or modify ;; it > +under the terms of the GNU General Public License as published by ;; > +the Free Software Foundation; either version 3, or (at your option) > +;; any later version. > + > +;; GCC is distributed in the hope that it will be useful, ;; but > +WITHOUT ANY WARRANTY; without even the implied warranty of ;; > +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ;; GNU > +General Public License for more details. > + > +;; You should have received a copy of the GNU General Public License > +;; along with GCC; see the file COPYING3. If not see ;; > +<http://www.gnu.org/licenses/>. > + > +(define_insn "*mov<GPR:mode><X:mode>cc_bitmanip" ^^ the pattern name starting with * does not really matter to GCC itself, but it is useful when debugging, so maybe rename that to "*mov<GPR:mode><X:mode>cc_xmipscomv"? > diff --git a/gcc/config/riscv/mips-p8700.md > b/gcc/config/riscv/mips-p8700.md new file mode 100644 index > 00000000000..7cf50381cab > --- /dev/null > +++ b/gcc/config/riscv/mips-p8700.md > @@ -0,0 +1,139 @@ > +;; DFA-based pipeline description for MIPS P8700. > +;; > +;; Copyright (C) 2018-2025 Free Software Foundation, Inc. 2025 rather than 2021-2025 > diff --git a/gcc/config/riscv/riscv-cores.def > b/gcc/config/riscv/riscv-cores.def > index 2918496bcd0..73df04148fa 100644 > --- a/gcc/config/riscv/riscv-cores.def > +++ b/gcc/config/riscv/riscv-cores.def > @@ -44,6 +44,7 @@ RISCV_TUNE("thead-c906", generic, > thead_c906_tune_info) RISCV_TUNE("xiangshan-nanhu", xiangshan, > xiangshan_nanhu_tune_info) RISCV_TUNE("generic-ooo", generic_ooo, > generic_ooo_tune_info) RISCV_TUNE("size", generic, > optimize_size_tune_info) > +RISCV_TUNE("mips-p8700", mips_p8700, mips_p8700_tune_info) > > #undef RISCV_TUNE > > diff --git a/gcc/config/riscv/riscv-opts.h > b/gcc/config/riscv/riscv-opts.h index 26fe228e0f8..3ae284b0d95 100644 > --- a/gcc/config/riscv/riscv-opts.h > +++ b/gcc/config/riscv/riscv-opts.h > @@ -58,7 +58,8 @@ enum riscv_microarchitecture_type { > sifive_p400, > sifive_p600, > xiangshan, > - generic_ooo > + generic_ooo, > + mips_p8700, > }; > extern enum riscv_microarchitecture_type riscv_microarchitecture; > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 38f3ae7cd84..a8325ece2e9 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -642,6 +642,72 @@ static const struct riscv_tune_param > optimize_size_tune_info = { > NULL, /* loop_align */ > }; > > +/* Costs to use when optimizing for MIPS P8700. */ static const > +struct riscv_tune_param mips_p8700_tune_info = { ^^^ Why does this repeat 3 times? > static bool riscv_avoid_shrink_wrapping_separate (); static tree > riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool *); > static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool > *); @@ -3946,7 +4012,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, > int outer_code, int opno ATTRIBUTE_UN The diff seems corrupt?
