P8700 is a high-performance processor from MIPS by extending RISCV with the MIPS custom instructions.
Tested with dejagnu riscv.exp tests for --mtune=mips-p8700. Please refer @ https://mips.com/products/hardware/p8700/ --- gcc/ChangeLog | 21 +++ gcc/common/config/riscv/riscv-common.cc | 10 ++ gcc/config/riscv/mips-insn.md | 37 +++++ gcc/config/riscv/mips-p8700.md | 139 +++++++++++++++++++ gcc/config/riscv/riscv-cores.def | 1 + gcc/config/riscv/riscv-opts.h | 3 +- gcc/config/riscv/riscv.cc | 92 +++++++++++- gcc/config/riscv/riscv.md | 16 ++- gcc/config/riscv/riscv.opt | 11 ++ gcc/testsuite/gcc.target/riscv/mipscondmov.c | 30 ++++ 10 files changed, 355 insertions(+), 5 deletions(-) create mode 100644 gcc/config/riscv/mips-insn.md create mode 100644 gcc/config/riscv/mips-p8700.md create mode 100644 gcc/testsuite/gcc.target/riscv/mipscondmov.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1326c67563a..d2642390b2a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,24 @@ +2025-04-09 Umesh Kalappa <ukalappa.m...@gmail.com> + + P8700 is a high-performance processor from MIPS by extending RISCV + with the MIPS custom instructions. + The following changes enable P8700 processor for RISCV and + added MIPS specific insns. + + * common/config/riscv/riscv-common.cc (riscv_ext_version_table) : + Added MIPS specific insns. + * config/riscv/riscv-cores.def(RISCV_TUNE):Added mips-p8700 tune. + * config/riscv/riscv-opts.h(riscv_microarchitecture_type): Likewise + * config/riscv/riscv.c(riscv_expand_conditional_move): + Added insns costs p8700 tune and handle the ccmov expand. + * config/riscv/riscv.md(tune and mov<mode>cc): + Added p8700 tune for insn attribute and updated expand for MIPS CCMOV. + * config/riscv/riscv.opt:Added riscv_mips_subext for MIPS ext insns. + * config/riscv/mips-insn.md:New file for mips-p8700 ext insns. + * config/riscv/mips-p8700.md:New File for mips-p8700 pipeline + description. + * testsuite/gcc.target/riscv/mipscondmov.c :New file to test ccmov insn. + 2025-04-10 Iain Sandoe <i...@sandoe.co.uk> * config/darwin.h (LINK_SPEC): Add support for diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index b34409adf39..c8467016c87 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -442,6 +442,11 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"xsfvqmaccdod", ISA_SPEC_CLASS_NONE, 1, 0}, {"xsfvfnrclipxfqf", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xmipscbop", ISA_SPEC_CLASS_NONE, 1, 0}, {"xmipscmov", + ISA_SPEC_CLASS_NONE, 1, 0}, {"xmipsexectl", ISA_SPEC_CLASS_NONE, 1, + 0}, {"xmipslsp", ISA_SPEC_CLASS_NONE, 1, 0}, + /* Terminate the list. */ {NULL, ISA_SPEC_CLASS_NONE, 0, 0} }; @@ -1778,6 +1783,11 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = RISCV_EXT_FLAG_ENTRY ("xsfvqmaccdod", x_riscv_sifive_subext, MASK_XSFVQMACCDOD), RISCV_EXT_FLAG_ENTRY ("xsfvfnrclipxfqf", x_riscv_sifive_subext, MASK_XSFVFNRCLIPXFQF), + RISCV_EXT_FLAG_ENTRY ("xmipscbop", x_riscv_mips_subext, MASK_XMIPSCBOP), + RISCV_EXT_FLAG_ENTRY ("xmipscmov", x_riscv_mips_subext, MASK_XMIPSCMOV), + RISCV_EXT_FLAG_ENTRY ("xmipsexectl", x_riscv_mips_subext, MASK_XMIPSEXECTL), + RISCV_EXT_FLAG_ENTRY ("xmipslsp", x_riscv_mips_subext, MASK_XMIPSLSP), + {NULL, NULL, NULL, 0} }; diff --git a/gcc/config/riscv/mips-insn.md b/gcc/config/riscv/mips-insn.md new file mode 100644 index 00000000000..0c92a9d9e94 --- /dev/null +++ b/gcc/config/riscv/mips-insn.md @@ -0,0 +1,37 @@ +;; Machine description for MIPS custom instructioins. +;; Copyright (C) 2021-2025 Free Software Foundation, Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify ;; it +under the terms of the GNU General Public License as published by ;; +the Free Software Foundation; either version 3, or (at your option) ;; +any later version. + +;; GCC is distributed in the hope that it will be useful, ;; but +WITHOUT ANY WARRANTY; without even the implied warranty of ;; +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ;; GNU +General Public License for more details. + +;; You should have received a copy of the GNU General Public License ;; +along with GCC; see the file COPYING3. If not see ;; +<http://www.gnu.org/licenses/>. + +(define_insn "*mov<GPR:mode><X:mode>cc_bitmanip" + [(set (match_operand:GPR 0 "register_operand" "=r") + (if_then_else:GPR + (match_operator 5 "equality_operator" + [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "const_0_operand" "J")]) + (match_operand:GPR 3 "reg_or_0_operand" "rJ") + (match_operand:GPR 4 "reg_or_0_operand" "rJ")))] + "TARGET_XMIPSCMOV" +{ + enum rtx_code code = GET_CODE (operands[5]); + if (code == NE) + return "mips.ccmov\t%0,%1,%z3,%z4"; + else + return "mips.ccmov\t%0,%1,%z4,%z3"; } + [(set_attr "type" "arith") + (set_attr "mode" "<GPR:MODE>")]) diff --git a/gcc/config/riscv/mips-p8700.md b/gcc/config/riscv/mips-p8700.md new file mode 100644 index 00000000000..7cf50381cab --- /dev/null +++ b/gcc/config/riscv/mips-p8700.md @@ -0,0 +1,139 @@ +;; DFA-based pipeline description for MIPS P8700. +;; +;; Copyright (C) 2018-2025 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it ;; +under the terms of the GNU General Public License as published ;; by +the Free Software Foundation; either version 3, or (at your ;; option) +any later version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ;; +License for more details. + +;; You should have received a copy of the GNU General Public License ;; +along with GCC; see the file COPYING3. If not see ;; +<http://www.gnu.org/licenses/>. + +(define_automaton "mips_p8700_agen_alq_pipe, mips_p8700_mdu_pipe, +mips_p8700_fpu_pipe") + +;; The address generation queue (AGQ) has AL2, CTISTD and LDSTA pipes +(define_cpu_unit "mips_p8700_agq, mips_p8700_al2, mips_p8700_ctistd, mips_p8700_lsu" + "mips_p8700_agen_alq_pipe") + +(define_cpu_unit "mips_p8700_gpmul, mips_p8700_gpdiv" +"mips_p8700_mdu_pipe") + +;; The arithmetic-logic-unit queue (ALQ) has ALU pipe (define_cpu_unit +"mips_p8700_alq, mips_p8700_alu" "mips_p8700_agen_alq_pipe") + +;; The floating-point-unit queue (FPQ) has short and long pipes +(define_cpu_unit "mips_p8700_fpu_short, mips_p8700_fpu_long" +"mips_p8700_fpu_pipe") + +;; Long FPU pipeline. +(define_cpu_unit "mips_p8700_fpu_apu" "mips_p8700_fpu_pipe") + +(define_reservation "mips_p8700_agq_al2" "mips_p8700_agq, +mips_p8700_al2") (define_reservation "mips_p8700_agq_ctistd" +"mips_p8700_agq, mips_p8700_ctistd") (define_reservation +"mips_p8700_agq_lsu" "mips_p8700_agq, mips_p8700_lsu") +(define_reservation "mips_p8700_alq_alu" "mips_p8700_alq, +mips_p8700_alu") + +;; +;; FPU pipe +;; + +(define_insn_reservation "mips_p8700_fpu_fadd" 4 + (and (eq_attr "tune" "mips_p8700") + (eq_attr "type" "fadd")) + "mips_p8700_fpu_long, mips_p8700_fpu_apu") + +(define_insn_reservation "mips_p8700_fpu_fabs" 2 + (and (eq_attr "tune" "mips_p8700") + (eq_attr "type" "fcmp,fmove")) + "mips_p8700_fpu_short, mips_p8700_fpu_apu") + +(define_insn_reservation "mips_p8700_fpu_fload" 8 + (and (eq_attr "tune" "mips_p8700") + (eq_attr "type" "fpload")) + "mips_p8700_agq_lsu") + +(define_insn_reservation "mips_p8700_fpu_fstore" 1 + (and (eq_attr "tune" "mips_p8700") + (eq_attr "type" "fpstore")) + "mips_p8700_agq_lsu") + +(define_insn_reservation "mips_p8700_fpu_fmadd" 8 + (and (eq_attr "tune" "mips_p8700") + (eq_attr "type" "fmadd")) + "mips_p8700_fpu_long, mips_p8700_fpu_apu") + +(define_insn_reservation "mips_p8700_fpu_fmul" 5 + (and (eq_attr "tune" "mips_p8700") + (eq_attr "type" "fmul")) + "mips_p8700_fpu_long, mips_p8700_fpu_apu") + +(define_insn_reservation "mips_p8700_fpu_div" 17 + (and (eq_attr "tune" "mips_p8700") + (eq_attr "type" "fdiv,fsqrt")) + "mips_p8700_fpu_long, mips_p8700_fpu_apu*17") + +(define_insn_reservation "mips_p8700_fpu_fcvt" 4 + (and (eq_attr "tune" "mips_p8700") + (eq_attr "type" "fcvt,fcvt_i2f,fcvt_f2i")) + "mips_p8700_fpu_long, mips_p8700_fpu_apu") + +(define_insn_reservation "mips_p8700_fpu_fmtc" 7 + (and (eq_attr "tune" "mips_p8700") + (eq_attr "type" "mtc")) + "mips_p8700_agq_lsu") + +(define_insn_reservation "mips_p8700_fpu_fmfc" 7 + (and (eq_attr "tune" "mips_p8700") + (eq_attr "type" "mfc")) + "mips_p8700_agq_lsu") + +;; +;; Integer pipe +;; + +(define_insn_reservation "mips_p8700_int_load" 4 + (and (eq_attr "tune" "mips_p8700") + (eq_attr "type" "load")) + "mips_p8700_agq_lsu") + +(define_insn_reservation "mips_p8700_int_store" 3 + (and (eq_attr "tune" "mips_p8700") + (eq_attr "type" "store")) + "mips_p8700_agq_lsu") + +(define_insn_reservation "mips_p8700_int_arith_1" 1 + (and (eq_attr "tune" "mips_p8700") + (eq_attr "type" +"unknown,const,arith,shift,slt,multi,auipc,logical,move,bitmanip,min,ma +x,minu,maxu,clz,ctz,rotate,atomic,condmove,crypto,mvpair,zicond")) + "mips_p8700_alq_alu | mips_p8700_agq_al2") + +(define_insn_reservation "mips_p8700_int_nop" 0 + (and (eq_attr "tune" "mips_p8700") + (eq_attr "type" "nop")) + "mips_p8700_alq_alu | mips_p8700_agq_al2") + +(define_insn_reservation "mips_p8700_dsp_mult" 4 + (and (eq_attr "tune" "mips_p8700") + (eq_attr "type" "imul,cpop,clmul")) + "mips_p8700_gpmul") + +(define_insn_reservation "mips_p8700_int_div" 8 + (and (eq_attr "tune" "mips_p8700") + (eq_attr "type" "idiv")) + "mips_p8700_gpdiv*5") + +(define_insn_reservation "mips_p8700_int_branch" 1 + (and (eq_attr "tune" "mips_p8700") + (eq_attr "type" "branch,jump,ret,sfb_alu,trap")) + "mips_p8700_agq_ctistd") + +(define_insn_reservation "mips_p8700_int_call" 2 + (and (eq_attr "tune" "mips_p8700") + (eq_attr "type" "call,jalr")) + "mips_p8700_agq_ctistd") diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index 2918496bcd0..73df04148fa 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -44,6 +44,7 @@ RISCV_TUNE("thead-c906", generic, thead_c906_tune_info) RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info) RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info) RISCV_TUNE("size", generic, optimize_size_tune_info) +RISCV_TUNE("mips-p8700", mips_p8700, mips_p8700_tune_info) #undef RISCV_TUNE diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 26fe228e0f8..3ae284b0d95 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -58,7 +58,8 @@ enum riscv_microarchitecture_type { sifive_p400, sifive_p600, xiangshan, - generic_ooo + generic_ooo, + mips_p8700, }; extern enum riscv_microarchitecture_type riscv_microarchitecture; diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 38f3ae7cd84..a8325ece2e9 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -642,6 +642,72 @@ static const struct riscv_tune_param optimize_size_tune_info = { NULL, /* loop_align */ }; +/* Costs to use when optimizing for MIPS P8700. */ static const struct +riscv_tune_param mips_p8700_tune_info = { + {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* fp_add */ + {COSTS_N_INSNS (5), COSTS_N_INSNS (5)}, /* fp_mul */ + {COSTS_N_INSNS (17), COSTS_N_INSNS (17)}, /* fp_div */ + {COSTS_N_INSNS (5), COSTS_N_INSNS (5)}, /* int_mul */ + {COSTS_N_INSNS (8), COSTS_N_INSNS (8)}, /* int_div */ + 4, /* issue_rate */ + 8, /* branch_cost */ + 4, /* memory_cost */ + 8, /* fmv_cost */ + true, /* slow_unaligned_access */ + false, /* vector_unaligned_access */ + false, /* use_divmod_expansion */ + false, /* overlap_op_by_pieces */ + RISCV_FUSE_NOTHING, /* fusible_ops */ + NULL, /* vector cost */ + NULL, /* function_align */ + NULL, /* jump_align */ + NULL, /* loop_align */ +}; + +/* Costs to use when optimizing for MIPS P8700. */ static const struct +riscv_tune_param mips_p8700_tune_info = { + {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* fp_add */ + {COSTS_N_INSNS (5), COSTS_N_INSNS (5)}, /* fp_mul */ + {COSTS_N_INSNS (17), COSTS_N_INSNS (17)}, /* fp_div */ + {COSTS_N_INSNS (5), COSTS_N_INSNS (5)}, /* int_mul */ + {COSTS_N_INSNS (8), COSTS_N_INSNS (8)}, /* int_div */ + 4, /* issue_rate */ + 8, /* branch_cost */ + 4, /* memory_cost */ + 8, /* fmv_cost */ + true, /* slow_unaligned_access */ + false, /* vector_unaligned_access */ + false, /* use_divmod_expansion */ + false, /* overlap_op_by_pieces */ + RISCV_FUSE_NOTHING, /* fusible_ops */ + NULL, /* vector cost */ + NULL, /* function_align */ + NULL, /* jump_align */ + NULL, /* loop_align */ +}; + +/* Costs to use when optimizing for MIPS P8700. */ static const struct +riscv_tune_param mips_p8700_tune_info = { + {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* fp_add */ + {COSTS_N_INSNS (5), COSTS_N_INSNS (5)}, /* fp_mul */ + {COSTS_N_INSNS (17), COSTS_N_INSNS (17)}, /* fp_div */ + {COSTS_N_INSNS (5), COSTS_N_INSNS (5)}, /* int_mul */ + {COSTS_N_INSNS (8), COSTS_N_INSNS (8)}, /* int_div */ + 4, /* issue_rate */ + 8, /* branch_cost */ + 4, /* memory_cost */ + 8, /* fmv_cost */ + true, /* slow_unaligned_access */ + false, /* vector_unaligned_access */ + false, /* use_divmod_expansion */ + false, /* overlap_op_by_pieces */ + RISCV_FUSE_NOTHING, /* fusible_ops */ + NULL, /* vector cost */ + NULL, /* function_align */ + NULL, /* jump_align */ + NULL, /* loop_align */ +}; + static bool riscv_avoid_shrink_wrapping_separate (); static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool *); static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *); @@ -3946,7 +4012,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN return false; case IF_THEN_ELSE: - if ((TARGET_SFB_ALU || TARGET_XTHEADCONDMOV) + if ((TARGET_SFB_ALU || TARGET_XTHEADCONDMOV || TARGET_XMIPSCMOV) && reg_or_0_operand (XEXP (x, 1), mode) && sfb_alu_operand (XEXP (x, 2), mode) && comparison_operator (XEXP (x, 0), VOIDmode)) @@ -5263,8 +5329,30 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt) rtx_code code = GET_CODE (op); rtx op0 = XEXP (op, 0); rtx op1 = XEXP (op, 1); + rtx target; - if (((TARGET_ZICOND_LIKE + if (TARGET_XMIPSCMOV && mode == word_mode && GET_MODE (op0) == word_mode) + { + if (code == EQ || code == NE) + { + op0 = riscv_zero_if_equal (op0, op1); + op1 = const0_rtx; + } + else + { + target = gen_reg_rtx (GET_MODE (op0)); + riscv_emit_int_order_test(code, 0, target, op0, op1); + op0 = target; + op1 = const0_rtx; + code = NE; + } + riscv_emit_int_compare (&code, &op0, &op1); + rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); + emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (GET_MODE (dest), + cond, cons, alt))); + return true; + } + else if (((TARGET_ZICOND_LIKE || (arith_operand (cons, mode) && arith_operand (alt, mode))) && (GET_MODE_CLASS (mode) == MODE_INT)) || TARGET_SFB_ALU || TARGET_XTHEADCONDMOV) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 26a247c2b96..b1ed347fd75 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -669,7 +669,7 @@ ;; Microarchitectures we know how to tune for. ;; Keep this in sync with enum riscv_microarchitecture. (define_attr "tune" - "generic,sifive_7,sifive_p400,sifive_p600,xiangshan,generic_ooo" + "generic,sifive_7,sifive_p400,sifive_p600,xiangshan,generic_ooo,mips_p8700" (const (symbol_ref "((enum attr_tune) riscv_microarchitecture)"))) ;; Describe a user's asm statement. @@ -3277,8 +3277,18 @@ (match_operand:GPR 2 "movcc_operand") (match_operand:GPR 3 "movcc_operand")))] "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV || TARGET_ZICOND_LIKE - || TARGET_MOVCC" + || TARGET_MOVCC || TARGET_XMIPSCMOV" { + if (TARGET_XMIPSCMOV) { + /* operands[2] must be register or 0. */ + if (!reg_or_0_operand (operands[2], GET_MODE (operands[2]))) + operands[2] = force_reg (<GPR:MODE>mode, operands[2]); + + /* operands[3] must be register or 0. */ + if (!reg_or_0_operand (operands[3], GET_MODE (operands[3]))) + operands[3] = force_reg (<GPR:MODE>mode, operands[3]); + } + if (riscv_expand_conditional_move (operands[0], operands[1], operands[2], operands[3])) DONE; @@ -4828,3 +4838,5 @@ (include "zc.md") (include "corev.md") (include "xiangshan.md") +(include "mips-p8700.md") +(include "mips-insn.md") diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 7515c8ea13d..19cf448e1eb 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -535,6 +535,17 @@ Mask(XSFVQMACCDOD) Var(riscv_sifive_subext) Mask(XSFVFNRCLIPXFQF) Var(riscv_sifive_subext) +TargetVariable +int riscv_mips_subext + +Mask(XMIPSCBOP) Var(riscv_mips_subext) + +Mask(XMIPSCMOV) Var(riscv_mips_subext) + +Mask(XMIPSEXECTL) Var(riscv_mips_subext) + +Mask(XMIPSLSP) Var(riscv_mips_subext) + TargetVariable int riscv_fmv_priority = 0 diff --git a/gcc/testsuite/gcc.target/riscv/mipscondmov.c b/gcc/testsuite/gcc.target/riscv/mipscondmov.c new file mode 100644 index 00000000000..144a6b718ef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mipscondmov.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64imafd_xmipscmov -mabi=lp64d" { target { +rv64 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +#define MYTEST(name, mytype) \ +mytype test1_ ## name (mytype a, mytype b, mytype c, mytype d) { return +(a == b) ? c : d; } \ mytype test2_ ## name (mytype a, mytype b, mytype +c, mytype d) { return (a != b) ? c : d; } \ mytype test3_ ## name +(mytype a, mytype b, mytype c, mytype d) { return (a > b) ? c : d; } \ +mytype test4_ ## name (mytype a, mytype b, mytype c, mytype d) { return +(a >= b) ? c : d; } \ mytype test5_ ## name (mytype a, mytype b, mytype +c, mytype d) { return (a < b) ? c : d; } \ mytype test6_ ## name +(mytype a, mytype b, mytype c, mytype d) { return (a <= b) ? c : d; } \ +mytype test7_ ## name (mytype a, mytype b, mytype c, mytype d) { return +(a == 1) ? c : d; } \ mytype test8_ ## name (mytype a, mytype b, mytype +c, mytype d) { return (a != 1) ? c : d; } \ mytype test9_ ## name +(mytype a, mytype b, mytype c, mytype d) { return (a > 1) ? c : d; } \ +mytype test10_ ## name (mytype a, mytype b, mytype c, mytype d) { +return (a >= 1) ? c : d; } \ mytype test11_ ## name (mytype a, mytype +b, mytype c, mytype d) { return (a < 1) ? c : d; } \ mytype test12_ ## +name (mytype a, mytype b, mytype c, mytype d) { return (a <= 1) ? c : +d; } + +MYTEST(1, long long); +MYTEST(2, unsigned long long); +MYTEST(3, long); +MYTEST(4, unsigned long); +MYTEST(5, int); +MYTEST(6, unsigned int); +MYTEST(7, short); +MYTEST(8, unsigned short); +MYTEST(9, signed char); +MYTEST(10, unsigned char); + +/* { dg-final { scan-assembler-times "mips.ccmov" 120 } } */ -- 2.43.0
