On Tue, Aug 27, 2024 at 7:17 PM Richard Sandiford
wrote:
>
> The documentation of ASM_INPUT_P implied that the flag has no
> effect on ASM_EXPRs that have operands (and which therefore must be
> extended asms). In fact we require ASM_INPUT_P to be false for all
> extended asms.
Quite a bad name
committed to trunk.
> You don't need an OK of course but LGTM.
>
> When I found another instance of this I was thinking about having
> exhaustive self tests for those attributes. Maybe a good learning
> exercise?
Yeah, that would be great, otherwise it's not really easy to maintain
those attribu
version.syn#2 requires to define
__cpp_lib_allocator_traits_is_always_equal.
The attached patch therefore defines the
__glibcxx_want_allocator_traits_is_always_equal macro to get the
definition of the feature-test macro from .
This is not isolated only to though. The standard requires the
foll
Thanks for the ping - It's running now:
https://github.com/ewlu/gcc-precommit-ci/issues/2146
Patrick
On 8/27/24 18:22, Li, Pan2 wrote:
Hi Patrick,
Could you please help to re-trigger the pre-commit?
Thanks in advance!
Pan
-Original Message-
From: Patrick O'Neill
Sent: Tuesday, Augu
While working on PR 114224 (popcount costs is not modeled), I noticed
that addv (vector reduction add) was not handled either. This adds the handling
there. Some of the extends are part of the instructions so we need to handle
those
too.
gcc/ChangeLog:
* config/aarch64/aarch64.cc (aarch6
While looking into some popcount related I noticed that the popcount
cost is not modeled at all. This adds both the vector and scalar (for CSSC)
costs. For CSSC, we default to `COSTS_N_INSNS (3)` based on the Ampere1B's
cycle count that is found from LLVM's model.
Built and tested for aarch64-linu
While working on PR 114224, I found it would be useful to dump the
different costs of the expansion to make easier to understand why one
was chosen over the other.
Bootstrapped and tested on x86_64-linux-gnu.
Build and tested for aarch64-linux-gnu.
gcc/ChangeLog:
* internal-fn.cc (expand
From: Pan Li
The .SAT_ADD has 2 operand, when one of the operand may be INTEGER_CST.
For example _1 = .SAT_ADD (_2, 9) comes from below sample code.
Form 3:
#define DEF_VEC_SAT_U_ADD_IMM_FMT_3(T, IMM) \
T __attribute__((noinline))
On Tue, Aug 27, 2024 at 8:54 PM Kugan Vivekanandarajah
wrote:
>
> Hi Richard,
>
> Thanks for the reply.
>
> > On 27 Aug 2024, at 7:05 pm, Richard Biener
> > wrote:
> >
> > External email: Use caution opening links or attachments
> >
> >
> > On Tue, Aug 27, 2024 at 8:23 AM Kugan Vivekanandarajah
Hello, gentle maintainer.
This is a message from the Translation Project robot.
A revised PO file for textual domain 'gcc' has been submitted
by the Georgian team of translators. The file is available at:
https://translationproject.org/latest/gcc/ka.po
(This file, 'gcc-14.2.0.ka.po', has j
Hi Richard,
Thanks for the reply.
> On 27 Aug 2024, at 7:05 pm, Richard Biener wrote:
>
> External email: Use caution opening links or attachments
>
>
> On Tue, Aug 27, 2024 at 8:23 AM Kugan Vivekanandarajah
> wrote:
>>
>> Hi Richard,
>>
>>> On 22 Aug 2024, at 10:34 pm, Richard Biener
>>
Hi all,
Sorry for the disturb since I mis-typoed gcc-patches to gcc-patchs, resend
the patch.
This patch will add documentation for recent update in x86-64 backend.
Ok for wwwdocs trunk?
Thx,
Haochen
---
Mention AVX10.2 support and Xeon Phi removal in GCC 15.
---
htdocs/gcc-15/changes.html
Hi Patrick,
Could you please help to re-trigger the pre-commit?
Thanks in advance!
Pan
-Original Message-
From: Patrick O'Neill
Sent: Tuesday, August 20, 2024 12:14 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com; Jeff Law
Kindly ping.
Pan
-Original Message-
From: Li, Pan2
Sent: Monday, August 19, 2024 10:05 AM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com;
rdapp@gmail.com; Li, Pan2
Subject: [PATCH v2] Test: Move pr116278 run test to dg/torture [NF
Hi Richard,
On 8/7/24 10:47, Richard Sandiford wrote:
> I should probably start by saying that the "model" heuristic is now
> pretty old and was originally tuned for an in-order AArch32 core.
> The aim wasn't to *minimise* spilling, but to strike a better balance
> between parallelising with spill
Hi all,
Thanks for reading my email.
I submitted a patch for libstdc++/complex, but I have no idea if that was
merged. I also have no idea on how to check that. Could someone help me?
Patch name: "[PATCH] libstdc++/complex: Remove implicit type casts in
complex"
Many thanks,
Weslley
--
Wesl
From: Andi Kleen
SPARC does not support vectorizing conditions, which this test relies
on. Use vect_condition as effective target.
Committed as obvious.
PR testsuite/116500
gcc/testsuite/ChangeLog:
* gcc.dg/vect/vect-switch-ifcvt-1.c: Use vect_condition to
check if vectorizing
On 8/22/2024 5:35 AM, Richard Biener wrote:
On Thu, Aug 22, 2024 at 1:03 AM Edwin Lu wrote:
Hi,
Just wanted to ping this for more guidance.
It's difficult for me as long as I cannot investigate this with a testcase. Can
we go ahead with the other parts so the testcase can be added and the
LGTM
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-08-28 03:48
To: juzhe.zh...@rivai.ai; gcc-patches
CC: pal...@dabbelt.com; kito.ch...@gmail.com; jeffreya...@gmail.com;
pan2...@intel.com; Robin Dapp
Subject: Re: [PATCH] RISC-V: Fix subreg of VLS modes larger than a vector
[PR116086].
> +
Jason Merrill writes:
> On 8/1/24 12:48 PM, Arsen Arsenović wrote:
>> Tested on x86_64-pc-linux-gnu, no regression.
>> OK for trunk?
>> TIA, have a lovely day.
>> -- >8 --
>> Previously, we were building and inserting case_labels manually, which
>> lead to them not being added int
When LRA pulls an address operand out of a MEM it caninoicalizes a
containing MULT into ASHIFT. Adjust the address decomposer to recognize
this form.
PR target/116413
* config/m68k/m68k.cc (m68k_decompose_index): Accept ASHIFT like
MULT.
(m68k_rtx_costs) [PLUS]: Li
Update analyze_parms not to disable function parameter analysis for
-ffat-lto-objects. Tested on x86-64, there are no differences in zstd
with "-O2 -flto=auto" -g "vs -O2 -flto=auto -g -ffat-lto-objects".
PR ipa/116410
* ipa-modref.cc (analyze_parms): Always analyze function param
Mikael,
Am 23.08.24 um 10:31 schrieb Mikael Morin:
From: Mikael Morin
The documentation in this patch was partly reworded, compared
to the previous version posted at:
https://gcc.gnu.org/pipermail/gcc-patches/2024-August/660607.html
The rest of the patch is unchanged, just rebased to a more re
> +(define_mode_iterator V_HAS_HALF [
> + V2QI V4QI V8QI V16QI V32QI V64QI V128QI V256QI V512QI V1024QI V2048QI
> V4096QI
> + V2HI V4HI V8HI V16HI V32HI V64HI V128HI V256HI V512HI V1024HI V2048HI
> + V2SI V4SI V8SI V16SI V32SI V64SI V128SI V256SI V512SI V1024SI
> + V2DI V4DI V8DI V16DI V32DI V
On 8/27/24 11:06, Tobias Burnus wrote:
Hi FX,
FX Coudert wrote:
Give it’s a doc patch, I think it might fall under the obvious rule,
and will commit in a week if there is no objection.
The patch clearly fixes a bug in the current specification and is fine,
I just wonder …
* libquadmath.te
On Tue, Aug 27, 2024 at 6:58 AM Qing Zhao wrote:
> > On Aug 27, 2024, at 02:17, Martin Uecker wrote:
> > Am Montag, dem 26.08.2024 um 17:21 -0700 schrieb Kees Cook:
> >> On Mon, Aug 26, 2024 at 11:01:08PM +0200, Martin Uecker wrote:
> >>> Am Montag, dem 26.08.2024 um 13:30 -0700 schrieb Kees Cook
On Tue, Aug 27, 2024 at 06:46:08PM +0200, Thomas Koenig wrote:
> Steve,
>
> > On Sun, Aug 18, 2024 at 12:10:18PM +0200, Thomas Koenig wrote:
> > >
> > > this version of the patch includes DOT_PRODUCT, MATMUL and quite
> > > a few improvements for simplification.
> >
> > Thomas,
> >
> > Your upd
On 8/27/24 1:15 PM, Simon Martin wrote:
Hi Jason,
On 26 Aug 2024, at 19:30, Jason Merrill wrote:
On 8/26/24 12:49 PM, Simon Martin wrote:
We mention 'X::__ct' instead of 'X::X' in the "names the constructor,
not the type" error for this invalid code:
=== cut here ===
struct X {};
void g (
Am 27.08.24 um 17:28 schrieb Jeff Law:
On 8/26/24 1:15 PM, Georg-Johann Lay wrote:
What the avr-ifelse pass does is try to replace 2 cbranch insns with
one compare insn and two branches. It runs after reload and just prior
to .split2 (split_after_reload). It must run after reload because
REG
The documentation of ASM_INPUT_P implied that the flag has no
effect on ASM_EXPRs that have operands (and which therefore must be
extended asms). In fact we require ASM_INPUT_P to be false for all
extended asms.
Tested on aarch64-linux-gnu. OK to install?
Richard
gcc/
* tree.h (ASM_IN
Hi Jason,
On 26 Aug 2024, at 19:30, Jason Merrill wrote:
> On 8/26/24 12:49 PM, Simon Martin wrote:
>> We mention 'X::__ct' instead of 'X::X' in the "names the constructor,
>> not the type" error for this invalid code:
>>
>> === cut here ===
>> struct X {};
>> void g () {
>>X::X x;
>> }
>> =
On 8/27/24 08:04, Jeff Law wrote:
On 8/26/24 6:37 PM, Patrick O'Neill wrote:
These subroutines will be used in expand_const_vector in a future patch.
Relocate so expand_const_vector can use them.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_vector_init_insert_elems):
Relocate.
On 8/27/24 08:04, Jeff Law wrote:
On 8/26/24 6:37 PM, Patrick O'Neill wrote:
Currently we assert when encountering a non-duplicate boolean vector.
This patch allows non-duplicate vectors to fall through to the
gcc_unreachable and assert there.
This will be useful when adding a catch-all pat
On 8/27/24 08:02, Jeff Law wrote:
On 8/26/24 6:36 PM, Patrick O'Neill wrote:
The comment previously here stated that the Wc0/Wc1 cases are handled by
the vi constraint but that is not true for the 0.0 Wc0 case.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_const_insns): Handle 0.0
floa
On 8/27/24 08:01, Jeff Law wrote:
On 8/26/24 6:36 PM, Patrick O'Neill wrote:
These cases are handled in the expander
(riscv-v.cc:expand_const_vector). We need the vector builder to detect
these cases so extract that out into a new riscv-v.h header file.
gcc/ChangeLog:
* config/riscv/ri
On 8/27/24 08:00, Jeff Law wrote:
On 8/26/24 6:36 PM, Patrick O'Neill wrote:
This manifests in RTL that is optimized away which causes runtime
failures
in the testsuite. Update all patterns to use a temp result register
if required.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_co
On 8/27/24 07:56, Jeff Law wrote:
On 8/26/24 6:36 PM, Patrick O'Neill wrote:
The corresponding expander (riscv-v.cc:expand_const_vector) matches
const_vec_duplicate_p before const_vec_series_p. Reorder to match this
behavior when calculating costs.
gcc/ChangeLog:
* config/riscv/riscv.c
On 8/27/24 07:55, Jeff Law wrote:
On 8/26/24 6:36 PM, Patrick O'Neill wrote:
Prior to this patch the expander would emit vectors like:
{ 0, 0, 5, 5, 10, 10, ...}
as:
{ 0, 0, 2, 2, 4, 4, ...}
This patch sets the step size to the requested value.
gcc/ChangeLog:
* config/riscv/riscv-v.
Hi FX,
FX Coudert wrote:
Give it’s a doc patch, I think it might fall under the obvious rule, and will
commit in a week if there is no objection.
The patch clearly fixes a bug in the current specification and is fine,
I just wonder …
* libquadmath.texi (M_LOG2Eq, M_LOG10Eq, M_2_PIq): Fix
On 8/27/24 08:19, Jeff Law wrote:
On 8/26/24 6:37 PM, Patrick O'Neill wrote:
This patch adds some advanced checking to assert that the emitted
costs match
emitted patterns for const_vecs.
Flow:
Costing: Insert into hashmap>
Expand: Check for membership in hashmap
-> Not in hashmap: ignor
kind ping
Give it’s a doc patch, I think it might fall under the obvious rule, and will
commit in a week if there is no objection.
FX
> As reported by Peter Randall, the description of three constants in
> libquadmath is wrong. Attached patch fixes them.
>
> OK to push?
>
> FX
>
>
> libquad
Steve,
On Sun, Aug 18, 2024 at 12:10:18PM +0200, Thomas Koenig wrote:
this version of the patch includes DOT_PRODUCT, MATMUL and quite
a few improvements for simplification.
Thomas,
Your updated patch applied cleanly on top-of-tree gcc.
Bootstrap and regression testing on amd64-*-freebsd
co
On Tue, Aug 27, 2024 at 12:25 PM Richard Biener
wrote:
> On Mon, Aug 26, 2024 at 5:26 PM Matevos Mehrabyan
> wrote:
> >
> >
> >
> > On Mon, Aug 26, 2024 at 2:44 AM Jeff Law wrote:
> >>
> >>
> >>
> >> On 8/20/24 5:41 AM, Richard Biener wrote:
> >>
> >> >
> >> > So the store-merging variant IIRC
On 8/26/24 1:15 PM, Georg-Johann Lay wrote:
What the avr-ifelse pass does is try to replace 2 cbranch insns with
one compare insn and two branches. It runs after reload and just prior
to .split2 (split_after_reload). It must run after reload because
REG_CC comes into existence in .split2.
On 8/26/24 4:48 PM, Mark Harmstone wrote:
Run all CodeView names through a new function get_name, which chains
together a DIE's DW_AT_name with that of its parent to create a
C++-style name.
gcc/
* dwarf2codeview.cc (get_name): New function.
(add_enum_forward_def): Call get_na
On 15/08/2024 13:55, Richard Sandiford wrote:
> scanltranstree.exp defines some LTO wrappers around standard
> non-LTO scanners. Four of them are cut-&-paste variants of
> one another, so this patch generates them from a single template.
> It also does the same for scan-ltrans-tree-dump-times, so
On 8/26/24 6:37 PM, Patrick O'Neill wrote:
This patch adds some advanced checking to assert that the emitted costs match
emitted patterns for const_vecs.
Flow:
Costing: Insert into hashmap>
Expand: Check for membership in hashmap
-> Not in hashmap: ignore, this wasn't costed
-> In hashmap
On 8/26/24 6:37 PM, Patrick O'Neill wrote:
Also explicitly disallow CONST_VECTOR_DUPLICATE_P for now.
CONST_VECTOR_DUPLICATE_P was previously disallowed implicitly.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_vec_series): Update comment.
(expand_vector_init_insert_elems)
On 8/26/24 6:37 PM, Patrick O'Neill wrote:
These subroutines will be used in expand_const_vector in a future patch.
Relocate so expand_const_vector can use them.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_vector_init_insert_elems): Relocate.
(expand_vector_init_trailing
On 8/26/24 6:37 PM, Patrick O'Neill wrote:
Currently we assert when encountering a non-duplicate boolean vector.
This patch allows non-duplicate vectors to fall through to the
gcc_unreachable and assert there.
This will be useful when adding a catch-all pattern to emit costs and
handle arbita
On 8/26/24 6:36 PM, Patrick O'Neill wrote:
The comment previously here stated that the Wc0/Wc1 cases are handled by
the vi constraint but that is not true for the 0.0 Wc0 case.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_const_insns): Handle 0.0 floating-point
case.
OK
Jef
On 8/26/24 6:36 PM, Patrick O'Neill wrote:
These cases are handled in the expander
(riscv-v.cc:expand_const_vector). We need the vector builder to detect
these cases so extract that out into a new riscv-v.h header file.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (class rvv_builder): Mo
On 8/26/24 6:36 PM, Patrick O'Neill wrote:
This manifests in RTL that is optimized away which causes runtime failures
in the testsuite. Update all patterns to use a temp result register if required.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_const_vector): Use tmp register if
On 8/26/24 6:36 PM, Patrick O'Neill wrote:
The corresponding expander (riscv-v.cc:expand_const_vector) matches
const_vec_duplicate_p before const_vec_series_p. Reorder to match this
behavior when calculating costs.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_const_insns): Relocate.
On 8/26/24 6:36 PM, Patrick O'Neill wrote:
Prior to this patch the expander would emit vectors like:
{ 0, 0, 5, 5, 10, 10, ...}
as:
{ 0, 0, 2, 2, 4, 4, ...}
This patch sets the step size to the requested value.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_const_vector): Fix ST
On 8/27/24 8:02 AM, Robin Dapp wrote:
Hi,
this is a hopefully better way to solve the "subreg problem" by first,
in the generic case, have the RA go via memory and second, providing a
vector-vector extract that deals with it in an optimized way.
When the source mode is potentially larger tha
+(define_mode_iterator V_HAS_HALF [
+ V2QI V4QI V8QI V16QI V32QI V64QI V128QI V256QI V512QI V1024QI V2048QI V4096QI
+ V2HI V4HI V8HI V16HI V32HI V64HI V128HI V256HI V512HI V1024HI V2048HI
+ V2SI V4SI V8SI V16SI V32SI V64SI V128SI V256SI V512SI V1024SI
+ V2DI V4DI V8DI V16DI V32DI V64DI V128DI V
Andreas Schwab writes:
> On Aug 27 2024, H.J. Lu wrote:
>
>> diff --git a/gcc/testsuite/gcc.target/i386/pr116174.c
>> b/gcc/testsuite/gcc.target/i386/pr116174.c
>> index 8877d0b51af..686aeb9ff31 100644
>> --- a/gcc/testsuite/gcc.target/i386/pr116174.c
>> +++ b/gcc/testsuite/gcc.target/i386/pr1161
* gcc.target/i386/pr116174.c: Add the missing */.
Signed-off-by: H.J. Lu
---
gcc/testsuite/gcc.target/i386/pr116174.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/i386/pr116174.c
b/gcc/testsuite/gcc.target/i386/pr116174.c
index 686aeb9ff31
You don't need an OK of course but LGTM.
When I found another instance of this I was thinking about having
exhaustive self tests for those attributes. Maybe a good learning
exercise?
--
Regards
Robin
On Aug 27 2024, H.J. Lu wrote:
> diff --git a/gcc/testsuite/gcc.target/i386/pr116174.c
> b/gcc/testsuite/gcc.target/i386/pr116174.c
> index 8877d0b51af..686aeb9ff31 100644
> --- a/gcc/testsuite/gcc.target/i386/pr116174.c
> +++ b/gcc/testsuite/gcc.target/i386/pr116174.c
> @@ -1,6 +1,20 @@
> /* {
We add pattern for vector rotate, but seems like we forgot adding
mode_idx which used in AVL propgation (riscv-avlprop.cc).
gcc/ChangeLog:
* config/riscv/vector.md (mode_idx): Add vrol and vror.
gcctestsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/rotr.c: New.
---
gcc/config/
On Tue, Aug 27, 2024 at 6:54 AM Richard Sandiford
wrote:
>
> "H.J. Lu" writes:
> >> > append function_regexp ")"
> >> > } elseif { [string equal $line "..."] } {
> >> > append function_regexp ".*"
> >> > + } elseif { [regexp "^.L.*" $line] } {
> >>
>
As PR target/116174 shown, we may need to verify labels and the directive
order. Extend check-function-bodies to support matched output lines to
allow label and directives.
gcc/
* doc/sourcebuild.texi (check-function-bodies): Add an optional
argument for matched output lines.
gc
Hi,
this is the second version of this patch. See the mail with the first version
here:
https://inbox.sourceware.org/gcc-patches/ZsnRLdYErnIWQlCe@localhost.localdomain/
In this version I've made these adjustments:
- Added calls direct_internal_fn_supported_p to can_pow2p. Before I just
assum
Hi,
this is a hopefully better way to solve the "subreg problem" by first,
in the generic case, have the RA go via memory and second, providing a
vector-vector extract that deals with it in an optimized way.
When the source mode is potentially larger than one vector (e.g. an
LMUL2 mode for VLEN=1
> On Aug 27, 2024, at 02:17, Martin Uecker wrote:
>
> Am Montag, dem 26.08.2024 um 17:21 -0700 schrieb Kees Cook:
>> On Mon, Aug 26, 2024 at 11:01:08PM +0200, Martin Uecker wrote:
>>> Am Montag, dem 26.08.2024 um 13:30 -0700 schrieb Kees Cook:
On Mon, Aug 26, 2024 at 07:30:15PM +, Qing
"H.J. Lu" writes:
>> > append function_regexp ")"
>> > } elseif { [string equal $line "..."] } {
>> > append function_regexp ".*"
>> > + } elseif { [regexp "^.L.*" $line] } {
>>
>> {^\.L} would be more precise than "^.L.*".
>
> I tried {^\.L}. It did
On Tue, Aug 27, 2024 at 2:18 AM Richard Sandiford
wrote:
>
> "H.J. Lu" writes:
> > As PR target/116174 shown, we may need to verify labels and the directive
> > order. Extend check-function-bodies to support matched output lines to
> > allow label and directives.
> >
> > gcc/
> >
> > * doc
Hello,
On Mon, 26 Aug 2024, Paul Koning wrote:
> >>> Yeah, I wondered as well. For things to go wrong some instructions that
> >>> contain pre/post-inc/dec of the stack pointer need to have reloads in
> >>> such
> >>> a way that the actual SP-change sideeffect moves to a different
> >>> inst
As PR target/116174 shown, we may need to verify labels and the directive
order. Extend check-function-bodies to support matched output lines to
allow label and directives.
gcc/
* doc/sourcebuild.texi (check-function-bodies): Add an optional
argument for matched output lines.
gc
> On Aug 26, 2024, at 17:01, Martin Uecker wrote:
>
> Am Montag, dem 26.08.2024 um 13:30 -0700 schrieb Kees Cook:
>> On Mon, Aug 26, 2024 at 07:30:15PM +, Qing Zhao wrote:
>>> Hi, Martin,
>>>
>>> Looks like that there is some issue when I tried to use the _Generic for
>>> the testing case
> On Aug 26, 2024, at 16:30, Kees Cook wrote:
>
> On Mon, Aug 26, 2024 at 07:30:15PM +, Qing Zhao wrote:
>> Hi, Martin,
>>
>> Looks like that there is some issue when I tried to use the _Generic for the
>> testing cases, and then I narrowed down to a
>> small testing case that shows the p
This default constructor was made private by r15-3124-gb25b101bc38000 so
the pretty printer tests need a fix to stop using it. There's no
conforming way to get a default-constructed 'reference' now, e.g. trying
to access an element of a default-constructed std::vector will
trigger an assertion. Rem
On Mon, 26 Aug 2024 at 00:08, Andrew Pinski wrote:
>
> On Fri, Aug 23, 2024 at 5:20 AM Jonathan Wakely wrote:
> >
> > Tested x86_64-linux. Pushed to trunk.
> >
> > -- >8 --
> >
> > The standard says this constructor should be private. LWG 4141 proposes
> > to remove it entirely. We still need it
> On Aug 26, 2024, at 15:46, Bill Wendling wrote:
>
> On Wed, Aug 21, 2024 at 8:43 AM Martin Uecker wrote:
>>
>> Am Mittwoch, dem 21.08.2024 um 15:24 + schrieb Qing Zhao:
But if we changed it to return a void pointer, we could make this
a compile-time check:
au
On 8/27/24 1:17 AM, pan2...@intel.com wrote:
From: Pan Li
This patch would like to add test cases for the unsigned scalar
.SAT_SUB IMM form 3. Aka:
Form 3:
#define DEF_SAT_U_SUB_IMM_FMT_3(T, IMM) \
T __attribute__((noinline)) \
sat_u_sub_imm##IMM##_##T##_fmt_3 (T y) \
On Tue, 27 Aug 2024, Dora, Sunil Kumar wrote:
> Dear GCC Team,
>
> Please consider this as a gentle reminder to review the patch I posted at the
> following link: [
> https://gcc.gnu.org/pipermail/gcc-patches/2024-August/660223.html ].
>
> BUG Link : [ https://gcc.gnu.org/bugzilla/show_bug.cgi
Hi Jeff,
Yes, there are some tests fails after the last_combine pass introduced.
I remember these tests still have vv format which not become vf after
last_combine.
I’ll update the testcase based on my local branch after your push.
Regards,
Demin
From: Jeff Law
Sent: 2024年8月26日 5:59
To: Demin
On Tue, Aug 27, 2024 at 1:53 PM wrote:
>
> From: Pan Li
>
> This patch would like to support the form 1 of the scalar signed
> integer .SAT_ADD. Aka below example:
>
> Form 1:
> #define DEF_SAT_S_ADD_FMT_1(T, UT, MIN, MAX) \
> T __attribute__((noinline)) \
> sat_s_add_##T#
From: Pan Li
This patch would like to support the form 1 of the scalar signed
integer .SAT_ADD. Aka below example:
Form 1:
#define DEF_SAT_S_ADD_FMT_1(T, UT, MIN, MAX) \
T __attribute__((noinline)) \
sat_s_add_##T##_fmt_1 (T x, T y) \
{
On 13/08/2024 17:18, Andre Vieira (lists) wrote:
> I'm not a maintainer but I'd argue the entire test is bogus.
>
> The error reporting in this area seems to be somewhat fragile, if you compile
> it with '-march=armv7-a -mfloat-abi=soft', you also don't get the error this
> is testing for. I'd
> :c is required when you want to match up @0s and they appear in a commutative
> operation and there's no canonicalization rule putting it into one or the
> other
> position. In your case you have two commutative operations you want to match
> up, so it should be only necessary to try swapping o
Thanks Richard for comments.
> Err, can you please simply do
>if (TREE_CODE (ops[1]) == INTEGER_CST)
> ops[1] = fold_convert (TREE_TYPE (ops[0]), ops[1])
> ? you are always matching the constant to @1 IIRC.
That would be much more simple, will have a try in v3.
Pan
--
> -Original Message-
> From: Richard Sandiford
> Sent: Tuesday, August 27, 2024 11:46 AM
> To: Tamar Christina
> Cc: Jennifer Schmitz ; gcc-patches@gcc.gnu.org; Kyrylo
> Tkachov
> Subject: Re: [RFC][PATCH] AArch64: Remove
> AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS
>
> Tamar Christina wr
Hi Andrew,
Andrew Stubbs:
On 22/08/2024 19:26, Tobias Burnus wrote:
(A) Any comments, suggestions regarding the patch in general and in
particular the plugin/ related parts?
The code all looks pretty reasonable to me.
The header file conditional includes worry me though: it is adding
comple
Found a few more places that had similar issue with the termination of the
comment, so fixed them all.
Pushed below patch as obvious (r15-3215).
--
gcc/testsuite/ChangeLog:
* gcc.dg/pr108757-1.c: Fixed dg-comment.
* gcc.dg/pr71071.c: Likewise.
* gcc.dg/tree-ssa/noretur
Hi!
On 2024-08-19T13:14:02-0700, Edwin Lu wrote:
> The testcase has been modified to include the -fwrapv flag which now
> causes the test to pass. Remove the xfail exception
> --- a/gcc/testsuite/gcc.dg/signbit-5.c
> +++ b/gcc/testsuite/gcc.dg/signbit-5.c
> @@ -4,7 +4,6 @@
> /* This test does n
Tamar Christina writes:
> Hi Jennifer,
>
>> -Original Message-
>> From: Jennifer Schmitz
>> Sent: Friday, August 23, 2024 1:07 PM
>> To: gcc-patches@gcc.gnu.org
>> Cc: Richard Sandiford ; Kyrylo Tkachov
>>
>> Subject: [RFC][PATCH] AArch64: Remove
>> AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COST
On 21/08/2024 17:06, Christophe Lyon wrote:
> On Wed, 14 Aug 2024 at 22:04, Torbjörn SVENSSON
> wrote:
>>
>> Ok for trunk and releases/gcc-14?
>>
>> --
>>
>> On Cortex-M55 with fpv5-d16, the vmov.f64 instruction is used.
>
> Hi Torbjorn,
>
> Thanks for the patch: after looking further I realized
On 21/08/2024 17:03, Christophe Lyon wrote:
> With MVE, vmov.f64 is always supported (no need for +fp.dp extension).
>
> This patch updates two patterns:
> - in movdi_vfp, we incorrectly checked
> TARGET_VFP_SINGLE || TARGET_HAVE_MVE instead of
> TARGET_VFP_SINGLE && !TARGET_HAVE_MVE, and didn
Hi,
This is a v3 that hopefully addresses the feedback from both Jason and
Jakub. v2 was posted here:
https://gcc.gnu.org/pipermail/gcc-patches/2024-August/660191.html
(Sorry for the delay in posting the re-spin, I was away last week.)
In this version we refactor to introudce a helper class (an
LGTM, good catch, and I am a little suppressed that we don't handle
"case REG" in riscv_rtx_costs...but adding that might disturb too much
at once, so this fix is fine for now, and ...and I guess we should
improve that in future.
On Tue, Aug 27, 2024 at 5:19 PM Xianmiao Qu wrote:
>
> Currently,
On 22/08/2024 19:26, Tobias Burnus wrote:
This patch adds OpenMP's interop support to the libgomp plugins (nvptx:
cuda, cuda_driver, hip; gcn: hip, hsa).*
[The idea is that the user can ask OpenMP to return a foreign-runtime
handle (CUdevice, hipCtx_t, …) for to a specified OpenMP device numbe
Currently, in RV32, even with the D extension enabled, the cost of DFmode
register moves is still set to 'COSTS_N_INSNS (2)'. This results in the
'lower-subreg' pass splitting DFmode register moves into two SImode SUBREG
register moves, leading to the generation of many redundant instructions.
As
"H.J. Lu" writes:
> As PR target/116174 shown, we may need to verify labels and the directive
> order. Extend check-function-bodies to support matched output lines to
> allow label and directives.
>
> gcc/
>
> * doc/sourcebuild.texi (check-function-bodies): Add an optional
> argument
On Tue, Aug 27, 2024 at 9:09 AM wrote:
>
> From: Pan Li
>
> The .SAT_ADD has 2 operand, when one of the operand may be INTEGER_CST.
> For example _1 = .SAT_ADD (_2, 9) comes from below sample code.
>
> Form 3:
> #define DEF_VEC_SAT_U_ADD_IMM_FMT_3(T, IMM) \
> T __attr
On Tue, Aug 27, 2024 at 8:23 AM Kugan Vivekanandarajah
wrote:
>
> Hi Richard,
>
> > On 22 Aug 2024, at 10:34 pm, Richard Biener
> > wrote:
> >
> > External email: Use caution opening links or attachments
> >
> >
> > On Wed, Aug 21, 2024 at 12:08 PM Kugan Vivekanandarajah
> > wrote:
> >>
> >> Hi
On Tue, Aug 27, 2024 at 5:20 AM liuhongt wrote:
>
> > You are possibly overwriting src_related_elt - I'd suggest to either break
> > here or do the loop below for each found elt?
> Changed.
>
> > Do we know that will always succeed?
> 1) validate_subreg allows subreg for 2 vector modes with same c
Dear GCC Team,
Please consider this as a gentle reminder to review the patch I posted at the
following link: [
https://gcc.gnu.org/pipermail/gcc-patches/2024-August/660223.html ].
BUG Link : [ https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111527 ]
Your feedback or approval would be greatly appr
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