On 8/26/24 6:36 PM, Patrick O'Neill wrote:
This manifests in RTL that is optimized away which causes runtime failures
in the testsuite. Update all patterns to use a temp result register if required.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_const_vector): Use tmp register if
needed.
OK. Just a note below, I don't think you necessarily need to change
anything.
Signed-off-by: Patrick O'Neill <patr...@rivosinc.com>
---
gcc/config/riscv/riscv-v.cc | 73 +++++++++++++++++++++----------------
1 file changed, 41 insertions(+), 32 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index a3039a2cb19..aea4b9b872b 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1150,26 +1150,29 @@ static void
expand_const_vector (rtx target, rtx src)
{
machine_mode mode = GET_MODE (target);
+ rtx result = register_operand (target, mode) ? target : gen_reg_rtx (mode);
So a cheaper test would be REG_OR_SUBREG_P rather than register_operand.
While testing register_operand does check the mode, if we have a
mismatch on the modes between src/target, then the copy from result to
target is going to fail.
But again, I don't think you really need to change anything here. Just
pointing out the marginally more efficient test.
jeff
