On Mon, Aug 28, 2023 at 11:33:37AM +0200, Andreas Krebbel wrote:
> Hi Stefan,
>
> do you really need to introduce a new flag for U64 given that the type of the
> builtin is unsigned long?
In function s390_const_operand_ok the immediate is checked whether it is
valide w.r.t. the flag:
tree_to_
The subject should be "Add tests for SX vector floating-point
instructions". The "support" has already been added.
Likewise for patches 5-9.
--
Xi Ruoyao
School of Aerospace Science and Technology, Xidian University
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/vector/lsx/lsx-vsadd-1.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vsadd-2.c: New test.
---
.../loongarch/vector/lsx/lsx-vsadd-1.c| 335 +
.../loongarch/vector/lsx/lsx-vsadd-2.c| 345 +++
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/vector/lsx/lsx-builtin.c: New test.
---
.../loongarch/vector/lsx/lsx-builtin.c| 5038 +
1 file changed, 5038 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c
diff --git a/
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/strict-align.c: New test.
---
gcc/testsuite/gcc.target/loongarch/strict-align.c | 12
1 file changed, 12 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/loongarch/strict-align.c
diff --git a/gcc/testsuite/gcc.target/
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/vector/loongarch-vector.exp: New test.
* gcc.target/loongarch/vector/simd_correctness_check.h: New test.
---
.../loongarch/vector/loongarch-vector.exp | 42 +++
.../loongarch/vector/simd_correctness_check.h | 54 +
v2 -> v3:
Standardize the code using the GNU format.
In order to better test the function of the vector instruction, the 128 and
256
bit test cases are further split according to the function of the instruction.
Xiaolong Chen (9):
LoongArch: Add tests of -mstrict-align option.
LoongArch
Ping this patch.
I think it's time to enable scalable vectorization by default and do the whole
regression every time (except vect.exp that we didn't enable yet)
Update current FAILs status:
Real FAILS (ICE and execution FAIL):
FAIL: gcc.dg/pr70252.c (internal compiler error: in
gimple_expand
I found that it's more reasonable to use existing dominance analysis.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc
(pass_vsetvl::global_eliminate_vsetvl_insn): Use dominance analysis.
(pass_vsetvl::init): Ditto.
(pass_vsetvl::done): Ditto.
---
gcc/config/riscv/riscv-vs
This patch add VLS modes VEC_PERM support which fix these following
FAILs in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111311:
FAIL: gcc.dg/tree-ssa/forwprop-40.c scan-tree-dump-times optimized
"BIT_FIELD_REF" 0
FAIL: gcc.dg/tree-ssa/forwprop-40.c scan-tree-dump-times optimized
"BIT_INSERT_EX
Sure. Thanks kito.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-09-11 10:57
To: juzhe.zh...@rivai.ai
CC: gcc-patches; Kito.cheng
Subject: Re: Re: [PATCH] RISC-V: Add VLS modes VEC_PERM support[PR111311]
OK, but could you split this patch into two patches? pre-approved for both.
On Mon, S
Committed.
gcc/ChangeLog:
* config/riscv/autovec-vls.md (*mov_vls): New pattern.
* config/riscv/vector-iterators.md: New iterator
---
gcc/config/riscv/autovec-vls.md | 8
gcc/config/riscv/vector-iterators.md | 15 +++
2 files changed, 23 insertions(+)
OK, but could you split this patch into two patches? pre-approved for both.
On Mon, Sep 11, 2023 at 10:36 AM juzhe.zh...@rivai.ai
wrote:
>
> >> Should we also add loads and stores as well?
> >> and just make sure this is also necessary for the fix and not sneaky,
> >> right?
>
> No, we don't nee
>> Should we also add loads and stores as well?
>> and just make sure this is also necessary for the fix and not sneaky, right?
No, we don't need loads/stores. Since this following handling codes:
(define_insn_and_split "*mov_lra"
[(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand" "=vr, m,v
On 9/10/23 20:18, Andrew Pinski via Gcc-patches wrote:
I noticed this while working on other MINMAX optimizations. It was
hard to find a simplified testcase though because it was dependent on
the ssa name versions. Adding the `:c` to cmp allows the pattern to
be match for the case where minmax
> diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md
> index d208b418e5f..6f48f7d6232 100644
> --- a/gcc/config/riscv/autovec-vls.md
> +++ b/gcc/config/riscv/autovec-vls.md
> @@ -148,6 +148,14 @@
>[(set_attr "type" "vmov")
> (set_attr "mode" "")])
>
> +(define_in
I noticed this while working on other MINMAX optimizations. It was
hard to find a simplified testcase though because it was dependent on
the ssa name versions. Adding the `:c` to cmp allows the pattern to
be match for the case where minmax as the first operand of the comparison
rather than the seco
On Thu, Sep 7, 2023 at 1:28 PM David Malcolm wrote:
> On Mon, 2023-09-04 at 22:13 -0400, Eric Feng wrote:
>
> > Hi Dave,
>
> Hi Eric, thanks for the patch.
>
> >
> > Recently I've been working on symbolic value support for the reference
> > count checker. I've attached a patch for it below; let m
Here's the patch I've commited.
The patch also remove % for vfmaddcph.
gcc/ChangeLog:
PR target/111306
PR target/111335
* config/i386/sse.md (int_comm): New int_attr.
(fma__):
Remove % for Complex conjugate operations since they're not
commutative.
Committed, thanks Jeff.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Jeff Law via Gcc-patches
Sent: Sunday, September 10, 2023 9:38 PM
To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org
Cc: kito.ch...@sifive.com; kito.ch...@gmail.com
Subject: Re: [PATCH] RISC-V: Expand fixed-vlmax/vls v
Committed, thanks Jeff.
Pan
-Original Message-
From: Gcc-patches On Behalf
Of Jeff Law via Gcc-patches
Sent: Sunday, September 10, 2023 11:25 PM
To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org
Cc: kito.ch...@sifive.com; kito.ch...@gmail.com
Subject: Re: [PATCH V2] RISC-V: Avoid unnecessary sl
Some targets like arm-eabi with newlib and default settings rely on
__sync_synchronize() to ensure synchronization. Newlib does not
implement it by default, to make users aware they have to take special
care.
This makes a few tests fail to link.
This patch requires the missing thread-fence effec
Some targets like arm-eabi with newlib and default settings rely on
__sync_synchronize() to ensure synchronization. Newlib does not
implement it by default, to make users aware they have to take special
care.
This makes a few tests fail to link.
This patch adds a new thread_fence effective targe
swap: Fix incorrect lane extraction by vec_extract() [PR106770]
In the routine rs6000_analyze_swaps(), special handling of swappable
instructions is done even if the webs that contain the swappable
instructions are not optimized, i.e., the webs do not contain any
permuting load/store instructions
Ping.
> > > On Thu, Aug 10, 2023 at 03:04:03PM +0200, Stefan Schulze Frielinghaus
> > > wrote:
> > > > In the former fix in commit 41ef5a34161356817807be3a2e51fbdbe575ae85 I
> > > > completely missed the fact that the normal form of a generated constant
> > > > for a
> > > > mode with fewer bits
On 9/8/23 06:39, Andrew Pinski via Gcc-patches wrote:
The problem here is after r6-7425-ga9fee7cdc3c62d0e51730,
the comparison to see if the transformation could be done was using the
wrong value. Instead of see if the inner was LE (for MIN and GE for MAX)
the outer value, it was comparing the
On 8/31/23 11:36, Edwin Lu wrote:
Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/
This patch updates the THEAD instructions to ensure that no insn is left
without a type attribute.
Tested for regressions using rv32/64 multilib for
François Dumont via Gcc-patches writes:
> Following confirmation of the fix by TC here is the patch where I'm
> simply adding a 'constexpr' on _M_next().
>
> Please let me know this ChangeLog entry is correct. I would prefer
> this patch to be assigned to 'TC' with me as co-author but I don't
>
On 9/10/23 08:07, Juzhe-Zhong wrote:
gcc/ChangeLog:
* config/riscv/riscv-v.cc (shuffle_compress_patterns): Avoid
unnecessary slideup.
OK
jeff
Address comment: [PATCH V2] RISC-V: Avoid unnecessary slideup in compress
pattern of vec_perm (gnu.org)
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-09-10 21:34
To: Juzhe-Zhong; gcc-patches
CC: kito.cheng; kito.cheng; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Avoid unnecessary slideup in compr
Tested on x86_64-darwin21 and i686-darwin9 with both dwarfutils and
llvm-based dsymutil implementations. Pushed to trunk, thanks
Iain
--- 8< ---
Although the Darwin ABI places both hot and cold partitions in the same
section (the linker can partition by name), this does not work with the
current
Address comment: [PATCH V2] RISC-V: Avoid unnecessary slideup in compress
pattern of vec_perm (gnu.org)
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-09-10 22:07
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH V2] RISC-V: Avoid unnecessary s
gcc/ChangeLog:
* config/riscv/riscv-v.cc (shuffle_compress_patterns): Avoid
unnecessary slideup.
---
gcc/config/riscv/riscv-v.cc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index bee60de1d26..3cd1f61de0e
Following confirmation of the fix by TC here is the patch where I'm
simply adding a 'constexpr' on _M_next().
Please let me know this ChangeLog entry is correct. I would prefer this
patch to be assigned to 'TC' with me as co-author but I don't know how
to do such a thing. Unless I need to chan
On 9/9/23 20:33, Juzhe-Zhong wrote:
When debugging FAIL: gcc.dg/pr92301.c execution test.
Realize a vls vector permutation situation failed to vectorize since early
return false:
- /* For constant size indices, we dont't need to handle it here.
- Just leave it to vec_perm. */
- if (d-
On 9/9/23 21:55, Juzhe-Zhong wrote:
If a const vector all elements are same, the slide up is unnecessary.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (shuffle_compress_patterns): Avoid
unnecessary slideup.
---
gcc/config/riscv/riscv-v.cc | 2 +-
1 file changed, 1 insertion(+), 1 de
Thanks Joseph, below is a a revised version of this patch
with slight additional changes to the comment of
tagged_types_tu_compatible_p.
ok for trunk?
Martin
Am Mittwoch, dem 06.09.2023 um 20:59 + schrieb Joseph Myers:
> On Sat, 26 Aug 2023, Martin Uecker via Gcc-patches wrote:
>
> > -st
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