Address comment: [PATCH V2] RISC-V: Avoid unnecessary slideup in compress
pattern of vec_perm (gnu.org)
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-09-10 22:07
To: gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH V2] RISC-V: Avoid unnecessary slideup in compress pattern of
vec_perm
gcc/ChangeLog:
* config/riscv/riscv-v.cc (shuffle_compress_patterns): Avoid unnecessary
slideup.
---
gcc/config/riscv/riscv-v.cc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index bee60de1d26..3cd1f61de0e 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2647,7 +2647,8 @@ shuffle_compress_patterns (struct expand_vec_perm_d *d)
For index = { 0, 2, 5, 6}, we need to slide op1 up before
we apply compress approach. */
- bool need_slideup_p = maybe_ne (d->perm[vlen - 1], 2 * vec_len - 1);
+ bool need_slideup_p = maybe_ne (d->perm[vlen - 1], 2 * vec_len - 1)
+ && !const_vec_duplicate_p (d->op1);
/* If we leave it directly be handled by general gather,
the code sequence will be:
--
2.36.3
