[PING] nvptx: Re-enable a number of test cases

2022-12-19 Thread Thomas Schwinge
Hi! Ping this whole series. Grüße Thomas On 2022-12-02T13:03:06+0100, Thomas Schwinge wrote: > Hi! > > I'm proposing to re-enable a number of test cases for nvptx. OK to push? > > > Grüße > Thomas - Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße 201, 806

[PING^2] nvptx: stack size limits are relevant for execution only (was: [PATCH, testsuite] Add effective target stack_size)

2022-12-19 Thread Thomas Schwinge
Hi! Ping. Grüße Thomas On 2022-11-25T12:09:36+0100, I wrote: > Hi! > > Ping. > > > Grüße > Thomas > > > On 2022-11-08T21:29:49+0100, I wrote: >> Hi! >> >> On 2017-06-09T16:24:30+0200, Tom de Vries wrote: >>> The patch defines an effective target stack_size, which is used in >>> individual t

Re: [PATCH V2 2/2] [x86] x86: Add a new option -mdaz-ftz to enable FTZ and DAZ flags in MXCSR.

2022-12-19 Thread Hongtao Liu via Gcc-patches
On Thu, Dec 15, 2022 at 3:45 PM Hongtao Liu wrote: > > On Thu, Dec 15, 2022 at 3:39 PM Jakub Jelinek wrote: > > > > On Thu, Dec 15, 2022 at 02:21:37PM +0800, liuhongt via Gcc-patches wrote: > > > --- a/gcc/config/i386/i386.opt > > > +++ b/gcc/config/i386/i386.opt > > > @@ -420,6 +420,10 @@ mpc80

Re: [PATCH V7] rs6000: Optimize cmp on rotated 16bits constant

2022-12-19 Thread Jiufu Guo via Gcc-patches
Hi Segher, Thanks for your review, and helpful comments! Segher Boessenkool writes: > Hi! > > Mostlt nitpicking left: > > On Mon, Dec 19, 2022 at 10:06:45PM +0800, Jiufu Guo wrote: >> When checking eq/ne with a constant which has only 16bits, it can be >> optimized to check the rotated data.

Re: [committed] testsuite: Fix up pr107397.f90 test [PR107397]

2022-12-19 Thread Jerry D via Gcc-patches
On 12/19/22 2:29 AM, Jakub Jelinek wrote: On Sat, Dec 17, 2022 at 09:12:43AM -0800, Jerry D via Gcc-patches wrote: The attached patch fixes a regression and is a patch from Steve. I have regression tested it and provided a test case. It is fairly simple and I will commit under the "simple" rul

Ping [PATCH v3] Add condition coverage profiling

2022-12-19 Thread Jørgen Kvalsvik via Gcc-patches
On 05/12/2022 10:40, Jørgen Kvalsvik wrote: > This patch adds support in gcc+gcov for modified condition/decision > coverage (MC/DC) with the -fprofile-conditions flag. MC/DC is a type of > test/code coverage and it is particularly important in the avation and > automotive industries for safety-cri

Re: [PATCH] RISC-V: Fix incorrect annotation

2022-12-19 Thread Jeff Law via Gcc-patches
On 12/19/22 16:13, juzhe.zh...@rivai.ai wrote: From: Ju-Zhe Zhong gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (anticipatable_occurrence_p): Fix incorrect annotations. (available_occurrence_p): Ditto. (backward_propagate_worthwhile_p): Ditto. (can_backw

Re: [PATCH] RISC-V: Fix muti-line condition format

2022-12-19 Thread Jeff Law via Gcc-patches
On 12/19/22 16:09, juzhe.zh...@rivai.ai wrote: From: Ju-Zhe Zhong gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (vlmax_avl_insn_p): Fix multi-line conditional. (vsetvl_insn_p): Ditto. (same_bb_and_before_p): Ditto. (same_bb_and_after_or_equal_p): Ditto.

[PATCH] RISC-V: Fix incorrect annotation

2022-12-19 Thread juzhe . zhong
From: Ju-Zhe Zhong gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (anticipatable_occurrence_p): Fix incorrect annotations. (available_occurrence_p): Ditto. (backward_propagate_worthwhile_p): Ditto. (can_backward_propagate_p): Ditto. --- gcc/config/riscv/riscv-vs

[PATCH] RISC-V: Fix muti-line condition format

2022-12-19 Thread juzhe . zhong
From: Ju-Zhe Zhong gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (vlmax_avl_insn_p): Fix multi-line conditional. (vsetvl_insn_p): Ditto. (same_bb_and_before_p): Ditto. (same_bb_and_after_or_equal_p): Ditto. --- gcc/config/riscv/riscv-vsetvl.cc | 16

Re: Re: [PATCH] RISC-V: Support VSETVL PASS for RVV support

2022-12-19 Thread 钟居哲
>> ISTM that if you want to run before sched2, then >> you'd need to introduce dependencies between the vsetvl instrutions and >> the vector instructions that utilize those settings? Yes, I want to run before sched2 so that we could have the chance to do the instruction scheduling before sched2.

Re: [PATCH] fold-const: Treat fp conversion to a type with same mode as copy

2022-12-19 Thread Segher Boessenkool
Hi! On Mon, Dec 19, 2022 at 11:02:30AM +0100, Jakub Jelinek wrote: > On Mon, Dec 19, 2022 at 09:49:36AM +0100, Richard Biener wrote: > > On Mon, Dec 19, 2022 at 9:12 AM Kewen.Lin wrote: > > > In function fold_convert_const_real_from_real, when the modes of > > > two types involved in fp conversio

Modula-2 / Rust: Many targets failing

2022-12-19 Thread Jan-Benedict Glaw
Hi! With the recent merges for Modula-2 and Rust, I see a good number of targets failing with --enable-languages=all, mostly due to issues with the Modula-2 driver. Modula-2 related issues = --target=x86_64-apple-darwin ~~ /bin/bash

Re: [PATCH RFA] build: add -Wconditionally-supported to strict_warn [PR64867]

2022-12-19 Thread Jason Merrill via Gcc-patches
On 12/16/22 19:52, Jeff Law wrote: On 12/6/22 06:26, Jason Merrill via Gcc-patches wrote: Tested x86_64-pc-linux-gnu, OK for trunk? -- 8< -- The PR (which isn't resolved by this commit) pointed out to me that GCC should build with -Wconditionally-supported to support bootstrapping with a C

[PATCH 2/2] nvptx: Prevent emitting duplicate declarations for '__nvptx_stacks', '__nvptx_uni'

2022-12-19 Thread Thomas Schwinge
As I have reported to Nvidia in 2022-12-01 'NVIDIA Incident Report (3891704): ptxas: Duplicate declaration error: "cannot be resolved by a '.static'"', 'ptxas' has an inscrutable error mode for duplicate declarations: ptxas softstack-decl-1.o, line 11; error : '.extern' variable '__nvptx_st

[PATCH 1/2] Add 'gcc.target/nvptx/softstack-decl-1.c', 'gcc.target/nvptx/uniform-simt-decl-1.c'

2022-12-19 Thread Thomas Schwinge
... to document the status quo re implicit (via 'need_softstack_decl', 'need_unisimt_decl') and explicit declarations of '__nvptx_stacks', '__nvptx_uni'. gcc/testsuite/ * gcc.target/nvptx/softstack-decl-1.c: New. * gcc.target/nvptx/uniform-simt-decl-1.c: Likewise. --- .../

Re: [PATCH] c++: NTTP object wrapper substitution fixes [PR103346, ...]

2022-12-19 Thread Jason Merrill via Gcc-patches
On 12/19/22 13:13, Patrick Palka wrote: On Mon, 19 Dec 2022, Jason Merrill wrote: On 12/6/22 13:35, Patrick Palka wrote: This patch fixes some issues with substitution into a C++20 template parameter object wrapper: * The first testcase demonstrates a situation where the same_type_p asser

Re: [PATCH v2 05/11] riscv: thead: Add support for the XTheadBa ISA extension

2022-12-19 Thread Philipp Tomsich
On Mon, 19 Dec 2022 at 05:20, Kito Cheng wrote: > > LGTM with a nit: > > ... > > + "TARGET_XTHEADBA > > + && (INTVAL (operands[2]) >= 0) && (INTVAL (operands[2]) <= 3)" > > IN_RANGE(INTVAL(operands[2]), 0, 3) > > and I am little bit suppress it can be zero So was I, when reading the specificat

Re: [PATCH] c++: NTTP object wrapper substitution fixes [PR103346, ...]

2022-12-19 Thread Patrick Palka via Gcc-patches
On Mon, 19 Dec 2022, Jason Merrill wrote: > On 12/6/22 13:35, Patrick Palka wrote: > > This patch fixes some issues with substitution into a C++20 template > > parameter object wrapper: > > > > * The first testcase demonstrates a situation where the same_type_p > >assert in relevant case of t

Re: [PATCH] c++: ICE with concepts TS multiple auto deduction [PR101886]

2022-12-19 Thread Jason Merrill via Gcc-patches
On 12/7/22 15:18, Patrick Palka wrote: In extract_autos_r, we need to reset TYPE_CANONICAL for the template type parameter after adjusting its index, otherwise we end up with a comptypes ICE for the below testcase. Note that such in-place type adjustment isn't generallly safe to do since the typ

Re: [PATCH] c++: NTTP object wrapper substitution fixes [PR103346, ...]

2022-12-19 Thread Jason Merrill via Gcc-patches
On 12/6/22 13:35, Patrick Palka wrote: This patch fixes some issues with substitution into a C++20 template parameter object wrapper: * The first testcase demonstrates a situation where the same_type_p assert in relevant case of tsubst_copy doesn't hold, because (partial) substitution of {

[PATCH] libgo: check if -lucontext is required for {make, set, get}context

2022-12-19 Thread soeren--- via Gcc-patches
From: Sören Tempel This patch is similar to the existing check for librt. If libucontext is installed and libucontext.a provides the aforementioned symbols, then it is added to $LIBS. If not, no error is emitted. We could, alternatively, also check libc.a for these symbols and thus prefer libc ov

Re: [PATCH V7] rs6000: Optimize cmp on rotated 16bits constant

2022-12-19 Thread Segher Boessenkool
Hi! Mostlt nitpicking left: On Mon, Dec 19, 2022 at 10:06:45PM +0800, Jiufu Guo wrote: > When checking eq/ne with a constant which has only 16bits, it can be > optimized to check the rotated data. By this, the constant building > is optimized. > > As the example in PR103743: > For "in == 0x8000

Re: [PATCH] i386: correct division modeling in lujiazui.md

2022-12-19 Thread Alexander Monakov via Gcc-patches
Ping. If there are any questions or concerns about the patch, please let me know: I'm interested in continuing this cleanup at least for older AMD models. I noticed I had an extra line in my Changelog: > (lua_sseicvt_si): Ditto. It got there accidentally and I will drop it. Alexander On

[PATCH] libatomic: Provide gthr.h default implementation

2022-12-19 Thread Sebastian Huber
Build libatomic for all targets. Use gthr.h to provide a default implementation. If the thread model is "single", then this implementation will not work if for example atomic operations are used for thread/interrupt synchronization. libatomic/ChangeLog: * Makefile.am (BUILT_SOURCES): Ne

Re: [PATCH] c++: NTTP object wrapper substitution fixes [PR103346, ...]

2022-12-19 Thread Patrick Palka via Gcc-patches
On Tue, 6 Dec 2022, Patrick Palka wrote: > On Tue, 6 Dec 2022, Patrick Palka wrote: > > > This patch fixes some issues with substitution into a C++20 template > > parameter object wrapper: > > > > * The first testcase demonstrates a situation where the same_type_p > > assert in relevant case o

Re: [PATCH] c++: ICE with concepts TS multiple auto deduction [PR101886]

2022-12-19 Thread Patrick Palka via Gcc-patches
On Wed, 7 Dec 2022, Patrick Palka wrote: > In extract_autos_r, we need to reset TYPE_CANONICAL for the template > type parameter after adjusting its index, otherwise we end up with a > comptypes ICE for the below testcase. Note that such in-place type > adjustment isn't generallly safe to do sinc

Re: [PATCH PING 2 (tree)] c++: source position of lambda captures [PR84471]

2022-12-19 Thread Jason Merrill via Gcc-patches
On 12/2/22 10:45, Jason Merrill wrote: Tested x86_64-pc-linux-gnu, OK for trunk? -- 8< -- If the DECL_VALUE_EXPR of a VAR_DECL has EXPR_LOCATION set, then any use of that variable looks like it has that location, which leads to the debugger jumping back and forth for both lambdas and structured

Re: [PATCH] c: Diagnose compound literals with function type [PR108043]

2022-12-19 Thread Marek Polacek via Gcc-patches
On Mon, Dec 19, 2022 at 12:05:48PM +0100, Jakub Jelinek wrote: > Hi! > > Both C99 and latest C2X say that compound literal shall have an object type > (complete object type in the latter case) or array of unknown bound, > so complit with function type is invalid. When the initializer had to be >

Re: [PATCH v2] coroutines: Accept 'extern "C"' coroutines.

2022-12-19 Thread Jason Merrill via Gcc-patches
On 12/17/22 08:40, Iain Sandoe wrote: Hi. It seems that everyone agrees that extern C coroutines should be permitted, although I have yet to see a useful testcase. This patch has been revised to append the suffices for such functions in mangle.cc rather than as part of the outlined function dec

Re: [PATCH] RISC-V: Support VSETVL PASS for RVV support

2022-12-19 Thread Jeff Law via Gcc-patches
I believe Kito already approved. There's nothing here that is critical, just minor cleanups and I'm fine with them being cleaned up as a follow-up patch given Kito has already approved this patch. On 12/14/22 00:13, juzhe.zh...@rivai.ai wrote: From: Ju-Zhe Zhong This patch is to support VSE

[PATCH] tree-optimization/108164 - undefined overflow with IV vectorization

2022-12-19 Thread Richard Biener via Gcc-patches
vect_update_ivs_after_vectorizer can end up emitting a signed IV update when the loop body performed an unsigned computation. The following makes sure to perform that update in the type of the loop update type to avoid undefined behavior on overflow. Bootstrapped and tested on x86_64-unknown-linux

Re: [PATCH] RISC-V: Simplify ASM checks 2

2022-12-19 Thread Kito Cheng via Gcc-patches
Merged into previou patch and commited 於 2022年12月19日 週一 19:13 寫道: > From: Ju-Zhe Zhong > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c: Simplify ASM > checks. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c: Ditto. > * gcc.target/r

Re: [PATCH] RISC-V: Simplify ASM checks.

2022-12-19 Thread Kito Cheng via Gcc-patches
Merged into previou patch and commited 於 2022年12月19日 週一 19:11 寫道: > From: Ju-Zhe Zhong > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c: Simplify ASM checks. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c: Ditto. > * gcc.target/riscv/rvv/vsetv

Re: [PATCH] RISC-V: Fix ASM checks.

2022-12-19 Thread Kito Cheng via Gcc-patches
Merged into previou patch and commited 於 2022年12月19日 週一 18:55 寫道: > From: Ju-Zhe Zhong > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c: Fix asm check. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c: Ditto. > * gcc.target/riscv/rvv

Re: [PATCH] RISC-V: Support VSETVL PASS for RVV support

2022-12-19 Thread Kito Cheng via Gcc-patches
LGTM, and thanks for this amazing work, actually I review this more than one month, so I gonna commit this for now. But feel free to keep helping review that, give comment and report bug to Ju-Zhe and me :) 於 2022年12月14日 週三 15:32 寫道: > From: Ju-Zhe Zhong > > This patch is to support VSETVL P

Re: [PATCH] RISC-V: Add testcases for VSETVL PASS 4

2022-12-19 Thread Kito Cheng via Gcc-patches
Commited to trunk 於 2022年12月14日 週三 16:20 寫道: > From: Ju-Zhe Zhong > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c:

Re: [PATCH] RISC-V: Add testcases for VSETVL PASS 3

2022-12-19 Thread Kito Cheng via Gcc-patches
Commited to trunk 於 2022年12月14日 週三 16:16 寫道: > From: Ju-Zhe Zhong > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_mis

Re: [PATCH] RISC-V: Add testcases for VSETVL PASS 5

2022-12-19 Thread Kito Cheng via Gcc-patches
Commited to trunk 於 2022年12月14日 週三 16:27 寫道: > From: Ju-Zhe Zhong > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-1.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-10.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop

Re: [PATCH] RISC-V: Add testcases for VSETVL PASS 2

2022-12-19 Thread Kito Cheng via Gcc-patches
Commited to trunk 於 2022年12月14日 週三 16:13 寫道: > From: Ju-Zhe Zhong > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c: New test. >

Re: [PATCH] RISC-V: Add VSETVL PASS VLMAX testcases.

2022-12-19 Thread Kito Cheng via Gcc-patches
Commited to trunk 於 2022年12月14日 週三 15:46 寫道: > From: Ju-Zhe Zhong > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/rvv.exp: Adjust to enable tests for VSETVL > PASS. > * gcc.target/riscv/rvv/vsetvl/dump-1.c: New test. > * gcc.target/riscv/rvv/vsetvl/vlmax_back_pro

Re: [PATCH] RISC-V: Change vlmul printing rule

2022-12-19 Thread Kito Cheng via Gcc-patches
Commited Jeff Law via Gcc-patches 於 2022年12月17日 週六 03:51 寫道: > > > On 12/13/22 23:57, juzhe.zh...@rivai.ai wrote: > > From: Ju-Zhe Zhong > > > > This patch is preparing patch for the following patch (VSETVL PASS) > > support since the current vlmul printing rule is not appropriate > > informati

Re: [PATCH] RISC-V: Fix annotation

2022-12-19 Thread Kito Cheng via Gcc-patches
Merged into previou patch. Jeff Law via Gcc-patches 於 2022年12月17日 週六 03:54 寫道: > > > On 12/14/22 01:39, juzhe.zh...@rivai.ai wrote: > > From: Ju-Zhe Zhong > > > > gcc/ChangeLog: > > > > * config/riscv/riscv-vsetvl.cc: Fix annotation. > Just roll this into the patch that adds riscv-vset

Re: [PATCH] RISC-V: Remove unused redundant vector attributes

2022-12-19 Thread Kito Cheng via Gcc-patches
Commited Jeff Law via Gcc-patches 於 2022年12月17日 週六 03:55 寫道: > > > On 12/14/22 01:51, juzhe.zh...@rivai.ai wrote: > > From: Ju-Zhe Zhong > > > > I found that I forgot to remove these redundant attributes. > > Sorry about that. > > > > gcc/ChangeLog: > > > > * config/riscv/vector.md ():

Re: Re: [PATCH] RISC-V: Remove unit-stride store from ta attribute

2022-12-19 Thread Kito Cheng via Gcc-patches
Commited to trunk, thanks:) 钟居哲 於 2022年12月17日 週六 09:22 寫道: > Yes, the vector stores doesn't care about policy no matter mask or tail. > Removing it can allow VSETVL PASS have more optimization chances > since VSETVL PASS has backward demands fusion. > > For example: > vadd tama > vse.v > VSETVL

[committed] arm: correctly define __ARM_FEATURE_CLZ

2022-12-19 Thread Richard Earnshaw via Gcc-patches
The ACLE requires that __ARM_FEATURE_CLZ be defined if the hardware supports it; it's also clear that this doesn't mean the current ISA, so we must define this even when compiling for Thumb1 if the target supports CLZ in A32. This brings GCC into alignment with Clang. gcc/ChangeLog: * c

Re: Re: [PATCH] RISC-V: Fix RVV machine mode attribute configuration

2022-12-19 Thread Kito Cheng via Gcc-patches
Commited to trunk. 钟居哲 於 2022年12月17日 週六 09:52 寫道: > Actually, I don't check and test HF carefully since I disable them. > Kito ask me to disable all HF modes since zvfhmin is no ratified and GCC > doesn't allow any un-ratified ISA. You can see vector-iterator.md that all > RVV modes supported in

[PATCH] PR tree-optimization/108139 - Don't use PHI equivalences in range-on-entry.

2022-12-19 Thread Andrew MacLeod via Gcc-patches
our use of equivalences on range-on-entry calculations cause an issue through a PHI node when a back edge is involved.  ie    a = VARYING    <...> bb5    b = PHI bb6    if (a != 0)      goto bb5 since the value of b is undefined on the edge 2->5, we ignore it. The range of a on the edge 6->5 i

Re: [PATCH V6] rs6000: Optimize cmp on rotated 16bits constant

2022-12-19 Thread Jiufu Guo via Gcc-patches
Hi, Segher Boessenkool writes: > On Wed, Dec 14, 2022 at 04:26:54PM +0800, Jiufu Guo wrote: >> Segher Boessenkool writes: >> > On Mon, Aug 29, 2022 at 11:42:16AM +0800, Jiufu Guo wrote: >> >> li %r9,-1 >> >> rldicr %r9,%r9,0,0 >> >> cmpd %cr0,%r3,%r9 >> > >> > FWIW, I fi

[PATCH V7] rs6000: Optimize cmp on rotated 16bits constant

2022-12-19 Thread Jiufu Guo via Gcc-patches
Hi, When checking eq/ne with a constant which has only 16bits, it can be optimized to check the rotated data. By this, the constant building is optimized. As the example in PR103743: For "in == 0x8000LL", this patch generates: rotldi 3,3,1 ; cmpldi 0,3,1 instead of: l

[committed] testsuite: Fix up pr64536.c for LLP64 targets [PR108151]

2022-12-19 Thread Jakub Jelinek via Gcc-patches
Hi! Apparently llp64 had 2 further warnings, fixed thusly. Committed as obvious after testing it with cross to mingw. 2022-12-19 Jakub Jelinek PR testsuite/108151 * gcc.dg/pr64536.c (bar): Cast long to __INTPTR_TYPE__ before casting to long *. --- gcc/testsuite/gcc.d

Re: [PATCH v2 06/11] riscv: thead: Add support for the XTheadBs ISA extension

2022-12-19 Thread Kito Cheng via Gcc-patches
LGTM On Mon, Dec 19, 2022 at 9:12 AM Christoph Muellner wrote: > > From: Christoph Müllner > > This patch adds support for the XTheadBs ISA extension. > The new INSN pattern is defined in a new file to separate > this vendor extension from the standard extensions. > The cost model adjustment reu

[PATCH (pushed)] gcc-changelog: support digits in PR's component in subject

2022-12-19 Thread Martin Liška
Yes, fixed in the following patch. Martin contrib/ChangeLog: * gcc-changelog/git_commit.py: Support digits in PR's component in subject. --- contrib/gcc-changelog/git_commit.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/contrib/gcc-changelog/git_commit.

Re: [PATCH (pushed)] gcc-changelog: allow digit in component name

2022-12-19 Thread Jakub Jelinek via Gcc-patches
On Mon, Dec 19, 2022 at 02:40:29PM +0100, Martin Liška wrote: > contrib/ChangeLog: > > * gcc-changelog/git_commit.py: Allow digit in component name. > > contrib/ChangeLog: > > * gcc-changelog/test_email.py: Add new test. > * gcc-changelog/test_patches.txt: Add new patch. > ---

[PATCH (pushed)] gcc-changelog: allow digit in component name

2022-12-19 Thread Martin Liška
contrib/ChangeLog: * gcc-changelog/git_commit.py: Allow digit in component name. contrib/ChangeLog: * gcc-changelog/test_email.py: Add new test. * gcc-changelog/test_patches.txt: Add new patch. --- contrib/gcc-changelog/git_commit.py| 2 +- contrib/gcc-changelog/te

Re: [PATCH] modula2: Don't treat % in Modula 2 messages specially

2022-12-19 Thread Gaius Mulley via Gcc-patches
Jakub Jelinek writes: > Hi! > > On top of the just posted patch, this patch makes sure that > any % chars in message strings aren't treated as format chars. > None of these functions take variable number of arguments, so for > most of format specifiers there is nowhere to take arguments from, > i

Re: [PATCH v2 05/11] riscv: thead: Add support for the XTheadBa ISA extension

2022-12-19 Thread Kito Cheng via Gcc-patches
LGTM with a nit: ... > + "TARGET_XTHEADBA > + && (INTVAL (operands[2]) >= 0) && (INTVAL (operands[2]) <= 3)" IN_RANGE(INTVAL(operands[2]), 0, 3) and I am little bit suppress it can be zero > + "th.addsl\t%0,%1,%3,%2" > + [(set_attr "type" "bitmanip") > + (set_attr "mode" "")])

Re: [PATCH] modula2: Fix up bootstrap on powerpc64le-linux [PR108147]

2022-12-19 Thread Gaius Mulley via Gcc-patches
Jakub Jelinek writes: > Hi! > > As mentioned in the PR, bootstrap with m2 enabled currently fails > on powerpc64le-linux, we get weird ICE after printing some diagnostics. > The problem is that mc creates from *.def prototypes like > extern void m2linemap_WarningAtf (m2linemap_location_t location

[committed] testsuite: Fix up pr64536.c for LLP64 targets [PR108151]

2022-12-19 Thread Jakub Jelinek via Gcc-patches
Hi! The test casts a pointer to long, which is ok for ilp32 and lp64 targets but not for llp64 targets. Nothing reads the values later, it is a link test, so all we care about is that it is the same cast on s390x-linux where it used to fail before the PR64536 fix, and that we don't warn about it.

Re: [PATCH, nvptx, 1/2] Reimplement libgomp barriers for nvptx

2022-12-19 Thread Thomas Schwinge
Hi! On 2022-12-16T15:51:35+0100, Tom de Vries via Gcc-patches wrote: > On 9/21/22 09:45, Chung-Lin Tang wrote: >> I had a patch submitted earlier, where I reported that the current way >> of implementing >> barriers in libgomp on nvptx created a quite significant performance >> drop on some SPEC

Re: [Patch] nvptx/mkoffload.cc: Add dummy proc for OpenMP rev-offload table [PR108098]

2022-12-19 Thread Thomas Schwinge
Hi! On 2022-12-16T17:19:00+0100, Tobias Burnus wrote: > Seems to be a CUDA JIT issue A Nvidia Driver JIT issue, more precisely. ;-) > which is fixed by adding a dummy procedure. Gah... :-| > Lightly tested with 4 systems at hand, where 2 failed before. I'm happy to confirm that indeed this

[PATCH] modula2: Don't treat % in Modula 2 messages specially

2022-12-19 Thread Jakub Jelinek via Gcc-patches
Hi! On top of the just posted patch, this patch makes sure that any % chars in message strings aren't treated as format chars. None of these functions take variable number of arguments, so for most of format specifiers there is nowhere to take arguments from, it is true that a couple of format spe

[PATCH][committed] aarch64: PR target/108140 Handle NULL target in data intrinsic expansion

2022-12-19 Thread Kyrylo Tkachov via Gcc-patches
Hi all, In this PR we ICE when expanding the __rbit builtin with a NULL target rtx. I *think* that only happens when the result is unused and hence maybe we shouldn't be expanding any RTL at all, but the ICE here is easily fixed by deriving the mode from the type of the expression rather than th

[PATCH] RISC-V: Simplify ASM checks.

2022-12-19 Thread juzhe . zhong
From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c: Simplify ASM checks. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c: Di

[PATCH] modula2: Fix up bootstrap on powerpc64le-linux [PR108147]

2022-12-19 Thread Jakub Jelinek via Gcc-patches
Hi! As mentioned in the PR, bootstrap with m2 enabled currently fails on powerpc64le-linux, we get weird ICE after printing some diagnostics. The problem is that mc creates from *.def prototypes like extern void m2linemap_WarningAtf (m2linemap_location_t location, void * message); but the actual

[PATCH] c: Diagnose compound literals with function type [PR108043]

2022-12-19 Thread Jakub Jelinek via Gcc-patches
Hi! Both C99 and latest C2X say that compound literal shall have an object type (complete object type in the latter case) or array of unknown bound, so complit with function type is invalid. When the initializer had to be non-empty for such case, we used to diagnose it as incorrect initializer, b

Re: [Patch] gfortran.dg/read_dir.f90: Make PASS on Windows

2022-12-19 Thread Tobias Burnus
On 19.12.22 10:26, Tobias Burnus wrote: And here is a more light-wight variant, suggested by Nightstrike: Using '.' instead of creating a new directory - and checking for __WIN32__ instead for __MINGW32__. The only downside of this variant is that it does not check whether "close(10,status='del

Re: [PATCH] fold-const: Treat fp conversion to a type with same mode as copy

2022-12-19 Thread Jakub Jelinek via Gcc-patches
On Mon, Dec 19, 2022 at 09:49:36AM +0100, Richard Biener wrote: > On Mon, Dec 19, 2022 at 9:12 AM Kewen.Lin wrote: > > In function fold_convert_const_real_from_real, when the modes of > > two types involved in fp conversion are the same, we can simply > > take it as copy, rebuild with the exactly

[Patch] gfortran.dg/read_dir.f90: Make PASS on Windows

2022-12-19 Thread Tobias Burnus
As discussed in #gfortran IRC, on Windows opening a directory fails with EACCESS. (It works under Cygwin - nightstrike was so kind to test this.) Additionally, '[ -d dir ] || mkdir dir' is also not very portable. Hence, I use an auxiliary C file calling the POSIX functions and expect a fail for

Re: [PATCH] fold-const: Treat fp conversion to a type with same mode as copy

2022-12-19 Thread Kewen.Lin via Gcc-patches
Hi Richi, Thanks for the comments! on 2022/12/19 16:49, Richard Biener wrote: > On Mon, Dec 19, 2022 at 9:12 AM Kewen.Lin wrote: >> >> Hi, >> >> In function fold_convert_const_real_from_real, when the modes of >> two types involved in fp conversion are the same, we can simply >> take it as copy,

[PATCH (pushed)] gcc-changelog: stop using --flake8

2022-12-19 Thread Martin Liška
The flake8 pytest plug-in is broken and we should not use it. contrib/ChangeLog: * gcc-changelog/setup.cfg: Do not use flake8 pytest plug-in. --- contrib/gcc-changelog/setup.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/contrib/gcc-changelog/setup.cfg b/contrib

Ping^2: [PATCH] jit: Install jit headers in $(libsubincludedir) [PR 101491]

2022-12-19 Thread Lorenzo Salvadore via Gcc-patches
Hello, Ping https://gcc.gnu.org/pipermail/gcc-patches/2022-November/606450.html Thanks, Lorenzo Salvadore > From f8e2c2ee89a7d8741bb65163d1f1c20edcd546ac Mon Sep 17 00:00:00 2001 > From: Lorenzo Salvadore develo...@lorenzosalvadore.it > > Date: Wed, 16 Nov 2022 11:27:38 +0100 > Subject: [PATCH

Re: [PATCH v2 02/11] riscv: Restructure callee-saved register save/restore code

2022-12-19 Thread Christoph Müllner
On Mon, Dec 19, 2022 at 7:30 AM Kito Cheng wrote: > just one more nit: Use INVALID_REGNUM as sentinel value for > riscv_next_saved_reg, otherwise LGTM, and feel free to commit that > separately :) > Would this change below be ok? @@ -5540,7 +5540,7 @@ riscv_next_saved_reg (unsigned int regno, u

[committed] testsuite: Fix up pr107397.f90 test [PR107397]

2022-12-19 Thread Jakub Jelinek via Gcc-patches
On Sat, Dec 17, 2022 at 09:12:43AM -0800, Jerry D via Gcc-patches wrote: > The attached patch fixes a regression and is a patch from Steve. I have > regression tested it and provided a test case. It is fairly simple and I > will commit under the "simple" rule in a little while. > > Thanks Steve

Re: [PATCH v2 02/11] riscv: Restructure callee-saved register save/restore code

2022-12-19 Thread Christoph Müllner
On Mon, Dec 19, 2022 at 10:26 AM Kito Cheng wrote: > Something like this: > > static unsigned int > riscv_next_saved_reg (unsigned int regno, unsigned int limit, > HOST_WIDE_INT *offset, bool inc = true) > { > if (inc) > regno++; > > while (regno <= limit) > { >

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2022-12-19 Thread Smart Marketting via Gcc-patches
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Re: [Patch] gfortran.dg/read_dir.f90: Make PASS on Windows

2022-12-19 Thread Tobias Burnus
And here is a more light-wight variant, suggested by Nightstrike: Using '.' instead of creating a new directory - and checking for __WIN32__ instead for __MINGW32__. The only downside of this variant is that it does not check whether "close(10,status='delete')" will delete a directory without fa

Re: [PATCH V4 1/2] rs6000: use li;x?oris to build constant

2022-12-19 Thread Jiufu Guo via Gcc-patches
Hi, Segher Boessenkool writes: > Hi! > > On Mon, Dec 12, 2022 at 09:38:28AM +0800, Jiufu Guo wrote: >> PR target/106708 >> >> gcc/ChangeLog: >> >> * config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Add using >> "li; x?oris" to build constant. >> >> gcc/testsuite/ChangeLog:

Re: [PATCH] fold-const: Treat fp conversion to a type with same mode as copy

2022-12-19 Thread Richard Biener via Gcc-patches
On Mon, Dec 19, 2022 at 9:12 AM Kewen.Lin wrote: > > Hi, > > In function fold_convert_const_real_from_real, when the modes of > two types involved in fp conversion are the same, we can simply > take it as copy, rebuild with the exactly same TREE_REAL_CST and > the target type. It is more efficien

Re: [PATCH v2 02/11] riscv: Restructure callee-saved register save/restore code

2022-12-19 Thread Kito Cheng
Something like this: static unsigned int riscv_next_saved_reg (unsigned int regno, unsigned int limit, HOST_WIDE_INT *offset, bool inc = true) { if (inc) regno++; while (regno <= limit) { if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))

Re: [PATCH v2 03/11] riscv: Add basic XThead* vendor extension support

2022-12-19 Thread Kito Cheng
> + {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0}, > + {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0}, > + {"xtheadbs", ISA_SPEC_CLASS_NONE, 1, 0}, > + {"xtheadcmo", ISA_SPEC_CLASS_NONE, 1, 0}, > + {"xtheadcondmov", ISA_SPEC_CLASS_NONE, 1, 0}, > + {"xtheadfmemidx", ISA_SPEC_CLASS_NONE, 1, 0}, > + {"xthea

[PATCH] fold-const: Treat fp conversion to a type with same mode as copy

2022-12-19 Thread Kewen.Lin via Gcc-patches
Hi, In function fold_convert_const_real_from_real, when the modes of two types involved in fp conversion are the same, we can simply take it as copy, rebuild with the exactly same TREE_REAL_CST and the target type. It is more efficient and helps to avoid possible unexpected signalling bit clearin

Re: [PATCH] RISC-V: Fix RVV mask mode size

2022-12-19 Thread Richard Biener via Gcc-patches
On Sat, Dec 17, 2022 at 2:54 AM Jeff Law via Gcc-patches wrote: > > > > On 12/16/22 18:44, 钟居哲 wrote: > > Yes, VNx4DF only has 4 bit in mask mode in case of load and store. > > For example vlm or vsm we will load store 8-bit ??? (I am not sure > > hardward can load store 4bit,but I am sure it defi

Re: [PATCH v2 02/11] riscv: Restructure callee-saved register save/restore code

2022-12-19 Thread Kito Cheng
just one more nit: Use INVALID_REGNUM as sentinel value for riscv_next_saved_reg, otherwise LGTM, and feel free to commit that separately :) On Mon, Dec 19, 2022 at 9:08 AM Christoph Muellner wrote: > > From: Christoph Müllner > > This patch restructures the loop over the GP registers > which sa

[PATCH v6, rs6000] Change mode and insn condition for VSX scalar extract/insert instructions

2022-12-19 Thread HAO CHEN GUI via Gcc-patches
Hi, This patch fixes several problems: 1. The exponent of double-precision can be put into a SImode register. So "xsxexpdp" doesn't require 64-bit environment. Also "xsxsigdp", "xsiexpdp" and "xsiexpdpf" can put exponent into a GPR register. 2. "TARGET_64BIT" check in insn cond

Re: [PATCH v2 04/11] riscv: riscv-cores.def: Add T-Head XuanTie C906

2022-12-19 Thread Kito Cheng
LGTM On Mon, Dec 19, 2022 at 9:08 AM Christoph Muellner wrote: > > From: Christoph Müllner > > This adds T-Head's XuanTie C906 to the list of known cores as "thead-c906". > The C906 is shipped for quite some time (it is the core of the Allwinner D1). > Note, that the tuning struct for the C906 i

[RFC/RFT 2/3] [PR102768] Support CFI: Add new pass for Control Flow Integrity

2022-12-19 Thread Dan Li via Gcc-patches
The CFI sanitizer enabled with -fsanitize=cfi implements a forward edge control flow integrity scheme for indirect calls, roughly similar to -fsanitize=kcfi [1] in llvm. At compile time, it appends a uniform type identifier before the first instruction of each function and inserts check code befor

[RFC/RFT 1/3] [PR102768] flag-types.h (enum sanitize_code): Extend sanitize_code to 64 bits to support more features

2022-12-19 Thread Dan Li via Gcc-patches
32-bit sanitize_code can no longer accommodate new options, extending it to 64-bit. Signed-off-by: Dan Li gcc/ChangeLog: PR c/102768 * asan.h (sanitize_flags_p): Promote to uint64_t. * common.opt: Likewise. * dwarf2asm.cc (dw2_output_indirect_constant_1): Likewis

Re: [PATCH] rs6000: Fix some issues related to Power10 fusion [PR104024]

2022-12-19 Thread Kewen.Lin via Gcc-patches
Hi Segher, Thanks for the review comments! on 2022/12/15 06:29, Segher Boessenkool wrote: > On Wed, Nov 30, 2022 at 04:30:13PM +0800, Kewen.Lin wrote: >> As PR104024 shows, the option -mpower10-fusion isn't guarded by >> -mcpu=power10, it causes compiler to fuse for some patterns >> even without

[RFC/RFT 3/3] [PR102768] aarch64: Add support for Control Flow Integrity

2022-12-19 Thread Dan Li via Gcc-patches
In the AArch64 platform, typeid can be directly inserted in front of the function header (offset is -4). For all functions that will not be called indirectly, insert the reserved RESERVED_CFI_TYPEID (0x0) as typeid in front of them. If not, the attacker may use the instruction/data before the func