Commited to trunk. 钟居哲 <juzhe.zh...@rivai.ai> 於 2022年12月17日 週六 09:52 寫道：
> Actually, I don't check and test HF carefully since I disable them. > Kito ask me to disable all HF modes since zvfhmin is no ratified and GCC > doesn't allow any un-ratified ISA. You can see vector-iterator.md that all > RVV modes supported including QI HI SI DI SF DF excluding HF and BF. > > > > juzhe.zh...@rivai.ai > > From: Jeff Law > Date: 2022-12-17 09:48 > To: juzhe.zhong; gcc-patches > CC: kito.cheng; palmer > Subject: Re: [PATCH] RISC-V: Fix RVV machine mode attribute configuration > > > On 12/14/22 00:01, juzhe.zh...@rivai.ai wrote: > > From: Ju-Zhe Zhong <juzhe.zh...@rivai.ai> > > > > The attribute configuration of each machine mode are support in the > previous patch. > > I noticed some of them are not correct during VSETVL PASS testsing. > > Correct them in the single patch now. > > > > gcc/ChangeLog: > > > > * config/riscv/riscv-vector-switch.def (ENTRY): Correct > attributes. > > > > > > > @@ -121,7 +121,7 @@ ENTRY (VNx2HI, true, LMUL_1, 16, LMUL_F2, 32) > > ENTRY (VNx1HI, true, LMUL_F2, 32, LMUL_F4, 64) > > > > /* TODO:Disable all FP16 vector, enable them when 'zvfh' is > supported. */ > > -ENTRY (VNx32HF, false, LMUL_8, 2, LMUL_RESERVED, 0) > > +ENTRY (VNx32HF, false, LMUL_RESERVED, 0, LMUL_8, 2) > Is there any value in making VNx32HF dependent on TARGET_MIN_VLEN > 32 > like we're doing for VNx32HI? In the past I've found it useful to have > HI, HF, BF behave identically as much as possible. > > You call. The patch is OK either way. > > jeff > > > > >
