On Sat, Dec 17, 2022 at 2:54 AM Jeff Law via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > > > On 12/16/22 18:44, 钟居哲 wrote: > > Yes, VNx4DF only has 4 bit in mask mode in case of load and store. > > For example vlm or vsm we will load store 8-bit ??? (I am not sure > > hardward can load store 4bit,but I am sure it definetly not load store > > the whole register size) > Most likely than not you end up loading a larger quantity with the high > bits zero'd. Interesting that we're using a packed model. I'd been > told it was fairly expensive to implement in hardware relative to teh > cost of implementing the sparse model.
Since the masks are extra inputs if you use a packed model you need to wire less bits into the execution units for the masks which I guess is actually cheaper. Yes, producing the masks might be more complicated. > > So ideally it should be model more accurate. However, since GCC assumes > > that 1 BOOL is 1-byte, the only thing I do is to model mask mode as > > smallest as possible. > > Maybe in the future, I can support 1BOOL for 1-bit?? I am not sure since > > it will need to change GCC framework. > I'm a bit confused by this. GCC can support single bit bools, though > ports often extend them to 8 bits or more for computational efficiency > purposes. At least that's the case in general. Is there something > particularly special about masks & bools that's causing problems? The only "issue" might be with 4, 2 and 1 bit masks which would have a size of 8 bits but a precision of less that endianess might play a role. Btw, this is all similar to AVX512 where we even don't use vector BI modes but integer modes for the mask which then becomes QImode for 1, 2, 4 and 8 bit masks and HImode for 16, SImode for 32 and DImode for 64 bit masks. Richard. > Jeff
