On 09/26/2017 02:26 PM, Rainer Orth wrote:
> Hi Andreas,
>
>> diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
>> index 307c726..3acfd85 100644
>> --- a/gcc/doc/sourcebuild.texi
>> +++ b/gcc/doc/sourcebuild.texi
>> @@ -1398,6 +1398,9 @@ Target supports a vector misalign access.
>>
On Tue, Sep 26, 2017 at 10:56 PM, Yuri Gribov wrote:
> Hi all,
>
> This patch fixes a trivial ICE in recent pattern. Bootstrapped and
> regtested on x86_64.
>
> Ok to commit?
>+ bool cst_int_p = ! real_isnan (cst) && real_identical (&icst, cst);
The GCC coding style says no space between the !
Hi all,
This patch fixes a trivial ICE in recent pattern. Bootstrapped and
regtested on x86_64.
Ok to commit?
-Y
pr82319-1.patch
Description: Binary data
On 09/26/2017 07:47 AM, Tsimbalist, Igor V wrote:
Here is a new version of the patch.
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index a374890..a900ed1 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -5655,6 +5655,13 @@ compiled with the @option{-fcf-protection=branch}
On 09/26/2017 07:45 AM, Tsimbalist, Igor V wrote:
Here is the updated version (version#3). All comments below are fixed.
This still needs more work. Specific comments below:
+The @code{nocf_check} attribute is applied to an object's type.
+In case of assignment of a function address or a fun
On 25 September 2017 at 17:24, Jan Hubicka wrote:
>> Hi Honza,
>> Could you please have a look at this patch ?
>> https://gcc.gnu.org/ml/gcc-patches/2017-07/msg02063.html
>
> I can and I should have done long time ago. I really apologize for slow
> response
> and I will try to be more timely from
On Tue, Sep 26, 2017 at 04:56:54PM -0500, Segher Boessenkool wrote:
> On Tue, Sep 26, 2017 at 10:48:29AM -0400, Michael Meissner wrote:
> > * config/rs6000/vsx.md (peephole for optimizing move SF to GPR):
> > Adjust code to eliminate needing to do the shift right 32-bits
> > operation a
I have committed the attached patch to fix PR 39570.
The problem is that the NetBSD cabs/cabsf/cabsl funcions are called
__c99_cabs etc. as NetBSD needed to change the ABI before it had symbol
versioning. This is handled in the system header file as
double cabs(double _Complex) __asm("__c99
On Tue, Sep 26, 2017 at 10:48:29AM -0400, Michael Meissner wrote:
> * config/rs6000/vsx.md (peephole for optimizing move SF to GPR):
> Adjust code to eliminate needing to do the shift right 32-bits
> operation after XSCVDPSPN.
After staring at this way too long... Looks correct.
There are a few places where the C++ FE will complain when attempting
to do things within an extern "C" linkage specifier.
I've run into problems where it wasn't clear where the pertinent
extern "C" was; for example, when failing to close an extern "C" linkage
specifier in a header, leading to "te
On 26 September 2017 12:57:37 CEST, Segher Boessenkool
wrote:
>> --- gcc/testsuite/gcc.target/powerpc/swps-p8-36.c(revision 0)
>> +++ gcc/testsuite/gcc.target/powerpc/swps-p8-36.c(working copy)
>> @@ -0,0 +1,31 @@
>> +/* This file's name was changed from swaps-p8-36.c so that the
>> +
On Mon, Sep 25, 2017 at 11:13:57AM +0100, Sudi Das wrote:
>
> Hi James
>
> I put aarch64_output_simd_general_immediate looking at the similarities of
> the immediates for mov/mvni and orr/bic. The CHECK macro in
> aarch64_simd_valid_immediate both checks
> and converts the immediates in a manner
* Claudiu Zissulescu [2017-09-01 14:32:10
+0200]:
> From: claziss
>
> Hi Andrew,
>
> By mistake I've pushed an incoplete ZOL-rework patch, and it missing the
> attached parts. Please can you check if it is ok?
>
> Thank you,
> Claudiu
>
> gcc/
> 2017-09-01 Claudiu Zissulescu
>
>
On Wed, Mar 14, 2012 at 07:02:33PM +0100, Rainer Orth wrote:
> Richard Henderson writes:
>
> > On 03/14/12 09:09, Rainer Orth wrote:
> >
> > Nearly ok.
> >
> >> + targetm.asm_file_start_file_directive = 0;
> >
> > This is default and may be deleted.
>
> Or would be if alpha.c didn't override th
Hello world,
I have committed the attached patch as obvious after regression-testing.
It removes the wrong warning from my recend DO warning patch that Jakub
pointed out. The test case that is restored with this patch is enough
to catch any regression.
Regards
Thomas
2017-09-26 Thom
On Tue, Sep 26, 2017 at 11:36:14AM -0500, Segher Boessenkool wrote:
> Hi!
>
> On Tue, Sep 26, 2017 at 10:34:44AM -0400, Michael Meissner wrote:
> > * config/rs6000/rs6000.md (movsi_from_df): Optimize converting a
> > DFmode to a SFmode, and then needing to move the SFmode to a GPR
> >
Similar to other architectures with IFUNC binutils/glibc support, this
patch enables the ifunc attribute for SPARC GNU/Linux. This is needed
for building glibc with the current checks on IFUNC resolver types
(and use of the attribute in glibc rather than manually created IFUNCs
is beneficial anywa
On Tue, Sep 26, 2017 at 11:06:09AM -0500, Segher Boessenkool wrote:
> > @@ -6850,52 +6850,41 @@ (define_insn_and_split "movsi_from_sf"
> >rtx op1 = operands[1];
> >rtx op2 = operands[2];
> >rtx op0_di = gen_rtx_REG (DImode, REGNO (op0));
> > + rtx op2_si = gen_rtx_REG (SImode, REGNO (o
On Tue, Sep 26, 2017 at 10:50:14AM -0400, Michael Meissner wrote:
> * gcc.target/powerpc/pr71977-1.c: Update test to know that we
> don't generate a 32-bit shift after doing XSCVDPSPN.
> * gcc.target/powerpc/direct-move-float1.c: Likewise.
> * gcc.target/powerpc/direct-move-
On Tue, Sep 26, 2017 at 10:44:24AM -0400, Michael Meissner wrote:
> * config/rs6000/vsx.md (vsx_xscvdpspn): Eliminate useless
> alternative constraint.
> (vsx_xscvspdpn): Likewise.
> (vsx_xscvspdpn_scalar): Likewise.
Okay, nice cleanup! Thanks,
Segher
Hi!
On Tue, Sep 26, 2017 at 10:39:06AM -0400, Michael Meissner wrote:
> * config/rs6000/vsx.md (vsx_xscvdpsp_scalar): Use "ww" constraint
> instead of "f" to allow SFmode to be in traditional Altivec
> registers.
Okay. Thanks,
Segher
On Tue, Sep 26, 2017 at 10:36:34AM -0400, Michael Meissner wrote:
> * config/rs6000/vsx.md (vsx_xscvspdp_scalar2): Move insn so that
> it is adjacent to the other XSCVSPDP insns.
Okay for trunk. Thanks,
Segher
Hi Jakub,
associate(k => v, l => a(i, j), m => a(i, :))
And I don't really see a bug in the testcase...
Hm, I will look at this. Maybe some strange
interaction with associate here...
Regards
Thomas
Ping^2.
On Friday, September 15 2017, I wrote:
> Ping.
>
> On Friday, September 01 2017, I wrote:
>
>> On Wednesday, August 23 2017, Pedro Alves wrote:
>>
>>> On 08/23/2017 05:17 AM, Sergio Durigan Junior wrote:
Hi there,
This is a series of two patches, one for GDB and one for GC
Hi!
On Mon, 25 Sep 2017 18:50:49 +0200, Thomas Koenig wrote:
Thanks for the review, committed as r253156.
Now, on to some other bugs...
No, back to this one please. ;-)
OK, if you insist :-)
Apparently, the changes you prepared for existing testcases did not get
committed, so I'm now s
On Sep 25, 2017, at 9:58 PM, Christophe Lyon wrote:
>
> Yes, thanks! I was missing the 'expr' part.
>
> Here is what I have committed (r253187), to avoid further noise in the
> results.
Yup, looks good. Thanks.
Andreas Krebbel writes:
> - vect_nopeel renamed to vect_no_peel
> - documentation added.
>
> gcc/testsuite/ChangeLog:
>
> 2017-09-26 Andreas Krebbel
>
> * doc/sourcebuild.texi: Document vect_no_peel.
>
> gcc/testsuite/ChangeLog:
>
> 2017-09-26 Andreas Krebbel
>
> * g++.dg/vect/sl
Hi!
On Tue, Sep 26, 2017 at 10:34:44AM -0400, Michael Meissner wrote:
> * config/rs6000/rs6000.md (movsi_from_df): Optimize converting a
> DFmode to a SFmode, and then needing to move the SFmode to a GPR
> to use the XSCVDPSP instruction instead of FRSP and XSCVDPSPN.
> --- gcc/
Hi,
On Tue, Sep 26, 2017 at 10:32:03AM -0400, Michael Meissner wrote:
> * config/rs6000/rs6000.md (movsi_from_sf): Adjust code to
> eliminate doing a 32-bit shift right or vector extract after doing
> XSCVDPSPN. Use zero_extendsidi2 instead of p8_mfvsrd_4_disf to
> move th
On Sep 26, 2017, at 5:57 AM, Segher Boessenkool
wrote:
>
>> +/* { dg-final { scan-assembler-not "swap" } } */
>
> So what is this really testing for? xxswapd? But a) we never generate
> that, and b) you could use a better regex?
Agreed, this looks like an unnecessary test for now. Changing
On September 26, 2017 5:20:25 PM GMT+02:00, Martin Jambor
wrote:
>Hi,
>
>On Mon, Sep 25, 2017 at 04:22:06PM +0300, Alexander Monakov wrote:
>>
>> Thanks! If this is resolved, haifa-sched autoprefetch ranking will
>become the
>> last remaining (among discovered so far) inconsistent qsort
>compar
Hi,
On Mon, Sep 25, 2017 at 04:22:06PM +0300, Alexander Monakov wrote:
>
> Thanks! If this is resolved, haifa-sched autoprefetch ranking will become the
> last remaining (among discovered so far) inconsistent qsort comparator in GCC.
>
So the following has passed bootstrap and testing on x86_6
Hi,
I would like to ping the below patch posted on 14th of august.
Thank you!
Sebastian
-Original Message-
From: Sebastian Perta
Sent: 14 August 2017 15:26
To: 'gcc-patches@gcc.gnu.org'
Subject: [PATCH] rl78 adddi3 improvement
The following patch improves both the speed and code size
On Tue, Sep 26, 2017 at 09:19:50AM -0500, Sebastian Pop wrote:
> Sven, is there already a function that computes the sum of all
> strides in a proximity map? Maybe you have code that does
> something similar in pet or ppcg?
What exactly do you want to sum?
If this involves any counting, then it c
Hi!
On Tue, Sep 26, 2017 at 10:30:03AM -0400, Michael Meissner wrote:
> I have broken the patches down to 8 chunks.
Thanks for doing this.
> +(define_split
> + [(set (match_operand:DI 0 "int_reg_operand")
> + (sign_extend:DI (match_operand:SI 1 "vsx_register_operand")))]
Should be EXTSI in
On Tue, Sep 26, 2017 at 4:44 AM, Janus Weil wrote:
> 2017-09-25 23:23 GMT+02:00 Steve Kargl :
>> On Mon, Sep 25, 2017 at 11:14:42PM +0200, Janus Weil wrote:
>>> 2017-09-25 17:07 GMT+02:00 David Edelsohn :
>>> > promotion_3.f90 and promotion_4.f90 are failing on at least PowerPC
>>> > and AArch64.
Off list, Segher asked that I break the patch eliminating a shift right when
transfering SFmode from a vector register to a GPR register down into smaller
chunks. The power7 and power8 instructions that convert values in the double
precision format to single precision actually duplicate the 32-bit
Off list, Segher asked that I break the patch eliminating a shift right when
transfering SFmode from a vector register to a GPR register down into smaller
chunks. The power7 and power8 instructions that convert values in the double
precision format to single precision actually duplicate the 32-bit
Off list, Segher asked that I break the patch eliminating a shift right when
transfering SFmode from a vector register to a GPR register down into smaller
chunks. The power7 and power8 instructions that convert values in the double
precision format to single precision actually duplicate the 32-bit
Off list, Segher asked that I break the patch eliminating a shift right when
transfering SFmode from a vector register to a GPR register down into smaller
chunks. The power7 and power8 instructions that convert values in the double
precision format to single precision actually duplicate the 32-bit
Off list, Segher asked that I break the patch eliminating a shift right when
transfering SFmode from a vector register to a GPR register down into smaller
chunks. The power7 and power8 instructions that convert values in the double
precision format to single precision actually duplicate the 32-bit
Off list, Segher asked that I break the patch eliminating a shift right when
transfering SFmode from a vector register to a GPR register down into smaller
chunks. The power7 and power8 instructions that convert values in the double
precision format to single precision actually duplicate the 32-bit
Off list, Segher asked that I break the patch eliminating a shift right when
transfering SFmode from a vector register to a GPR register down into smaller
chunks. The power7 and power8 instructions that convert values in the double
precision format to single precision actually duplicate the 32-bit
Off list, Segher asked that I break the patch eliminating a shift right when
transfering SFmode from a vector register to a GPR register down into smaller
chunks. The power7 and power8 instructions that convert values in the double
precision format to single precision actually duplicate the 32-bit
On Tue, Sep 26, 2017 at 7:03 AM, Richard Biener wrote:
>
> The following is the result of me trying to understand SCOP detection
> and the validity checks spread around the machinery. It removes several
> quadraticnesses by folding validity checks into
> scop_detection::harmful_loop_in_region wh
On Mon, Sep 25, 2017 at 8:12 AM, Richard Biener wrote:
> On Fri, 22 Sep 2017, Sebastian Pop wrote:
>
> > On Fri, Sep 22, 2017 at 8:03 AM, Richard Biener
> wrote:
> >
> > >
> > > This simplifies canonicalize_loop_closed_ssa and does other minimal
> > > TLC. It also adds a testcase I reduced from
On Tue, Sep 26, 2017 at 6:02 AM, Richard Biener wrote:
>
> Latent, exposed by me removing the "redundant"
> rewrite-into-loop-closed-ssa.
>
> Bootstrapped and tested on x86_64-unknown-linux-gnu, applied.
>
> Richard.
>
> 2017-09-26 Richard Biener
>
> PR tree-optimization/82321
>
On Mon, Sep 25, 2017 at 8:18 AM, Richard Biener wrote:
>
> The following adds a helper to sort the sibling loop list in RPO order
> as it can get messed up (we only ever add loops at the start of the list).
> GRAPHITE SCOP detection assumes this list is sorted naturally in RPO
> order (as a flow_
On Mon, Sep 25, 2017 at 4:47 AM, Richard Biener wrote:
>
> The following also dumps if the optimized schedule is equal to the
> original one. It also makes all ISL operations (well, nearly) not
> abort on errors but instead propagate errors upward.
>
> Bootstrapped and tested on x86_64-unknown-l
In r251026 (aka 3fe34694f0990d1d649711ede0326497f8a849dc,
"C/C++: show pertinent open token when missing a close token")
I copied part of cp_parser_error into cp_parser_required_error,
leading to duplication of code.
This patch eliminates this duplication by merging the two copies of the
code into
The patch improves our C/C++ frontends' handling of missing
symbols, by making c_parser_require and cp_parser_require use
"better" locations for the diagnostic, and insert fix-it hints,
under certain circumstances (see the comments in the patch for
full details).
For example, for this code with a
On Mon, 2017-08-28 at 09:22 -0600, Jeff Law wrote:
> On 07/03/2017 12:37 PM, David Malcolm wrote:
> > This patch improves our C/C++ frontends' handling of missing
> > symbols, by making c_parser_require and cp_parser_require use
> > "better" locations for the diagnostic, and insert fix-it hints,
>
Here is a new version of the patch.
Igor
> -Original Message-
> From: Sandra Loosemore [mailto:san...@codesourcery.com]
> Sent: Monday, September 25, 2017 5:43 AM
> To: Uros Bizjak ; Tsimbalist, Igor V
>
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: 0005-Part-5.-Add-x86-CET-documentation
Here is the updated version (version#3). All comments below are fixed.
Igor
> -Original Message-
> From: Tsimbalist, Igor V
> Sent: Monday, September 25, 2017 11:57 PM
> To: Sandra Loosemore ; 'gcc-
> patc...@gcc.gnu.org'
> Cc: Jeff Law ; Tsimbalist, Igor V
>
> Subject: RE: 0002-Part-2
On Tue, Sep 26, 2017 at 1:39 PM, Andreas Krebbel
wrote:
> Fails on S/390 with char defaulting to unsigned char.
Ok.
> gcc/testsuite/ChangeLog:
>
> 2017-09-26 Andreas Krebbel
>
> * gcc.dg/vect/pr65947-9.c: Use signed char explicitly.
> ---
> gcc/testsuite/gcc.dg/vect/pr65947-9.c | 2 +
Jakub Jelinek wrote:
> Well, we don't want to regress performance wise on one of the most important
> primary targets. I don't care that much if the RTL/backend work is done
> together with the patch, or as a follow-up during stage1/3, but it should be
> done, the testcases I've posted can be use
Hi All,
The slp vectorization test currently fails on AArch32 and AArch64
due to it not taking into account that we do have 128 bit vectors in
NEON. This means that two of the loops get vectorized instead of just 1.
So update the conditions to include a check for neon.
Regtested on aarch64-none-
On Tue, Sep 26, 2017 at 12:44:10PM +, Sudi Das wrote:
>
> Still waiting on Jakub's comment on whether there are more things needed
> at the backend. But I have updated the patch according to Richard's
> comments.
Well, we don't want to regress performance wise on one of the most important
pr
Hi,
On Sun, Sep 17, 2017 at 02:13:34PM +0200, Thomas Schwinge wrote:
> Hi!
>
> On Tue, 24 Jan 2017 15:30:34 -0500, David Malcolm wrote:
> > On Tue, 2017-01-24 at 13:52 +0100, Martin Jambor wrote:
> > > [...] I have just
> > > committed the BRIG FE as revision 244867.
>
> In a build with that en
Still waiting on Jakub's comment on whether there are more things needed at the
backend. But I have updated the patch according to Richard's comments.
Thanks
Sudi
From: Richard Biener
Sent: Friday, August 4, 2017 11:16 AM
To: Sudi Das
Cc: Wilco Dijkstra; Jakub Jelinek; GCC Patches; nd; Richa
Hi Andreas,
> diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
> index 307c726..3acfd85 100644
> --- a/gcc/doc/sourcebuild.texi
> +++ b/gcc/doc/sourcebuild.texi
> @@ -1398,6 +1398,9 @@ Target supports a vector misalign access.
> @item vect_no_align
> Target does not support a vec
On Tue, Sep 26, 2017 at 2:19 PM, Jakub Jelinek wrote:
> On Sun, Sep 24, 2017 at 11:25:34AM +0200, Uros Bizjak wrote:
>> We can use 'q' modifier just before register output part (plus a small
>> simplification).
>>
>> Can you try the attached (untested) patch?
>>
>> Uros.
>
>> Index: i386.c
>>
On Sun, Sep 24, 2017 at 11:25:34AM +0200, Uros Bizjak wrote:
> We can use 'q' modifier just before register output part (plus a small
> simplification).
>
> Can you try the attached (untested) patch?
>
> Uros.
> Index: i386.c
> ===
On 09/26/2017 01:57 PM, Rainer Orth wrote:
> Hi Andreas,
>
>> We don't have a 64 bit vector integer multiply on z. Add a specific
>> check for that.
>>
>> 2017-09-26 Andreas Krebbel
>>
>> * gcc.dg/vect/pr60656.c: Check vect_mult_long.
>> * lib/target-supports.exp (check_effective_tar
- vect_nopeel renamed to vect_no_peel
- documentation added.
gcc/testsuite/ChangeLog:
2017-09-26 Andreas Krebbel
* doc/sourcebuild.texi: Document vect_no_peel.
gcc/testsuite/ChangeLog:
2017-09-26 Andreas Krebbel
* g++.dg/vect/slp-pr56812.cc: Check vect_nopeel.
*
On Tue, 26 Sep 2017, Jakub Jelinek wrote:
> Hi!
>
> Right now we handle x == 0 && y == 0 into (x | y) == 0
> and x == -1 && y == -1 into (x & y) == -1 optimizations just in
> match.pd, where it will handle the case where the && (or || if using !=)
> is actually & (or |) and they are next to each
The following is the result of me trying to understand SCOP detection
and the validity checks spread around the machinery. It removes several
quadraticnesses by folding validity checks into
scop_detection::harmful_loop_in_region where we already walk over all
BBs in the region and process indivi
Hi!
Right now we handle x == 0 && y == 0 into (x | y) == 0
and x == -1 && y == -1 into (x & y) == -1 optimizations just in
match.pd, where it will handle the case where the && (or || if using !=)
is actually & (or |) and they are next to each other.
It doesn't handle the case when we have such com
Hi Andreas,
> We don't have a 64 bit vector integer multiply on z. Add a specific
> check for that.
>
> 2017-09-26 Andreas Krebbel
>
> * gcc.dg/vect/pr60656.c: Check vect_mult_long.
> * lib/target-supports.exp (check_effective_target_vect_mult_long):
> New proc.
as usual, th
On 09/26/2017 01:06 PM, Rainer Orth wrote:
> Hi Andreas,
>
>> Add s390 platform checks where appropriate.
>>
>> gcc/testsuite/ChangeLog:
>>
>> 2017-09-26 Andreas Krebbel
>>
>> * lib/target-supports.exp: Enable tests for S/390.
>
> this needs to be more specific: which procs were modified?
On Tue, Sep 26, 2017 at 09:17:40AM +0200, Thomas Schwinge wrote:
> Hi!
>
> On Mon, 25 Sep 2017 18:50:49 +0200, Thomas Koenig
> wrote:
> > Thanks for the review, committed as r253156.
> >
> > Now, on to some other bugs...
>
> No, back to this one please. ;-)
>
> Apparently, the changes you pr
Fails on S/390 with char defaulting to unsigned char.
gcc/testsuite/ChangeLog:
2017-09-26 Andreas Krebbel
* gcc.dg/vect/pr65947-9.c: Use signed char explicitly.
---
gcc/testsuite/gcc.dg/vect/pr65947-9.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite
Testcases which override the vect default options using dg-options
need at least -mzarch on S/390 32 bit.
gcc/testsuite/ChangeLog:
2017-09-26 Andreas Krebbel
* gfortran.dg/vect/fast-math-mgrid-resid.f: Use -mzarch on S/390.
* gfortran.dg/vect/pr77848.f: Likewise.
---
gcc/test
Without peeling loops for vector alignment the vectorization costs are
lower and in some cases make the loop vectorizer cover optimizations
which otherwise would be handelt in slp instead.
This adds a new target check for that purpose.
gcc/testsuite/ChangeLog:
2017-09-26 Andreas Krebbel
We don't have a 64 bit vector integer multiply on z. Add a specific
check for that.
2017-09-26 Andreas Krebbel
* gcc.dg/vect/pr60656.c: Check vect_mult_long.
* lib/target-supports.exp (check_effective_target_vect_mult_long):
New proc.
---
gcc/testsuite/gcc.dg/vect/pr6
The target supports routines provide vect_double and vect_float but
these do not appear to be used consequently in the vect testcases.
With z13 we only have support for vector double but with z14 also for
vector float. This patch adds vect_float to the testcases using the
float data type and make
These patches adjust the vect testcases and target support checks in
order to make the right set of testcases to be run on S/390 (z13 and
z14).
Ok for mainline?
Andreas Krebbel (5):
Enable vect_float with S/390 VXE and adjust testcases
pr60656.c: New target check: vect_mult_long
pr65947-9.c
Hi Andreas,
> Add s390 platform checks where appropriate.
>
> gcc/testsuite/ChangeLog:
>
> 2017-09-26 Andreas Krebbel
>
> * lib/target-supports.exp: Enable tests for S/390.
this needs to be more specific: which procs were modified?
Besides, the changes to check_vect_support_and_set_flag
Latent, exposed by me removing the "redundant"
rewrite-into-loop-closed-ssa.
Bootstrapped and tested on x86_64-unknown-linux-gnu, applied.
Richard.
2017-09-26 Richard Biener
PR tree-optimization/82321
* graphite.c (canonicalize_loop_closed_ssa): Properly check
for t
Hi Kelvin,
On Mon, Sep 25, 2017 at 04:11:32PM -0600, Kelvin Nilsen wrote:
> On Power8 little endian, two instructions are needed to load from the
> natural in-memory representation of a vector into a vector register: a
> load followed by a swap. When the vector value to be loaded is a
> constant,
gcc/ChangeLog:
2017-09-26 Andreas Krebbel
* config/s390/vx-builtins.md ("vmslg"): Add missing operand in
assembler output.
* config/s390/s390-builtins.def: Fix constraint on op4.
---
gcc/ChangeLog | 6 ++
gcc/config/s390/s390-builtins.def | 2 +-
gcc/ChangeLog:
2017-09-26 Andreas Krebbel
* config/s390/s390.c (s390_preferred_simd_mode): Return V4SFmode
for SFmode.
---
gcc/ChangeLog | 5 +
gcc/config/s390/s390.c | 8
2 files changed, 13 insertions(+)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index
V2DF mode was still hard-coded here.
gcc/ChangeLog:
2017-09-26 Andreas Krebbel
* config/s390/s390.c (s390_expand_vec_compare): Use the new mode
independent expanders.
* config/s390/vector.md ("vec_cmpuneq", "vec_cmpltgt")
("vec_ordered", "vec_unordered"): New e
gcc/ChangeLog:
2017-09-26 Andreas Krebbel
* config/s390/vector.md ("vec_unpacks_low_v16qi"): Rename to
vec_unpacks_lo_v16qi.
("vec_unpacku_low_v16qi"): Rename to vec_unpacku_lo_v16qi.
---
gcc/ChangeLog | 6 ++
gcc/config/s390/vector.md | 4 ++--
2 files
gcc/ChangeLog:
2017-09-26 Andreas Krebbel
* config/s390/vector.md ("vec_unpacks_lo_v4sf")
("vec_unpacks_hi_v4sf", "vec_unpacks_lo_v2df")
("vec_unpacks_hi_v2df", "vec_pack_trunc_v2df"): New expanders.
---
gcc/ChangeLog | 6 +++
gcc/config/s390/vector.md | 9
Add s390 platform checks where appropriate.
gcc/testsuite/ChangeLog:
2017-09-26 Andreas Krebbel
* lib/target-supports.exp: Enable tests for S/390.
---
gcc/testsuite/ChangeLog | 4 ++
gcc/testsuite/lib/target-supports.exp | 131 ++
2 fil
gcc/ChangeLog:
2017-09-26 Andreas Krebbel
* config/s390/predicates.md ("const_shift_by_byte_operand"): New
predicate.
* config/s390/vector.md ("*vec_srb"): Change modes to V_128
and V16QI.
("*vec_slb"): New insn pattern.
("vec_shr_"): New expande
Add support for widening vector multiply lo/hi patterns. These do not
directly match on IBM Z instructions but can be emulated with even/odd
+ vector merge.
gcc/ChangeLog:
2017-09-26 Andreas Krebbel
* config/s390/vector.md ("vec_widen_umult_lo_")
("vec_widen_umult_hi_", "vec_
Committed to mainline
Andreas Krebbel (8):
Enable vect testcases on S/390.
S/390: Add widening vector mult lo/hi patterns
S/390: Add support for vec_shr
S/390: Add FP vec_pack/unpack
S/390: Fix rtl standard names for vector unpack low->lo
S/390: Set the preferred mode for float vectors
On 09/26/2017 12:17 PM, Eric Botcazou wrote:
By the way, why not always do this "inlining", even when not optimizing?
Because this generates more bloated code and inferior debugging experience.
This is a trick question, because when you answer "because XYZ" I will then
reply "but XYZ is a com
Hi Arno,
it looks like this is in essence inlining the run-time library
routine. In which case, shouldn't you only do it if inlining is
enabled? For example, it seems rather odd to do this if
compiling with -Os.
Actually, measurements showed that this instance of inlining is a
win for both pe
> By the way, why not always do this "inlining", even when not optimizing?
Because this generates more bloated code and inferior debugging experience.
> This is a trick question, because when you answer "because XYZ" I will then
> reply "but XYZ is a common reason that people disable inlining whe
Duncan,
> >>it looks like this is in essence inlining the run-time library
> >>routine. In which case, shouldn't you only do it if inlining is
> >>enabled? For example, it seems rather odd to do this if
> >>compiling with -Os.
> >
> >Actually, measurements showed that this instance of inlining is
Hi Pierre-Marie,
On 09/26/2017 11:30 AM, Pierre-Marie de Rodat wrote:
On 09/25/2017 02:47 PM, Duncan Sands wrote:
it looks like this is in essence inlining the run-time library routine. In
which case, shouldn't you only do it if inlining is enabled? For example, it
seems rather odd to do this
Hi Rainer,
>> Attached is a more complete patch, which should fix all problems that
>> were reported concerning these two test cases. Would be great if
>> someone could confirm that it works on a failing target (I currently
>> only have access to x86_64-linux-gnu machines).
>
> I've just checked s
The new option processing machinery relies on %< rules in the specs to
suppress options that are rewritten. Suppression appears to be a two
phase process where the option is partially suppressed when %< is
processed and then fully suppressed at the end of the string. Strings
are separated by comm
On 09/25/2017 02:47 PM, Duncan Sands wrote:
it looks like this is in essence inlining the run-time library routine.
In which case, shouldn't you only do it if inlining is enabled? For
example, it seems rather odd to do this if compiling with -Os.
Actually, measurements showed that this insta
Hi Janus,
> Attached is a more complete patch, which should fix all problems that
> were reported concerning these two test cases. Would be great if
> someone could confirm that it works on a failing target (I currently
> only have access to x86_64-linux-gnu machines).
I've just checked sparc-sun
2017-09-26 10:44 GMT+02:00 Janus Weil :
> 2017-09-25 23:23 GMT+02:00 Steve Kargl :
>> On Mon, Sep 25, 2017 at 11:14:42PM +0200, Janus Weil wrote:
>>> 2017-09-25 17:07 GMT+02:00 David Edelsohn :
>>> > promotion_3.f90 and promotion_4.f90 are failing on at least PowerPC
>>> > and AArch64. Are these n
2017-09-25 23:23 GMT+02:00 Steve Kargl :
> On Mon, Sep 25, 2017 at 11:14:42PM +0200, Janus Weil wrote:
>> 2017-09-25 17:07 GMT+02:00 David Edelsohn :
>> > promotion_3.f90 and promotion_4.f90 are failing on at least PowerPC
>> > and AArch64. Are these new tests limited to x86 or some long double
>>
1 - 100 of 105 matches
Mail list logo
