Hi,
On Tue, Sep 26, 2017 at 10:32:03AM -0400, Michael Meissner wrote:
> * config/rs6000/rs6000.md (movsi_from_sf): Adjust code to
> eliminate doing a 32-bit shift right or vector extract after doing
> XSCVDPSPN. Use zero_extendsidi2 instead of p8_mfvsrd_4_disf to
> move the value to the GPRs.
> (movdi_from_sf_zero_ext): Likewise.
> (reload_gpr_from_vsxsf): Likewise.
> --- gcc/config/rs6000/rs6000.md (revision 253169)
> +++ gcc/config/rs6000/rs6000.md (working copy)
> @@ -6806,25 +6806,25 @@ (define_insn "*movsi_internal1_single"
> ;; needed.
>
> ;; MR LWZ LFIWZX LXSIWZX STW
> -;; STFS STXSSP STXSSPX VSX->GPR MTVSRWZ
> -;; VSX->VSX
> +;; STFS STXSSP STXSSPX VSX->GPR VSX->VSX,
> +;; MTVSRWZ
(Typo: comma at end of line).
> (define_insn_and_split "movsi_from_sf"
> [(set (match_operand:SI 0 "nonimmediate_operand"
> "=r, r, ?*wI, ?*wH, m,
> - m, wY, Z, r, wIwH,
> - ?wK")
> + m, wY, Z, r, ?*wIwH,
> + wIwH")
>
> (unspec:SI [(match_operand:SF 1 "input_operand"
> "r, m, Z, Z, r,
> - f, wb, wu, wIwH, r,
> - wK")]
> + f, wb, wu, wIwH, wIwH,
> + r")]
> UNSPEC_SI_FROM_SF))
>
> (clobber (match_scratch:V4SF 2
> "=X, X, X, X, X,
> - X, X, X, wa, X,
> - wa"))]
> + X, X, X, wIwH, X,
> + X"))]
>
> "TARGET_NO_SF_SUBREG
> && (register_operand (operands[0], SImode)
> @@ -6839,10 +6839,10 @@ (define_insn_and_split "movsi_from_sf"
> stxssp %1,%0
> stxsspx %x1,%y0
> #
> - mtvsrwz %x0,%1
> - #"
> + xscvdpspn %x0,%x1
> + mtvsrwz %x0,%1"
> "&& reload_completed
> - && register_operand (operands[0], SImode)
> + && int_reg_operand (operands[0], SImode)
> && vsx_reg_sfsubreg_ok (operands[1], SFmode)"
> [(const_int 0)]
> {
So you swap the last two alternatives. Hrm okay.
> @@ -6850,52 +6850,41 @@ (define_insn_and_split "movsi_from_sf"
> rtx op1 = operands[1];
> rtx op2 = operands[2];
> rtx op0_di = gen_rtx_REG (DImode, REGNO (op0));
> + rtx op2_si = gen_rtx_REG (SImode, REGNO (op2));
>
Does this work, btw? I would expect you need reg_or_subregno, for op0
that is (the new op2 might be fine, not sure). You do use it in most
places; please check.
> ;; movsi_from_sf with zero extension
> ;;
> ;; RLDICL LWZ LFIWZX LXSIWZX VSX->GPR
> -;; MTVSRWZ VSX->VSX
> +;; VSX->VSX MTVSRWZ
>
> (define_insn_and_split "*movdi_from_sf_zero_ext"
> [(set (match_operand:DI 0 "gpc_reg_operand"
> "=r, r, ?*wI, ?*wH, r,
> - wIwH, ?wK")
> + wK, wIwH")
This loses the "?", is that on purpose?
> [(set_attr "type"
> "*, load, fpload, fpload, mftgpr,
> - mffgpr, veclogical")
> + vecexts, mffgpr")
vecsimple or vecfloat I guess, not vecexts. We have no way of describing
it exactly, of course. Maybe just "two".
Okay for trunk with those things taken care of. Thanks!
Segher
