[gcc r15-3210] tree-optimization/116460 - ICE with DCE in forwprop

https://gcc.gnu.org/g:172637cf0d9b7b2798f83b9c5f9598b449675cb0 commit r15-3210-g172637cf0d9b7b2798f83b9c5f9598b449675cb0 Author: Richard Biener Date: Mon Aug 26 13:50:00 2024 +0200 tree-optimization/116460 - ICE with DCE in forwprop The following avoids removing stmts with defs th

[gcc r15-3211] c++, coroutines: The frame pointer is used in the helpers [PR116482].

https://gcc.gnu.org/g:8d6d6c864442a1cc987b3e6bcb1d903ceb975e4a commit r15-3211-g8d6d6c864442a1cc987b3e6bcb1d903ceb975e4a Author: Iain Sandoe Date: Mon Aug 26 14:09:40 2024 +0100 c++, coroutines: The frame pointer is used in the helpers [PR116482]. We have a bogus warning about the

[gcc r15-3212] lra: Don't apply eliminations to allocated registers [PR116321]

https://gcc.gnu.org/g:9db997e5ac4a206b9428eb2447fcdc90e37725f4 commit r15-3212-g9db997e5ac4a206b9428eb2447fcdc90e37725f4 Author: Richard Sandiford Date: Tue Aug 27 09:48:28 2024 +0100 lra: Don't apply eliminations to allocated registers [PR116321] The sequence of events in this PR

[gcc r15-3213] Handle arithmetic on eliminated address indices [PR116413]

https://gcc.gnu.org/g:708ee71808ea61758e73d0e36274b4194b28576a commit r15-3213-g708ee71808ea61758e73d0e36274b4194b28576a Author: Richard Sandiford Date: Tue Aug 27 09:48:28 2024 +0100 Handle arithmetic on eliminated address indices [PR116413] This patch fixes gcc.c-torture/compile

[gcc r15-3214] Un-XFAIL 'gcc.dg/signbit-5.c' for GCN

https://gcc.gnu.org/g:2daf6187c7289d012365419e10995042139cf8f5 commit r15-3214-g2daf6187c7289d012365419e10995042139cf8f5 Author: Thomas Schwinge Date: Tue Aug 27 12:37:29 2024 +0200 Un-XFAIL 'gcc.dg/signbit-5.c' for GCN It XPASSes after recent commit 5a3387938d4d95717cac29eecd0ba5

[gcc r15-3215] testsuite: Fix ending of comment in test cases

https://gcc.gnu.org/g:442e3cd20cb9504e8c65815c8a8ad0cfa3e4efa8 commit r15-3215-g442e3cd20cb9504e8c65815c8a8ad0cfa3e4efa8 Author: Torbjörn SVENSSON Date: Tue Aug 27 12:53:37 2024 +0200 testsuite: Fix ending of comment in test cases gcc/testsuite/ChangeLog: * gcc.dg

[gcc/devel/nothrow-detection] Fix handling of types

https://gcc.gnu.org/g:c16d4a0ae162abc00d97bb73e598ca00d16cf555 commit c16d4a0ae162abc00d97bb73e598ca00d16cf555 Author: Jan Hubicka Date: Tue Aug 27 13:50:32 2024 +0200 Fix handling of types * ipa-devirt.cc (odr_equivalent_or_derived_p): New. * ipa-utils.h (odr_

[gcc r15-3216] c++: Add correct copyright dates to output of gen-cxxapi-file.py

https://gcc.gnu.org/g:ff4aa45535bc0103e4417e72386089a5421fe520 commit r15-3216-gff4aa45535bc0103e4417e72386089a5421fe520 Author: Jonathan Wakely Date: Tue Aug 27 12:17:03 2024 +0100 c++: Add correct copyright dates to output of gen-cxxapi-file.py This ensures the generated output

[gcc r15-3217] c++: Add most missing C++20 and C++23 names to cxxapi-data.csv

https://gcc.gnu.org/g:470a27859d8a47a99f389f1dc6edb82c08b16e21 commit r15-3217-g470a27859d8a47a99f389f1dc6edb82c08b16e21 Author: Jonathan Wakely Date: Tue Aug 27 12:19:47 2024 +0100 c++: Add most missing C++20 and C++23 names to cxxapi-data.csv This includes uncommenting the atomi

[gcc r15-3218] libstdc++: Do not use std::vector::reference default ctor [PR115098]

https://gcc.gnu.org/g:75ef21665cb924265b818b08babbc7ec3108c876 commit r15-3218-g75ef21665cb924265b818b08babbc7ec3108c876 Author: Jonathan Wakely Date: Tue Aug 27 13:30:42 2024 +0100 libstdc++: Do not use std::vector::reference default ctor [PR115098] This default constructor was m

[gcc r15-3219] final: go down ASHIFT in walk_alter_subreg

https://gcc.gnu.org/g:359209bdc7245f8768b5044acded8509545e4990 commit r15-3219-g359209bdc7245f8768b5044acded8509545e4990 Author: Michael Matz Date: Thu Aug 22 17:03:56 2024 +0200 final: go down ASHIFT in walk_alter_subreg when experimenting with m68k plus LRA one of the change

[gcc r15-3221] LRA: Fix setup_sp_offset

https://gcc.gnu.org/g:e223ac9c225352e3aeea7180a3b56a96ecdbe2fd commit r15-3221-ge223ac9c225352e3aeea7180a3b56a96ecdbe2fd Author: Michael Matz Date: Thu Aug 22 17:21:42 2024 +0200 LRA: Fix setup_sp_offset This is part of making m68k work with LRA. See PR116429. In short: setup

[gcc r15-3220] LRA: Don't use 0 as initialization for sp_offset

https://gcc.gnu.org/g:542773888190ef67dca194f4861abab104fa9b5b commit r15-3220-g542773888190ef67dca194f4861abab104fa9b5b Author: Michael Matz Date: Thu Aug 22 17:09:11 2024 +0200 LRA: Don't use 0 as initialization for sp_offset this is part of making m68k work with LRA. See PR116

[gcc r15-3222] Extend check-function-bodies to allow label and directives

https://gcc.gnu.org/g:d6bb1e257fc414d21bc31faa7ddecbc93a197e3c commit r15-3222-gd6bb1e257fc414d21bc31faa7ddecbc93a197e3c Author: H.J. Lu Date: Tue Aug 27 07:03:22 2024 -0700 Extend check-function-bodies to allow label and directives As PR target/116174 shown, we may need to verify

[gcc r15-3223] pr116174.c: Add the missing */

https://gcc.gnu.org/g:ee986126807e68b996d02f5d792268df799b32fb commit r15-3223-gee986126807e68b996d02f5d792268df799b32fb Author: H.J. Lu Date: Tue Aug 27 07:21:02 2024 -0700 pr116174.c: Add the missing */ * gcc.target/i386/pr116174.c: Add the missing */. Signed-of

[gcc r15-3224] arm: Always use vmov.f64 instead of vmov.f32 with MVE

https://gcc.gnu.org/g:37c21d4c6ad0afe2aacdd6384b9efa96f5754169 commit r15-3224-g37c21d4c6ad0afe2aacdd6384b9efa96f5754169 Author: Christophe Lyon Date: Wed Aug 21 13:58:08 2024 + arm: Always use vmov.f64 instead of vmov.f32 with MVE With MVE, vmov.f64 is always supported (no ne

[gcc r15-3225] RISC-V: Fix vid const vector expander for non-npatterns size steps

https://gcc.gnu.org/g:c89038c7ae8bba7160ae2963647ce90171b5dd2c commit r15-3225-gc89038c7ae8bba7160ae2963647ce90171b5dd2c Author: Patrick O'Neill Date: Wed Aug 21 23:48:24 2024 -0700 RISC-V: Fix vid const vector expander for non-npatterns size steps Prior to this patch the expander

[gcc r15-3226] RISC-V: Reorder insn cost match order to match corresponding expander match order

https://gcc.gnu.org/g:ac1f3a8901344759dc7c247d3749c74a0bb524b0 commit r15-3226-gac1f3a8901344759dc7c247d3749c74a0bb524b0 Author: Patrick O'Neill Date: Tue Aug 20 11:38:20 2024 -0700 RISC-V: Reorder insn cost match order to match corresponding expander match order The correspondin

[gcc r15-3227] RISC-V: Handle case when constant vector construction target rtx is not a register

https://gcc.gnu.org/g:a3dc5d2100a3d17a2d67805de6d0373847bca780 commit r15-3227-ga3dc5d2100a3d17a2d67805de6d0373847bca780 Author: Patrick O'Neill Date: Tue Aug 20 11:29:12 2024 -0700 RISC-V: Handle case when constant vector construction target rtx is not a register This manifests

[gcc r15-3229] RISC-V: Handle 0.0 floating point pattern costing to match const_vector expander

https://gcc.gnu.org/g:282bbc9381c563c746a43bf35e93d349188cc8e8 commit r15-3229-g282bbc9381c563c746a43bf35e93d349188cc8e8 Author: Patrick O'Neill Date: Tue Aug 20 12:01:22 2024 -0700 RISC-V: Handle 0.0 floating point pattern costing to match const_vector expander The comment previ

[gcc r15-3231] RISC-V: Move helper functions above expand_const_vector

https://gcc.gnu.org/g:691f682fe24d07ff5854f1f53d81909320110c9c commit r15-3231-g691f682fe24d07ff5854f1f53d81909320110c9c Author: Patrick O'Neill Date: Mon Aug 19 12:40:14 2024 -0700 RISC-V: Move helper functions above expand_const_vector These subroutines will be used in expand_co

[gcc r15-3228] RISC-V: Emit costs for bool and stepped const vectors

https://gcc.gnu.org/g:771256bcb9ddc478dd0a8ecf929dfda5334f0ff3 commit r15-3228-g771256bcb9ddc478dd0a8ecf929dfda5334f0ff3 Author: Patrick O'Neill Date: Tue Aug 20 11:51:50 2024 -0700 RISC-V: Emit costs for bool and stepped const vectors These cases are handled in the expander (

[gcc r15-3230] RISC-V: Allow non-duplicate bool patterns in expand_const_vector

https://gcc.gnu.org/g:1cd890279668bf94c93004bdbb757a1342931914 commit r15-3230-g1cd890279668bf94c93004bdbb757a1342931914 Author: Patrick O'Neill Date: Tue Aug 20 12:50:51 2024 -0700 RISC-V: Allow non-duplicate bool patterns in expand_const_vector Currently we assert when encounter

[gcc r15-3232] c++: Don't show constructor internal name in error message [PR105483]

https://gcc.gnu.org/g:02dff52c60e5b89d290147f142f655c7817154c2 commit r15-3232-g02dff52c60e5b89d290147f142f655c7817154c2 Author: Simon Martin Date: Mon Aug 26 14:09:46 2024 +0200 c++: Don't show constructor internal name in error message [PR105483] We mention 'X::__ct' instead of

[gcc r15-3233] m68k: Accept ASHIFT like MULT in address operand

https://gcc.gnu.org/g:a83e519ab2d4e7df2756411cd9d21c6f1b583429 commit r15-3233-ga83e519ab2d4e7df2756411cd9d21c6f1b583429 Author: Andreas Schwab Date: Tue Aug 27 21:01:00 2024 +0200 m68k: Accept ASHIFT like MULT in address operand When LRA pulls an address operand out of a MEM it c

[gcc r15-3234] c++/coroutines: fix actor cases not being added to the current switch [PR109867]

https://gcc.gnu.org/g:ff0cba200af72f2514ebc987a99027f314d4cc99 commit r15-3234-gff0cba200af72f2514ebc987a99027f314d4cc99 Author: Arsen Arsenović Date: Wed Jul 24 20:43:01 2024 +0200 c++/coroutines: fix actor cases not being added to the current switch [PR109867] Previously, we we

[gcc r15-3235] Update gcc zh_CN.po

https://gcc.gnu.org/g:48032f28ad4bc5e810c303229bcaa223a0c4d09f commit r15-3235-g48032f28ad4bc5e810c303229bcaa223a0c4d09f Author: Joseph Myers Date: Tue Aug 27 21:20:43 2024 + Update gcc zh_CN.po * zh_CN.po: Update. Diff: --- gcc/po/zh_CN.po | 351

[gcc r14-10614] Update gcc zh_CN.po

https://gcc.gnu.org/g:90b123253dd28e03cbec03e8c71cafc366a3f602 commit r14-10614-g90b123253dd28e03cbec03e8c71cafc366a3f602 Author: Joseph Myers Date: Tue Aug 27 21:21:58 2024 + Update gcc zh_CN.po * zh_CN.po: Update. Diff: --- gcc/po/zh_CN.po | 351 +++

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Remove testcase XFAIL

https://gcc.gnu.org/g:fa76531046b57a540ccf88a67e7636353dfe43e0 commit fa76531046b57a540ccf88a67e7636353dfe43e0 Author: Edwin Lu Date: Mon Aug 19 13:10:15 2024 -0700 RISC-V: Remove testcase XFAIL The testcase has been modified to include the -fwrapv flag which now causes the te

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix one typo in .SAT_TRUNC test func name [NFC]

https://gcc.gnu.org/g:f93c8ea4f748225910a1cb25e95adc081e0d7be7 commit f93c8ea4f748225910a1cb25e95adc081e0d7be7 Author: Pan Li Date: Tue Aug 20 21:08:23 2024 +0800 RISC-V: Fix one typo in .SAT_TRUNC test func name [NFC] Fix one typo `sat_truc` to `sat_trunc`, as well as `SAT_TRUC`

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PR rtl-optimization/116437] Fix RTL checking issue in ext-dce

https://gcc.gnu.org/g:9660ade008244720fc3653865c7beaae09d6e3da commit 9660ade008244720fc3653865c7beaae09d6e3da Author: Jeff Law Date: Wed Aug 21 16:52:23 2024 -0600 [PR rtl-optimization/116437] Fix RTL checking issue in ext-dce Another RTL checking failure in ext-dce. An easy one

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 2

https://gcc.gnu.org/g:c8eec5d1eb5db3ed9ec0a781fe94867f69d3 commit c8eec5d1eb5db3ed9ec0a781fe94867f69d3 Author: Pan Li Date: Wed Aug 21 17:43:12 2024 +0800 RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 2 This patch would like to add test cases for the unsigned v

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 3

https://gcc.gnu.org/g:327021ed2a74817b2c9986e87358d84a0d921b00 commit 327021ed2a74817b2c9986e87358d84a0d921b00 Author: Pan Li Date: Wed Aug 21 17:57:47 2024 +0800 RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 3 This patch would like to add test cases for the unsigned v

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PR rtl-optimization/116420] Fix interesting block bitmap DF dataflow

https://gcc.gnu.org/g:9843c449d1ff93e0dc402f08eae0362302989049 commit 9843c449d1ff93e0dc402f08eae0362302989049 Author: Jeff Law Date: Thu Aug 22 12:48:49 2024 -0600 [PR rtl-optimization/116420] Fix interesting block bitmap DF dataflow The DF framework provides us a way to run data

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix vector cfi notes for stack-clash protection

https://gcc.gnu.org/g:204928bdf68a333ff8ca232397fb6a29b91bbc6a commit 204928bdf68a333ff8ca232397fb6a29b91bbc6a Author: Raphael Moreira Zinsly Date: Wed Aug 21 18:08:54 2024 -0300 RISC-V: Fix vector cfi notes for stack-clash protection The stack-clash code is generating wrong cfi d

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Expand vec abs without masking.

https://gcc.gnu.org/g:57cc189f5f5b50711fd37ee08308157fec0033f9 commit 57cc189f5f5b50711fd37ee08308157fec0033f9 Author: Robin Dapp Date: Fri Aug 9 15:05:39 2024 +0200 RISC-V: Expand vec abs without masking. Standard abs synthesis during expand is max (a, -a). This expansion ha

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Use encoded nelts when calling repeating_sequence_p

https://gcc.gnu.org/g:3ee78b3342cbe83e3498fd0b355e57ff9a30966d commit 3ee78b3342cbe83e3498fd0b355e57ff9a30966d Author: Patrick O'Neill Date: Mon Aug 19 12:19:33 2024 -0700 RISC-V: Use encoded nelts when calling repeating_sequence_p repeating_sequence_p operates directly on the enc

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Turn off late-combine for a few risc-v specific tests

https://gcc.gnu.org/g:ee54c9f75f443283801cc11eaec3d58ad85170b0 commit ee54c9f75f443283801cc11eaec3d58ad85170b0 Author: Jeff Law Date: Sun Aug 25 07:06:45 2024 -0600 Turn off late-combine for a few risc-v specific tests Just minor testsuite adjustments -- several of the shorten-mem

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] optabs-query: Use opt_machine_mode for smallest_int_mode_for_size [PR115495].

https://gcc.gnu.org/g:0e8e9e768db6649899038cf4a0de2ad604cb4535 commit 0e8e9e768db6649899038cf4a0de2ad604cb4535 Author: Robin Dapp Date: Tue Aug 20 14:02:09 2024 +0200 optabs-query: Use opt_machine_mode for smallest_int_mode_for_size [PR115495]. In get_best_extraction_insn we use

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] Fix assembly scan for RISC-V VLS tests

https://gcc.gnu.org/g:d95274bbd89eca93a94670d4688fa4b829cd commit d95274bbd89eca93a94670d4688fa4b829cd Author: Jeff Law Date: Sun Aug 25 07:16:50 2024 -0600 [committed] Fix assembly scan for RISC-V VLS tests Surya's IRA patch from June slightly improves the code we generat

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Disable late-combine in another RISC-V test

https://gcc.gnu.org/g:12fb83c7f94ad3a2b73a940f045ab6ec70f87d8b commit 12fb83c7f94ad3a2b73a940f045ab6ec70f87d8b Author: Jeff Law Date: Sun Aug 25 07:24:56 2024 -0600 Disable late-combine in another RISC-V test Another test where the output was slightly twiddled by late-combine in w

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH] Re-add calling emit_clobber in lower-subreg.cc's resolve_simple_move.

https://gcc.gnu.org/g:76ed0a7caacfc924d5ba67fc1eabc6446a8d8207 commit 76ed0a7caacfc924d5ba67fc1eabc6446a8d8207 Author: Xianmiao Qu Date: Sun Aug 25 11:22:21 2024 -0600 [PATCH] Re-add calling emit_clobber in lower-subreg.cc's resolve_simple_move. The previous patch: https://g

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix double mode under RV32 not utilize vf

https://gcc.gnu.org/g:93ef25c6f7366df397a985df569d12def715ee22 commit 93ef25c6f7366df397a985df569d12def715ee22 Author: demin.han Date: Sun Aug 25 15:53:58 2024 -0600 RISC-V: Fix double mode under RV32 not utilize vf Currently, some binops of vector vs double scalar under RV32 can'

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 4

https://gcc.gnu.org/g:a2432f0bc14acc8bfed1f72728f2b8bf9b2f9744 commit a2432f0bc14acc8bfed1f72728f2b8bf9b2f9744 Author: Pan Li Date: Sun Aug 25 11:02:10 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 4 This patch would like to add test cases for the unsigned s

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 4

https://gcc.gnu.org/g:db1772fa10aecab5344bac705c60baaba71fd11c commit db1772fa10aecab5344bac705c60baaba71fd11c Author: Pan Li Date: Sun Aug 25 14:15:40 2024 +0800 RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 4 This patch would like to add test cases for the unsigned v

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Support IMM for operand 0 of ussub pattern

https://gcc.gnu.org/g:ffb7ed746bee04052b62b2d4601bc9992acb40bc commit ffb7ed746bee04052b62b2d4601bc9992acb40bc Author: Pan Li Date: Sat Aug 3 07:02:57 2024 + RISC-V: Support IMM for operand 0 of ussub pattern This patch would like to allow IMM for the operand 0 of ussub patter

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Move helper functions above expand_const_vector

https://gcc.gnu.org/g:9d19855517b95a0205c795becab4c67b0c9eac7e commit 9d19855517b95a0205c795becab4c67b0c9eac7e Author: Patrick O'Neill Date: Mon Aug 19 12:40:14 2024 -0700 RISC-V: Move helper functions above expand_const_vector These subroutines will be used in expand_const_vector

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Support IMM for operand 1 of ussub pattern

https://gcc.gnu.org/g:a5bd5cc741a806106740fb10837dd6dacc630298 commit a5bd5cc741a806106740fb10837dd6dacc630298 Author: Pan Li Date: Mon Aug 26 15:58:52 2024 +0800 RISC-V: Support IMM for operand 1 of ussub pattern This patch would like to allow IMM for the operand 1 of ussub patte

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix vid const vector expander for non-npatterns size steps

https://gcc.gnu.org/g:3d0ae86388b8c89133386e9ee2c97ac8c75bf80a commit 3d0ae86388b8c89133386e9ee2c97ac8c75bf80a Author: Patrick O'Neill Date: Wed Aug 21 23:48:24 2024 -0700 RISC-V: Fix vid const vector expander for non-npatterns size steps Prior to this patch the expander would emi

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Reorder insn cost match order to match corresponding expander match order

https://gcc.gnu.org/g:77bdff2732045dfd049cb8ab91c948514f444fcb commit 77bdff2732045dfd049cb8ab91c948514f444fcb Author: Patrick O'Neill Date: Tue Aug 20 11:38:20 2024 -0700 RISC-V: Reorder insn cost match order to match corresponding expander match order The corresponding expander

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Handle case when constant vector construction target rtx is not a register

https://gcc.gnu.org/g:d812473dad74924f641325e3548333d93fa65b41 commit d812473dad74924f641325e3548333d93fa65b41 Author: Patrick O'Neill Date: Tue Aug 20 11:29:12 2024 -0700 RISC-V: Handle case when constant vector construction target rtx is not a register This manifests in RTL tha

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Emit costs for bool and stepped const vectors

https://gcc.gnu.org/g:1c7dfc57c1363ea7e387527a5919642308001b2f commit 1c7dfc57c1363ea7e387527a5919642308001b2f Author: Patrick O'Neill Date: Tue Aug 20 11:51:50 2024 -0700 RISC-V: Emit costs for bool and stepped const vectors These cases are handled in the expander (riscv-v.cc

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Handle 0.0 floating point pattern costing to match const_vector expander

https://gcc.gnu.org/g:f815c8f308c29271702255ec5690b77896ce71f3 commit f815c8f308c29271702255ec5690b77896ce71f3 Author: Patrick O'Neill Date: Tue Aug 20 12:01:22 2024 -0700 RISC-V: Handle 0.0 floating point pattern costing to match const_vector expander The comment previously here

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Allow non-duplicate bool patterns in expand_const_vector

https://gcc.gnu.org/g:a27d2ba5f655608dee585b6500bbdda17f488e91 commit a27d2ba5f655608dee585b6500bbdda17f488e91 Author: Patrick O'Neill Date: Tue Aug 20 12:50:51 2024 -0700 RISC-V: Allow non-duplicate bool patterns in expand_const_vector Currently we assert when encountering a non-

[gcc r15-3236] Fix test failing on sparc

https://gcc.gnu.org/g:ffb00a0da44be946bcac45dd702e18555f564b2e commit r15-3236-gffb00a0da44be946bcac45dd702e18555f564b2e Author: Andi Kleen Date: Tue Aug 27 16:45:26 2024 -0700 Fix test failing on sparc SPARC does not support vectorizing conditions, which this test relies on.

[gcc r15-3238] RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 3

https://gcc.gnu.org/g:cb0b8b62223b485a058a56fc5c6345974ebaa230 commit r15-3238-gcb0b8b62223b485a058a56fc5c6345974ebaa230 Author: Pan Li Date: Tue Aug 27 14:37:01 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 3 This patch would like to add test cases for th

[gcc r15-3239] RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 4

https://gcc.gnu.org/g:3989e31d867b3505f847ecb6d870eacacfdf47bf commit r15-3239-g3989e31d867b3505f847ecb6d870eacacfdf47bf Author: Pan Li Date: Tue Aug 27 15:14:40 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 4 This patch would like to add test cases for th

[gcc r15-3240] Fix PR testsuite/116271, gcc.dg/vect/tsvc/vect-tsvc-s176.c fails

https://gcc.gnu.org/g:beb94f5979953969593a2387561cdbc8fedfaeb1 commit r15-3240-gbeb94f5979953969593a2387561cdbc8fedfaeb1 Author: Joern Rennecke Date: Wed Aug 28 01:46:25 2024 +0100 Fix PR testsuite/116271, gcc.dg/vect/tsvc/vect-tsvc-s176.c fails gcc/testsuite: PR tests

[gcc r15-3241] Match: Support form 1 for scalar signed integer .SAT_ADD

https://gcc.gnu.org/g:fe5f652bab420eb372645281f7fe3e5aa1534d01 commit r15-3241-gfe5f652bab420eb372645281f7fe3e5aa1534d01 Author: Pan Li Date: Mon Aug 26 10:11:38 2024 +0800 Match: Support form 1 for scalar signed integer .SAT_ADD This patch would like to support the form 1 of the

[gcc r15-3242] RISC-V: Add missing mode_idx for vrol and vror

https://gcc.gnu.org/g:3cde331e9590944819621bcde41ddbffd9bbf0ba commit r15-3242-g3cde331e9590944819621bcde41ddbffd9bbf0ba Author: Kito Cheng Date: Tue Aug 27 21:27:02 2024 +0800 RISC-V: Add missing mode_idx for vrol and vror We add pattern for vector rotate, but seems like we forgo

[gcc(refs/users/egallager/heads/master)] Merge branch 'gcc-mirror:master' into me/master

https://gcc.gnu.org/g:c271fdc52ebe8067451e52a75794076613ae23a2 commit c271fdc52ebe8067451e52a75794076613ae23a2 Merge: be2674c47243 184978cd74f9 Author: Eric Gallager Date: Mon Feb 5 18:49:21 2024 -0500 Merge branch 'gcc-mirror:master' into me/master Diff: ChangeLog

[gcc(refs/users/egallager/heads/master)] Merge branch 'gcc-mirror:master' into me/master

https://gcc.gnu.org/g:acf3202147a77c67242e9638932ed7878cdee2f8 commit acf3202147a77c67242e9638932ed7878cdee2f8 Merge: f1b89f438575 4e3c8257304c Author: Eric Gallager Date: Sat Apr 6 20:18:13 2024 -0400 Merge branch 'gcc-mirror:master' into me/master Diff: ChangeLog

[gcc(refs/users/egallager/heads/master)] Merge branch 'gcc-mirror:master' into me/master

https://gcc.gnu.org/g:91913f4fdf0be9213eeb7cc787f91fdbf7b1ee38 commit 91913f4fdf0be9213eeb7cc787f91fdbf7b1ee38 Merge: acf3202147a7 b909daa5b673 Author: Eric Gallager Date: Mon Apr 22 18:22:16 2024 -0400 Merge branch 'gcc-mirror:master' into me/master Diff: ChangeLog

[gcc(refs/users/egallager/heads/master)] Merge branch 'gcc-mirror:master' into me/master

https://gcc.gnu.org/g:68dbebb95d94b331d4d71a96b6187fc6f1e47a29 commit 68dbebb95d94b331d4d71a96b6187fc6f1e47a29 Merge: b7b360c08cee 24cb586cafd4 Author: Eric Gallager Date: Sun Jul 7 15:13:57 2024 -0400 Merge branch 'gcc-mirror:master' into me/master Diff: ChangeLog

[gcc(refs/users/egallager/heads/CI)] Merge branch 'gcc-mirror:master' into me/CI

https://gcc.gnu.org/g:b2b3563188cb9e8a2e8116ba2f4b3495155c6809 commit b2b3563188cb9e8a2e8116ba2f4b3495155c6809 Merge: c64aef013f25 184978cd74f9 Author: Eric Gallager Date: Mon Feb 5 18:49:51 2024 -0500 Merge branch 'gcc-mirror:master' into me/CI Diff: ChangeLog

[gcc(refs/users/egallager/heads/CI)] Merge branch 'gcc-mirror:master' into me/CI

https://gcc.gnu.org/g:90e8f13063ec5d3e9d422115900169e0545e65ca commit 90e8f13063ec5d3e9d422115900169e0545e65ca Merge: b2b3563188cb 39d989022dd0 Author: Eric Gallager Date: Mon Feb 12 16:16:49 2024 -0500 Merge branch 'gcc-mirror:master' into me/CI Diff: ChangeLog

[gcc(refs/users/egallager/heads/CI)] Merge branch 'gcc-mirror:master' into me/CI

https://gcc.gnu.org/g:407eabd4ac5221a29b0a024e07161cc61fecb7c7 commit 407eabd4ac5221a29b0a024e07161cc61fecb7c7 Merge: daab033be527 a28046e21530 Author: Eric Gallager Date: Sun Jul 7 16:23:30 2024 -0400 Merge branch 'gcc-mirror:master' into me/CI Diff: ChangeLog

[gcc(refs/users/egallager/heads/CI)] Merge branch 'gcc-mirror:master' into me/CI

https://gcc.gnu.org/g:12281baa3f02521c9ded0c55b42e94a07b80f9b7 commit 12281baa3f02521c9ded0c55b42e94a07b80f9b7 Merge: a90e7b4b5280 4e3c8257304c Author: Eric Gallager Date: Sat Apr 6 20:19:19 2024 -0400 Merge branch 'gcc-mirror:master' into me/CI Diff: ChangeLog

[gcc(refs/users/egallager/heads/CI)] Merge branch 'gcc-mirror:master' into me/CI

https://gcc.gnu.org/g:11b6e08fa680736f27e62d6507db446f46e013e6 commit 11b6e08fa680736f27e62d6507db446f46e013e6 Merge: 12281baa3f02 b909daa5b673 Author: Eric Gallager Date: Mon Apr 22 18:23:06 2024 -0400 Merge branch 'gcc-mirror:master' into me/CI Diff: ChangeLog

[gcc/egallager/heads/master] (1361 commits) Merge branch 'gcc-mirror:master' into me/master

The branch 'egallager/heads/master' was updated to point to: 2e9f317e1fd9... Merge branch 'gcc-mirror:master' into me/master It previously pointed to: 68dbebb95d94... Merge branch 'gcc-mirror:master' into me/master Diff: Summary of changes (added commits): ---