https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78658
Michael Meissner changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78639
Michael Meissner changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolution|---
: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: meissner at gcc dot gnu.org
Target Milestone: ---
Created attachment 40344
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=40344&action=edit
Sample test fil
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78823
Michael Meissner changed:
What|Removed |Added
Target||powerpc64-linux-gnu,
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70568
--- Comment #6 from Michael Meissner ---
*** Bug 78823 has been marked as a duplicate of this bug. ***
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78823
Michael Meissner changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70568
Michael Meissner changed:
What|Removed |Added
Known to work||4.8.5
Known to fail|
||2016-12-29
Assignee|unassigned at gcc dot gnu.org |meissner at gcc dot
gnu.org
Ever confirmed|0 |1
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70754
Michael Meissner changed:
What|Removed |Added
CC||meissner at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70754
Michael Meissner changed:
What|Removed |Added
Attachment #40429|0 |1
is obsolete|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71977
--- Comment #3 from Michael Meissner ---
Created attachment 40431
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=40431&action=edit
Proposed patch to fix the problem
Assignee: unassigned at gcc dot gnu.org
Reporter: meissner at gcc dot gnu.org
Target Milestone: ---
Two of the spec 2006 benchmarks (gamess and calculix) get errors when compiled
by recent trunk compilers with -mcpu=power9:
Error in gamess:
Error: insn does not satisfy its
gnu.org |meissner at gcc dot
gnu.org
Ever confirmed|0 |1
--- Comment #1 from Michael Meissner ---
A quick glance at the code, shows that the V4SImode register is a traditional
floating point register, but the splitter for vsx_extract__p9 requires
the register
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78900
Michael Meissner changed:
What|Removed |Added
Status|UNCONFIRMED |ASSIGNED
Last reconfirmed|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78900
--- Comment #1 from Michael Meissner ---
Created attachment 40432
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=40432&action=edit
Proposed patch to fix the problem
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78953
--- Comment #2 from Michael Meissner ---
Created attachment 40449
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=40449&action=edit
Proposed patch to fix the problem
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78953
--- Comment #3 from Michael Meissner ---
Author: meissner
Date: Wed Jan 4 04:32:48 2017
New Revision: 244044
URL: https://gcc.gnu.org/viewcvs?rev=244044&root=gcc&view=rev
Log:
[gcc]
2016-12-30 Michael Meissner
PR target/78900
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78900
--- Comment #2 from Michael Meissner ---
Author: meissner
Date: Wed Jan 4 04:32:48 2017
New Revision: 244044
URL: https://gcc.gnu.org/viewcvs?rev=244044&root=gcc&view=rev
Log:
[gcc]
2016-12-30 Michael Meissner
PR target/78900
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78900
--- Comment #3 from Michael Meissner ---
Fixed in trunk in subversion id 244044. I will hold the bug open until it is
checked into the GCC 6 branch.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78953
Michael Meissner changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70568
--- Comment #8 from Michael Meissner ---
Author: meissner
Date: Thu Jan 5 00:43:53 2017
New Revision: 244084
URL: https://gcc.gnu.org/viewcvs?rev=244084&root=gcc&view=rev
Log:
[gcc]
2017-01-04 Michael Meissner
PR target/71977
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71977
--- Comment #4 from Michael Meissner ---
Author: meissner
Date: Thu Jan 5 00:43:53 2017
New Revision: 244084
URL: https://gcc.gnu.org/viewcvs?rev=244084&root=gcc&view=rev
Log:
[gcc]
2017-01-04 Michael Meissner
PR target/71977
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78823
--- Comment #3 from Michael Meissner ---
Author: meissner
Date: Thu Jan 5 00:43:53 2017
New Revision: 244084
URL: https://gcc.gnu.org/viewcvs?rev=244084&root=gcc&view=rev
Log:
[gcc]
2017-01-04 Michael Meissner
PR target/71977
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79004
--- Comment #4 from Michael Meissner ---
This was caused by subversion id 237806 that added small integer support in
vector registers (32-bit on power8, 8/16-bit on power9). Unfortunately, the
IEEE 128-bit hardware support was not adjusted for s
||2017-01-06
Assignee|unassigned at gcc dot gnu.org |meissner at gcc dot
gnu.org
Ever confirmed|0 |1
: enhancement
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: meissner at gcc dot gnu.org
Target Milestone: ---
The code for doing ISA 3.0 conversions between integer types and _Float128 was
written before 64-bit integer types were
,
||wschmidt at gcc dot gnu.org
Assignee|unassigned at gcc dot gnu.org |meissner at gcc dot
gnu.org
Ever confirmed|0 |1
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79004
--- Comment #5 from Michael Meissner ---
Created attachment 40484
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=40484&action=edit
Proposed patch to fix the problem
It was decided to split PR target/79004 into 2 parts. This patch fixes th
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71977
--- Comment #5 from Michael Meissner ---
Created attachment 40494
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=40494&action=edit
Back port of patch to fix problem on GCC 6 branch
While it has been decided not to apply this improvement to
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71977
--- Comment #6 from Michael Meissner ---
Author: meissner
Date: Tue Jan 10 17:44:17 2017
New Revision: 244279
URL: https://gcc.gnu.org/viewcvs?rev=244279&root=gcc&view=rev
Log:
[gcc]
2017-01-10 Michael Meissner
Back port from trunk
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70568
--- Comment #9 from Michael Meissner ---
Author: meissner
Date: Tue Jan 10 17:44:17 2017
New Revision: 244279
URL: https://gcc.gnu.org/viewcvs?rev=244279&root=gcc&view=rev
Log:
[gcc]
2017-01-10 Michael Meissner
Back port from trunk
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78823
--- Comment #4 from Michael Meissner ---
Author: meissner
Date: Tue Jan 10 17:44:17 2017
New Revision: 244279
URL: https://gcc.gnu.org/viewcvs?rev=244279&root=gcc&view=rev
Log:
[gcc]
2017-01-10 Michael Meissner
Back port from trunk
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71977
Michael Meissner changed:
What|Removed |Added
Attachment #40494|0 |1
is obsolete|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71977
Michael Meissner changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71977
Bug 71977 depends on bug 70568, which changed state.
Bug 70568 Summary: [5/6/7 regression] PowerPC64: union of floating and fixed
doesn't use POWER8 GPR/VSR moves
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70568
What|Removed
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70568
Michael Meissner changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
|unassigned at gcc dot gnu.org |meissner at gcc dot
gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78900
--- Comment #4 from Michael Meissner ---
Author: meissner
Date: Tue Jan 10 20:03:00 2017
New Revision: 244285
URL: https://gcc.gnu.org/viewcvs?rev=244285&root=gcc&view=rev
Log:
2017-01-10 Michael Meissner
Backport from mainline
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79004
--- Comment #6 from Michael Meissner ---
Author: meissner
Date: Thu Jan 12 22:02:57 2017
New Revision: 244386
URL: https://gcc.gnu.org/viewcvs?rev=244386&root=gcc&view=rev
Log:
[gcc]
2017-01-12 Michael Meissner
PR target/79004
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79004
--- Comment #7 from Michael Meissner ---
Author: meissner
Date: Wed Jan 18 00:35:29 2017
New Revision: 244561
URL: https://gcc.gnu.org/viewcvs?rev=244561&root=gcc&view=rev
Log:
2017-01-17 Michael Meissner
PR target/79004
* gc
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79004
Michael Meissner changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolution|---
Assignee: unassigned at gcc dot gnu.org
Reporter: meissner at gcc dot gnu.org
Target Milestone: ---
Created attachment 40540
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=40540&action=edit
Sample code that should be optimized.
In config/rs6000/rs6000.c is a f
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55598
Michael Meissner changed:
What|Removed |Added
Status|UNCONFIRMED |RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69738
Michael Meissner changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58452
Michael Meissner changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78604
--- Comment #6 from Michael Meissner ---
Unless -ffast-math or -fno-honor-nans is used, you cannot invert < to >=,
because you will get a different result if either operand is a NaN. However,
the basic code for vector compares hasn't changed muc
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70179
Michael Meissner changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70179
--- Comment #3 from Michael Meissner ---
I suspect the bug was fixed in a check in on May 2nd, 2016, when the complex
float128 was supported.
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: meissner at gcc dot gnu.org
Target Milestone: ---
I was looking at the code generated for:
double x, y
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79202
Michael Meissner changed:
What|Removed |Added
Status|UNCONFIRMED |NEW
Last reconfirmed|
ity: enhancement
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: meissner at gcc dot gnu.org
Target Milestone: ---
In looking at PR 79038, I noticed that the double/float conversions to
int/unsigned int were never modified when SIm
gnu.org |meissner at gcc dot
gnu.org
Ever confirmed|0 |1
||2017-01-25
Assignee|unassigned at gcc dot gnu.org |meissner at gcc dot
gnu.org
Ever confirmed|0 |1
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79179
--- Comment #1 from Michael Meissner ---
Created attachment 40584
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=40584&action=edit
Proposed patch to fix the problem.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79179
--- Comment #2 from Michael Meissner ---
Author: meissner
Date: Thu Jan 26 04:16:11 2017
New Revision: 244917
URL: https://gcc.gnu.org/viewcvs?rev=244917&root=gcc&view=rev
Log:
[gcc]
2017-01-25 Michael Meissner
PR target/79179
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79179
Michael Meissner changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65482
--- Comment #3 from Michael Meissner ---
The -mallow-movmisalign option has always been a debug option. It was added in
the early power7 days. However, after benchmarking, we discovered that vectors
of 32-bit elements (i.e. vector int and vecto
: enhancement
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: meissner at gcc dot gnu.org
Target Milestone: ---
In looking at the code generated for vec_insert, except for vec_insert of
64-bit items (i.e. long long, long on 64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79251
Michael Meissner changed:
What|Removed |Added
Priority|P3 |P5
CC|
: enhancement
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: meissner at gcc dot gnu.org
Target Milestone: ---
On PowerPC compiles with -mcpu=power8, if you do a vec_insert on vector types
that have 8, 16, or 32-bit element sizes (i.e
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79251
--- Comment #1 from Michael Meissner ---
Created attachment 40595
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=40595&action=edit
File to show various vector inserts
Compile this file with -O2 -mcpu=power9 (or -O2 -mcpu=power8), and look
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79251
Michael Meissner changed:
What|Removed |Added
Status|UNCONFIRMED |NEW
Last reconfirmed|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79252
--- Comment #1 from Michael Meissner ---
Created attachment 40594
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=40594&action=edit
Test case to show the various vec_inserts
Compile this code with -O2 -mcpu=power8, and look at the various
v
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79202
--- Comment #4 from Michael Meissner ---
Created attachment 40609
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=40609&action=edit
Proposed patch to fix the problem.
This patch is believed to fix the following PRs
* target/79038 (__float
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79203
--- Comment #1 from Michael Meissner ---
Created attachment 40610
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=40610&action=edit
Proposed patch to fix the problem.
This patch is believed to fix the following PRs
* target/79038 (__float
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79038
--- Comment #1 from Michael Meissner ---
Created attachment 40611
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=40611&action=edit
Proposed patch to fix the problem.
This patch is believed to fix the following PRs
* target/79038 (__float
||2017-01-30
CC||meissner at gcc dot gnu.org
Assignee|unassigned at gcc dot gnu.org |meissner at gcc dot
gnu.org
Ever confirmed|0 |1
--- Comment #2 from Michael Meissner ---
It is a real
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79197
--- Comment #8 from Michael Meissner ---
I agree the expander should call gpc_reg_operand and not reg_operand. This is
due to the fact that on PowerPCs with separate floating point registers, SFmode
is represented internally as DFmode when it is
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79038
--- Comment #2 from Michael Meissner ---
Author: meissner
Date: Tue Jan 31 13:38:35 2017
New Revision: 245059
URL: https://gcc.gnu.org/viewcvs?rev=245059&root=gcc&view=rev
Log:
2017-01-31 Michael Meissner
PR target/78597
PR t
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78597
--- Comment #3 from Michael Meissner ---
Author: meissner
Date: Tue Jan 31 13:38:35 2017
New Revision: 245059
URL: https://gcc.gnu.org/viewcvs?rev=245059&root=gcc&view=rev
Log:
2017-01-31 Michael Meissner
PR target/78597
PR t
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79038
--- Comment #3 from Michael Meissner ---
Subversion id 245059 fixes the majority of the issues. However, there are some
enhancements that should be added for GCC 8:
1) Add support for converting IEEE 128-bit floating point to/from char/short
da
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78597
Michael Meissner changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79295
--- Comment #2 from Michael Meissner ---
Yes, bcdadd requires all of its arguments to be altivec registers.
However, the pattern below is wrong:
(define_insn "bcd"
[(set (match_operand:V1TI 0 "register_operand" "")
(unspec:V1TI [(matc
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79295
Michael Meissner changed:
What|Removed |Added
Status|UNCONFIRMED |NEW
Last reconfirmed|
at gcc dot gnu.org|meissner at gcc dot
gnu.org
||meissner at gcc dot gnu.org
Assignee|unassigned at gcc dot gnu.org |meissner at gcc dot
gnu.org
gcc dot gnu.org|unassigned at gcc dot
gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66144
--- Comment #4 from Michael Meissner ---
Created attachment 40657
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=40657&action=edit
Potential patch to do the optimization
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66144
Michael Meissner changed:
What|Removed |Added
Attachment #40657|0 |1
is obsolete|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66144
--- Comment #6 from Michael Meissner ---
Created attachment 40660
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=40660&action=edit
Replacement proposed patch
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78303
--- Comment #1 from Michael Meissner ---
The problem is the tests use initialization (both static and auto
initialization). Unfortunately, when initializing a vector, the -maltivec=be
option is not checked when laying out the structure in memory
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66144
--- Comment #7 from Michael Meissner ---
Author: meissner
Date: Mon Feb 6 21:07:37 2017
New Revision: 245222
URL: https://gcc.gnu.org/viewcvs?rev=245222&root=gcc&view=rev
Log:
[gcc]
2017-02-06 Michael Meissner
PR target/66144
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66144
Michael Meissner changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68163
--- Comment #1 from Michael Meissner ---
Created attachment 40691
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=40691&action=edit
Proposed patch to fix the problem.
I believe this patch fixes the problem.
Note, I am going on vacation, an
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79038
Michael Meissner changed:
What|Removed |Added
Attachment #40611|0 |1
is obsolete|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79439
Michael Meissner changed:
What|Removed |Added
CC||meissner at gcc dot gnu.org
|unassigned at gcc dot gnu.org |meissner at gcc dot
gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79439
Michael Meissner changed:
What|Removed |Added
Attachment #40851|0 |1
is obsolete|
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79439
--- Comment #10 from Michael Meissner ---
Author: meissner
Date: Wed Mar 1 18:33:21 2017
New Revision: 245813
URL: https://gcc.gnu.org/viewcvs?rev=245813&root=gcc&view=rev
Log:
[gcc]
2017-03-01 Michael Meissner
PR target/79439
Assignee: unassigned at gcc dot gnu.org
Reporter: meissner at gcc dot gnu.org
Target Milestone: ---
At the moment, we do not have special code on power9 to have vec_insert of
single precision floating point.
So for:
vector float insert_0 (vector float vf, float f) { return
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79439
--- Comment #11 from Michael Meissner ---
Author: meissner
Date: Mon Mar 6 22:47:03 2017
New Revision: 245930
URL: https://gcc.gnu.org/viewcvs?rev=245930&root=gcc&view=rev
Log:
[gcc]
2017-03-06 Michael Meissner
Back port from trunk
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79439
--- Comment #12 from Michael Meissner ---
Author: meissner
Date: Fri Mar 10 20:53:18 2017
New Revision: 246058
URL: https://gcc.gnu.org/viewcvs?rev=246058&root=gcc&view=rev
Log:
[gcc]
2017-03-10 Michael Meissner
Back port from trunk
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79439
Michael Meissner changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolution|---
||2017-03-14
Assignee|unassigned at gcc dot gnu.org |meissner at gcc dot
gnu.org
Ever confirmed|0 |1
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79947
--- Comment #3 from Michael Meissner ---
The problem is the -mno-powerpc-gfxopt option disables floating point
conditional moves, which is needed to use the floating point reciprocal
estimate instructions.
The macro TARGET_FRSQRTES did not have
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79947
--- Comment #4 from Michael Meissner ---
Created attachment 40976
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=40976&action=edit
Proposed patch to fix the problem
The tARGET_RSQRTES macro needed a guard to require -mpowerpc-gfxopt.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79947
--- Comment #5 from Michael Meissner ---
Author: meissner
Date: Wed Mar 15 00:25:10 2017
New Revision: 246150
URL: https://gcc.gnu.org/viewcvs?rev=246150&root=gcc&view=rev
Log:
[gcc]
2017-03-14 Michael Meissner
PR target/79947
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71294
--- Comment #13 from Michael Meissner ---
FWIW, it does not fail for -mcpu=power7 or -mcpu=power9. If you use
-mcpu=power7, there is no direct move. If you use -mcpu=power9, the MTVSRDD
instruction is generated which bypasses the part that is f
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71294
--- Comment #16 from Michael Meissner ---
You need power8 support for the bug to show itself. In order to have power8
(ISA 2.07) support, you need a binutils that supports at least the power8
instructions.
|unassigned at gcc dot gnu.org |meissner at gcc dot
gnu.org
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