https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66144
--- Comment #7 from Michael Meissner <meissner at gcc dot gnu.org> --- Author: meissner Date: Mon Feb 6 21:07:37 2017 New Revision: 245222 URL: https://gcc.gnu.org/viewcvs?rev=245222&root=gcc&view=rev Log: [gcc] 2017-02-06 Michael Meissner <meiss...@linux.vnet.ibm.com> PR target/66144 * config/rs6000/vector.md (vcond<mode><mode>): Allow the true and false values to be constant vectors with all 0 or all 1 bits set. (vcondu<mode><mode>): Likewise. * config/rs6000/predicates.md (vector_int_reg_or_same_bit): New predicate. (fpmask_comparison_operator): Update comment. (vecint_comparison_operator): New predicate. * config/rs6000/rs6000.c (rs6000_emit_vector_cond_expr): Optimize vector conditionals when the true and false values are constant vectors with all 0 bits or all 1 bits set. [gcc/testsuite] 2017-02-06 Michael Meissner <meiss...@linux.vnet.ibm.com> PR target/66144 * gcc.target/powerpc/pr66144-1.c: New test. * gcc.target/powerpc/pr66144-2.c: Likewise. * gcc.target/powerpc/pr66144-3.c: Likewise. Added: trunk/gcc/testsuite/gcc.target/powerpc/pr66144-1.c trunk/gcc/testsuite/gcc.target/powerpc/pr66144-2.c trunk/gcc/testsuite/gcc.target/powerpc/pr66144-3.c Modified: trunk/gcc/ChangeLog trunk/gcc/config/rs6000/predicates.md trunk/gcc/config/rs6000/rs6000.c trunk/gcc/config/rs6000/vector.md trunk/gcc/testsuite/ChangeLog
