https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78900
--- Comment #2 from Michael Meissner <meissner at gcc dot gnu.org> --- Author: meissner Date: Wed Jan 4 04:32:48 2017 New Revision: 244044 URL: https://gcc.gnu.org/viewcvs?rev=244044&root=gcc&view=rev Log: [gcc] 2016-12-30 Michael Meissner <meiss...@linux.vnet.ibm.com> PR target/78900 * config/rs6000/rs6000.c (rs6000_split_signbit): Change some assertions. Add support for doing the signbit if the IEEE 128-bit floating point value is in a GPR. * config/rs6000/rs6000.md (Fsignbit): Delete. (signbit<mode>2_dm): Delete using <Fsignbit> and just use "wa". Update the length attribute if the value is in a GPR. (signbit<mode>2_dm_<su>ext): Add combiner pattern to eliminate the sign or zero extension instruction, since the value is always 0/1. (signbit<mode>2_dm2): Delete using <Fsignbit>. 2017-01-03 Michael Meissner <meiss...@linux.vnet.ibm.com> PR target/78953 * config/rs6000/vsx.md (vsx_extract_<mode>_store_p9): If we are extracting SImode to a GPR register so that we can generate a store, limit the vector to be in a traditional Altivec register for the vextuwrx instruction. [gcc/testsuite] 2017-01-03 Michael Meissner <meiss...@linux.vnet.ibm.com> PR target/78953 * gcc.target/powerpc/pr78953.c: New test. Added: trunk/gcc/testsuite/gcc.target/powerpc/pr78953.c Modified: trunk/gcc/ChangeLog trunk/gcc/config/rs6000/rs6000.c trunk/gcc/config/rs6000/rs6000.md trunk/gcc/config/rs6000/vsx.md trunk/gcc/testsuite/ChangeLog
