[Bug target/120930] [16 Regression] RISC-V: Miscompile at -O[23] with zvl256b -mrvv-vector-bits=zvl since r16-1645-g309dbcea2ca

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120930 Jeffrey A. Law changed: What|Removed |Added CC||skothadiya at whileone dot in --- Comm

[Bug target/122124] [16 Regression] RISC-V rv64gcv: miscompile at -O0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122124 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Blocks|120763

[Bug target/121845] [Trunk] RISC-V rv64gcv: miscompile at -O0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121845 --- Comment #3 from Jeffrey A. Law --- I've pushed Robin's patch to the trunk. What I don't know is whether or not this likely affects gcc-15, in which case we should add the regressinon marker and backport in a week or so. Robin, any sense of

[Bug target/122147] [16 Regression] ICE: maximum number of generated reload insns per insn achieved (90) with -O2 -march=rv64gcv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122147 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/120782] RISC-V: vector-strict-align not working for spec17 521 ref size

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120782 --- Comment #9 from Jeffrey A. Law --- In response to c#8, yes the alignment data attached to a MEM should be conservatively correct.

[Bug tree-optimization/117760] `a != b` implies that a or b is also non-zero

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117760 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/118945] RISC-V: VSETL pass: Don't promote Vectors ops from Tail agnostic to Tail Undisturbed

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118945 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/122114] [16 regression] ICE when building libgcrypt-1.11.2 on riscv with -fstack-clash-protection (in to_constant, at poly-int.h:592)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122114 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/121742] [15] RISC-V rv64gcv: miscompile at -O1/O2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121742 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/120763] [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763 Bug 120763 depends on bug 110812, which changed state. Bug 110812 Summary: Check availability of builtins at expand time https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110812 What|Removed |Added -

[Bug target/110812] Check availability of builtins at expand time

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110812 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/122147] [16 Regression] ICE: maximum number of generated reload insns per insn achieved (90) with -O2 -march=rv64gcv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122147 Jeffrey A. Law changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |law at gcc dot gnu.org

[Bug target/122076] [RISCV] [Miscompile] GCC - riscv64 target, miscompiles at -O3 as well as -O2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122076 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/120763] [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763 Bug 120763 depends on bug 121995, which changed state. Bug 121995 Summary: [RISCV] [Miscompile] GCC - riscv64 target, miscompiles with multiplication on unsigned char at -O3 as well as -O2 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121995

[Bug target/122147] [16 Regression] ICE: maximum number of generated reload insns per insn achieved (90) with -O2 -march=rv64gcv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122147 --- Comment #1 from Jeffrey A. Law --- Probably the (subreg (mem ... )) created by combine that causes the problems: Trying 7 -> 14: 7: r134:V2QI=[r140:DI] REG_DEAD r140:DI 14: r138:HF=r134:V2QI#0 REG_DEAD r134:V2QI Successfu

[Bug target/122102] [16 Regression] [RISCV] [Miscompile] GCC - riscv64 target, miscompiles at -O3 as well as -O2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122102 --- Comment #8 from Jeffrey A. Law --- *** Bug 121995 has been marked as a duplicate of this bug. ***

[Bug target/121995] [RISCV] [Miscompile] GCC - riscv64 target, miscompiles with multiplication on unsigned char at -O3 as well as -O2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121995 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |DUPLICATE Status|UNCONFIRM

[Bug target/120763] [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763 Bug 120763 depends on bug 122076, which changed state. Bug 122076 Summary: [RISCV] [Miscompile] GCC - riscv64 target, miscompiles at -O3 as well as -O2 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122076 What|Removed

[Bug target/122102] [16 Regression] [RISCV] [Miscompile] GCC - riscv64 target, miscompiles at -O3 as well as -O2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122102 --- Comment #7 from Jeffrey A. Law --- *** Bug 122076 has been marked as a duplicate of this bug. ***

[Bug rtl-optimization/101188] [13 Regression] [postreload] Uses content of a clobbered register

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101188 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/122124] [Trunk] RISC-V rv64gcv: miscompile at -O0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122124 Jeffrey A. Law changed: What|Removed |Added CC||rzinsly at ventanamicro dot com --- Co

[Bug target/122124] [Trunk] RISC-V rv64gcv: miscompile at -O0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122124 Jeffrey A. Law changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed|

[Bug target/121845] [Trunk] RISC-V rv64gcv: miscompile at -O0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121845 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |NEW Ever confirmed|0

[Bug target/120763] [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763 Bug 120763 depends on bug 121742, which changed state. Bug 121742 Summary: [15] RISC-V rv64gcv: miscompile at -O1/O2 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121742 What|Removed |Added -

[Bug target/121780] [Trunk] RISC-V rv64gcv: miscompile at -O1

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121780 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/120763] [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763 Bug 120763 depends on bug 121780, which changed state. Bug 121780 Summary: [Trunk] RISC-V rv64gcv: miscompile at -O1 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121780 What|Removed |Added -

[Bug target/122147] [16 Regression] ICE: maximum number of generated reload insns per insn achieved (90) with -O2 -march=rv64gcv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122147 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/120763] [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763 Bug 120763 depends on bug 121937, which changed state. Bug 121937 Summary: [16 Regression] RISC-V rv64gcv: crash at -O3 during RTL pass: combine https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121937 What|Removed

[Bug target/121937] [16 Regression] RISC-V rv64gcv: crash at -O3 during RTL pass: combine

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121937 Jeffrey A. Law changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug tree-optimization/53947] [meta-bug] vectorizer missed-optimizations

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53947 Bug 53947 depends on bug 120378, which changed state. Bug 120378 Summary: Support narrowing clip idiom https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120378 What|Removed |Added

[Bug middle-end/26163] [meta-bug] missed optimization in SPEC (2k17, 2k and 2k6 and 95)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=26163 Bug 26163 depends on bug 120378, which changed state. Bug 120378 Summary: Support narrowing clip idiom https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120378 What|Removed |Added

[Bug middle-end/120378] Support narrowing clip idiom

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120378 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/118840] RISC-V: current rv64gcv testsuite failures as of r15-7464-g30a3a557a54

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118840 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |WONTFIX Status|UNCONFIRMED

[Bug target/113362] RISCV64 divide and remainder with the same operands generates two divide operations

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113362 Jeffrey A. Law changed: What|Removed |Added Status|NEW |SUSPENDED

[Bug target/105870] Asan cannot work correctly for RISC-V GCC

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105870 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/105330] Asan cannot work correctly for RISC-V GCC

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105330 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/121973] [trunk, RV64] Poor quality (useless, harmless) code is added to naked functions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121973 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/121652] [15 Regression] round builtin does not raise FE_INVALID for signaling NaN

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121652 Jeffrey A. Law changed: What|Removed |Added Summary|[15/16 Regression] round|[15 Regression] round

[Bug target/118945] RISC-V: VSETL pass: Don't promote Vectors ops from Tail agnostic to Tail Undisturbed

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118945 --- Comment #13 from Jeffrey A. Law --- wrt c#12, clearly it's not moving fast enough. So once your patch is approved by Robin we'll integrate it and close out this BZ. Thanks for picking this up Zhongyao!

[Bug target/121937] [16 Regression] RISC-V rv64gcv: crash at -O3 during RTL pass: combine

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121937 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Ever confirmed|0

[Bug target/122051] ICE: in validate_change_or_fail, at config/riscv/riscv-v.cc:6011 with -mrvv-vector-bits=zvl -mcpu=xt-c920

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122051 Jeffrey A. Law changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/122106] ICE: in expand_reversed_crc_table_based, at expr.cc:14704 with __builtin_rev_crc16_data16()

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122106 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/122102] [16 Regression] [RISCV] [Miscompile] GCC - riscv64 target, miscompiles at -O3 as well as -O2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122102 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/122051] ICE: in validate_change_or_fail, at config/riscv/riscv-v.cc:6011 with -mrvv-vector-bits=zvl -mcpu=xt-c920

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122051 Jeffrey A. Law changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |law at gcc dot gnu.org Ever

[Bug target/110812] Check availability of builtins at expand time

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110812 --- Comment #35 from Jeffrey A. Law --- Not only that, hiway is too painfully slow to build that it would blow up testing times beyond all usefullness. As Sam noted, we reduce regressions from hiway and include those. We also rely on the likes

[Bug tree-optimization/122086] [16 regression] gcc.target/riscv/cmo-zicboz-zic64-1.c fails after r16-4081

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122086 --- Comment #1 from Jeffrey A. Law --- Adding Edwin and Robin for awareness as it's virtually certain this is going to be triggering failures in the RV CI system across many tests. My tester is currently flaging 125-150 regressions related to t

[Bug target/122106] ICE: in expand_reversed_crc_table_based, at expr.cc:14704 with __builtin_rev_crc16_data16()

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122106 Jeffrey A. Law changed: What|Removed |Added Ever confirmed|0 |1 Status|UNCONFIRMED

[Bug target/122108] [M68K][Fixed-Point] Wrong stack pointer update after function call

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122108 Jeffrey A. Law changed: What|Removed |Added Last reconfirmed||2025-10-01 Status|UNCONFIR

[Bug middle-end/111875] With -Og ubsan check inserted even though __builtin_assume_aligned guarantees no UB

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111875 --- Comment #9 from Jeffrey A. Law --- Note we may be seeing the same core issue showing up outside the sanitizer context. My tester flagged this on sh3eb-linux-gnu Tests that now fail, but worked before (4 tests): gcc: gcc.target/sh/cmpstr.c

[Bug target/121778] Improve rotation detection for RISC-V

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121778 --- Comment #5 from Jeffrey A. Law --- Yea, I don't see a great target in the rv64 dumps. As far as the patch itself. I'd bet we want to change all those SIs to X so that it works on rv64 on a comparable testcase like: unsigned long test_011

[Bug target/121983] [16 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1946 with -O2 -mcpu=xiangshan-nanhu

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121983 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/121985] [RISCV] [Miscompile] GCC - riscv64 target, miscompiles at -O3 as well as -O2 on valid code

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121985 --- Comment #5 from Jeffrey A. Law --- Somehow ranger is mucking things up. === BB 2 Imports: var_8 Exports: var_8 [local count: 153437704]: var_8 = f; pretmp_23 = a; if (var_8 <= 5) goto ; [85.7

[Bug target/121983] [16 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1946 with -O2 -mcpu=xiangshan-nanhu

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121983 Jeffrey A. Law changed: What|Removed |Added Last reconfirmed||2025-09-18 Status|UNCONFIR

[Bug target/121910] RISC-V: dynamic lmul choosing wrong vector mode

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121910 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/121982] [16 Regression] ICE: in riscv_sched_variable_issue, at config/riscv/riscv.cc:10236 with -mcpu=tt-ascalon-d8 -flive-range-shrinkage and vector division

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121982 Jeffrey A. Law changed: What|Removed |Added Assignee|law at gcc dot gnu.org |bergner at gcc dot gnu.org ---

[Bug target/121985] [RISCV] [Miscompile] GCC - riscv64 target, miscompiles at -O3 as well as -O2 on valid code

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121985 Jeffrey A. Law changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |law at gcc dot gnu.org --- Comm

[Bug target/121512] internal compiler error: in generate_insn, at config/riscv/riscv-vector-builtins.cc:4470

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121512 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/110812] Check availability of builtins at expand time

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110812 --- Comment #31 from Jeffrey A. Law --- *** Bug 121512 has been marked as a duplicate of this bug. ***

[Bug target/120763] [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763 Bug 120763 depends on bug 121512, which changed state. Bug 121512 Summary: internal compiler error: in generate_insn, at config/riscv/riscv-vector-builtins.cc:4470 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121512 What|Removed

[Bug tree-optimization/58727] Sub-optimal code for bit clear/set sequence

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58727 --- Comment #7 from Jeffrey A. Law --- So part of the problem here is the ARM and x86 ports will accept the "simplified" constant in their AND patterns. The ARM port will eventually split it into components, but by then it's too late to clean th

[Bug c++/121889] [16 regression] ice in discriminator_for_local_entity, at cp/mangle.cc:2293

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121889 --- Comment #4 from Jeffrey A. Law --- Doesn't really make much sense to me. Your error is way up in the front-end while the fusion change is deep in the RTL pipeline.

[Bug middle-end/108016] RISC-V：Bad codegen in scalar code comparing to LLVM

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108016 --- Comment #15 from Jeffrey A. Law --- WRT c#14. Yes, if had a stack object and the references to it go away during the later optimization phases, then the useless stack adjustments will be left lying around. I don't have the PR for that prob

[Bug target/120811] RISC-V: missed load offset

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120811 --- Comment #10 from Jeffrey A. Law --- Just a quick update. We're seeing really good results with Shreya's in-flight work. Hoping to test cactusBSSN on design this week.

[Bug target/121652] [15/16 Regression] round builtin does not raise FE_INVALID for signaling NaN

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121652 --- Comment #16 from Jeffrey A. Law --- WRT c#13, yes, it's worth it, the performance gains were huge. Of course if we look out Zfa should become ubiquitious and that other path won't matter. But we're not at that point yet IMHO.

[Bug tree-optimization/57650] Suboptimal code after TRUTH_AND_EXPR is changed into BIT_AND_EXPR

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=57650 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment #5 f

[Bug tree-optimization/121660] [16 Regression] RISC-V: internal compiler error: in apply_scale, at profile-count.h:1187

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121660 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |DUPLICATE Status|UNCONFIRM

[Bug target/120763] [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763 Bug 120763 depends on bug 121660, which changed state. Bug 121660 Summary: [16 Regression] RISC-V: internal compiler error: in apply_scale, at profile-count.h:1187 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121660 What|Removed

[Bug tree-optimization/121523] [16 Regression] RISC-V: ICE in apply_scale, at profile-count.h:1187 since r16-3065-geee51f9a4b6

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121523 Jeffrey A. Law changed: What|Removed |Added CC||skothadiya at whileone dot in --- Comm

[Bug target/121778] New: Improve rotation detection for RISC-V

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121778 Bug ID: 121778 Summary: Improve rotation detection for RISC-V Product: gcc Version: 16.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug target/65266] [SH] Use rotcl for bit reversals

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65266 --- Comment #1 from Jeffrey A. Law --- So I took at peek at this as it looked like it might be an interesting missed optimization case for one my interns.

[Bug target/121213] Poor RV64 code generated for __atomic_exchange_n (llvm seems to do it right)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121213 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/121548] [15 Regression] ICE: SIGSEGV in satisfies_constraint_vu (constraints.md:199) with -O -mrvv-vector-bits=zvl -march=rv64gv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121548 Jeffrey A. Law changed: What|Removed |Added Blocks|120763 | Status|NEW

[Bug tree-optimization/121753] New: [16 Regression] Recent vectorizer changes causes ICE in vect_build_slp_tree_2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121753 Bug ID: 121753 Summary: [16 Regression] Recent vectorizer changes causes ICE in vect_build_slp_tree_2 Product: gcc Version: 16.0 Status: UNCONFIRMED Severity:

[Bug target/89828] Inernal compiler error on -fno-omit-frame-pointer

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89828 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug ipa/99951] Dead return value after modify_call() is not released

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99951 Jeffrey A. Law changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug tree-optimization/101822] Codegen bug for popcount

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101822 Bug 101822 depends on bug 7, which changed state. Bug 7 Summary: Missed optimisation with -Os https://gcc.gnu.org/bugzilla/show_bug.cgi?id=7 What|Removed |Added -

[Bug tree-optimization/99997] Missed optimisation with -Os

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=7 Jeffrey A. Law changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug tree-optimization/99997] Missed optimisation with -Os

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=7 --- Comment #8 from Jeffrey A. Law --- Seems to be fixed on the trunk.

[Bug target/121548] [15 Regression] ICE: SIGSEGV in satisfies_constraint_vu (constraints.md:199) with -O -mrvv-vector-bits=zvl -march=rv64gv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121548 Jeffrey A. Law changed: What|Removed |Added Summary|[15/16 Regression] ICE: |[15 Regression] ICE:

[Bug tree-optimization/65964] [meta-bug] Operand Shortening

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65964 Bug 65964 depends on bug 14617, which changed state. Bug 14617 Summary: [tree-ssa] suboptimal code ('0' <= c && c <= '9') ? c - '0' : 0 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=14617 What|Removed |Added ---

[Bug tree-optimization/14617] [tree-ssa] suboptimal code ('0' <= c && c <= '9') ? c - '0' : 0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=14617 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug target/17108] Store with update not generated for a simple loop

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=17108 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug middle-end/117169] Missed opportunity to combine sign and bitmask tests

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117169 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug tree-optimization/118037] missing unswitch loops with RISCV intrinsics

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118037 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/121213] Poor RV64 code generated for __atomic_exchange_n (llvm seems to do it right)

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121213 --- Comment #6 from Jeffrey A. Law --- And you'll note the bug is still open and that Austin explicitly indicated the redundant sign extend is still in there. That's a separate issue that needs a completely different approach to solve.

[Bug target/121268] RISC-V: Possible optimization when manipulating rightmost bits with zbb enabled

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121268 Jeffrey A. Law changed: What|Removed |Added Blocks|120763 | --- Comment #2 from Jeffrey A. Law -

[Bug target/121548] [15/16 Regression] ICE: SIGSEGV in satisfies_constraint_vu (constraints.md:199) with -O -mrvv-vector-bits=zvl -march=rv64gv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121548 --- Comment #1 from Jeffrey A. Law --- It looks like we're unconditionally trying to get the merge_op_idx on an insn that doesn't support that: (insn 16 15 17 2 (set (subreg:V1DF (reg:RVVM1DF 149 [ _4 ]) 0) (mem:V1DF (reg/f:DI 151 [ q

[Bug target/121548] [15/16 Regression] ICE: SIGSEGV in satisfies_constraint_vu (constraints.md:199) with -O -mrvv-vector-bits=zvl -march=rv64gv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121548 Jeffrey A. Law changed: What|Removed |Added Last reconfirmed||2025-08-25 Ever confirmed|0

[Bug tree-optimization/121656] [16 regression] wrong code at -O{1,2,3} on x86_64-linux-gnu

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121656 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/120811] RISC-V: missed load offset

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120811 --- Comment #9 from Jeffrey A. Law --- Costing should prevent mvconst_internal from causing problems in this case. >From the compiler's current cost model mvconst_internal+add has the same cost as addi+addi. So there's no reason for combine to

[Bug target/121498] long branches requires ra register but not modeled; causes issues sometimes with shrink wrapping and/or leaf functions

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121498 --- Comment #11 from Jeffrey A. Law --- I still need to throw it under a debugger, but I suspect it's the whole prologue/epilogue shrink wrapping that's the problem here. The component based shrink wrapping code excludes RA. Assuming that's th

[Bug target/120553] Improve code to select between -1 and various values

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120553 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug tree-optimization/121523] [16 Regression] RISC-V: ICE in apply_scale, at profile-count.h:1187 since r16-3065-geee51f9a4b6

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121523 Jeffrey A. Law changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed|

[Bug target/120763] [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763 Bug 120763 depends on bug 120141, which changed state. Bug 120141 Summary: [RVV] Noop are not removed https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120141 What|Removed |Added

[Bug target/120141] [RVV] Noop are not removed

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120141 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |WONTFIX Status|NEW

[Bug target/117421] [RISCV] Use byte comparison instead of word comparison

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117421 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |WAITING Ever confirmed|0

[Bug c/118618] RISC-V: Zcmp extension and RVV auto-vectorization are both enabled，the sp register error.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118618 Jeffrey A. Law changed: What|Removed |Added Blocks|120763 | Status|UNCONFIRMED

[Bug target/121538] RISC-V: Self tests broken for RV32EC with r16-3028-g0c517ddf9b136c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121538 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug target/121538] RISC-V: Self tests broken for RV32EC with r16-3028-g0c517ddf9b136c

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121538 --- Comment #3 from Jeffrey A. Law --- Fixed by Dimitar's patch on the trunk.

[Bug rtl-optimization/119275] ICE: in gen_lowpart_general, at rtlhooks.cc:57 with -O2 -march=rv64gv -mrvv-vector-bits=zvl

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119275 Jeffrey A. Law changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

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