https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118356
Jeffrey A. Law <law at gcc dot gnu.org> changed:
What |Removed |Added
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Status|NEW |WAITING
--- Comment #7 from Jeffrey A. Law <law at gcc dot gnu.org> ---
Right. The bits in place are the way they are so that each uarch known to GCC
can select the code aligments they want/need.
I don't have enough information to set suitable values for any uarch other than
the Ventana designs. The plan was to upstream the rest of the V1 bits which
would have been the first user of this capability, but once the V1 design was
shelved it didn't make sense to upstream any of the cost/scheduling bits for
it.
Someone with a deep understanding of a particular uarch needs to submit a patch
setting suitable values for that uarch.
That will almost certainly include certain tradeoffs based on where the uarch
is most likely going to be used. For example, deeply embedded where codesize
is particularly important likely won't want any code alignments. While other
uarchs (say targetting a server market) are going to be more likely to want
code alignments to improve performance, even if it means slightly larger
codesize.
Right now I don't see anything actionable here.
