Hi
I am writing a code generator for ARM64.
To access a global variable I was generating
addrp x0,someglobal
add x0,[x0,:lo12:someglobal]
This worked without any problems with gcc version 4.9.2 (Debian/Linaro
4.9.2-10) and GNU ld (GNU Binutils for Debian) 2.25.
I have updated m
Hi
I am getting this error:
GNU ld (GNU Binutils for Debian) 2.28
/usr/bin/ld: error.o: relocation R_AARCH64_ADR_PREL_PG_HI21 against
external symbol `stderr@@GLIBC_2.17' can not be used when making a
shared object; recompile with -fPIC
The problem is, I do NOT want to make a shared object!
Le 29/09/2017 à 13:22, Marc Glisse a écrit :
-no-pie probably.
YES!
It just did not occur to me, I should have figured out alone.
Thanks to all that answered.
jacob
When doing some tests with my ARM64 code generator, I saw the
performances of my software drop from 75% of gcc's speed to just 60%.
What was happening?
One of the reasons (besides the nullity of my code generator of course)
was that gcc cached the values of the global "table" in registers,
re
Le 05/11/2017 à 20:43, Jakub Jelinek a écrit :
A bug in the program that does that. You can use volatile, or atomics
(including e.g. relaxed __atomic_load, which isn't really expensive).
Yeah true. Maybe I will cache them in registers too, it is not very
difficult. Still, I think I will do i
Hi
I am confronted with a classical problem: a program gives correct
results when compiled with optimizations off, and gives the wrong ones
with optimization (-O2) on.
I have isolated the probem in a single file but now there is no way that
I can further track down the problem to one of the
Le 02/02/2018 à 22:11, Florian Weimer a écrit :
* jacob navia:
I have in my small C compiler introduced the following construct:
#pragma optimize(on/off,push/pop)
Not sure what you are after. GCC has something quite similar:
<https://gcc.gnu.org/onlinedocs/gcc/Function-Specific-Opt
I would like to know if the exception handling software has changed
between 4.1 and 4.3.
I have developed a module to generate gcc compatible dwarf debug info
and it works with gcc 4.1. It is in the context of a JIT.
Now I have some mysterious crashes with gcc 4.3 under Suse 11.
Ubuntu seems to
Hi
I have developed a JIT for linux 64 bits. It generates exception
handling information
according to DWARF under linux and it works with gcc 4.2.1.
I have recompiled the same code under the Macintosh and something has
changed,
apparently, because now any throw that passes through my code cr
Jack Howarth a écrit :
On Thu, Feb 04, 2010 at 08:12:10PM +0100, jacob navia wrote:
Hi
I have developed a JIT for linux 64 bits. It generates exception
handling information
according to DWARF under linux and it works with gcc 4.2.1.
I have recompiled the same code under the Macintosh
Jack Howarth a écrit :
Jacob,
Apple's gcc is based on their own branch and is not the
same as FSF gcc. The first FSF gcc that is validated on
on darwin10 was gcc 4.4. However I would suggest you first
start testing against current FSF gcc trunk. There are a
number of fixes for darwin10 that ar
Hi
We have an application compiled with gcc written in C++.
This application generates dynamically code and executes it, using a
JIT, a Just In time Compiler. Everything is working OK until the C++
code generates a throw.
To get to the corresponding catch, the runtime should skip through the
Daniel Jacobowitz a écrit :
On Tue, May 02, 2006 at 07:21:24PM -0700, Mike Stump wrote:
Otherwise, would it be possible to generate the DWARF Tables and
add those tables dynamically to the running program?
Yes (could require OS changes).
Under windows, Microsoft provides an AP
Tom Tromey a écrit :
"jacob" == jacob navia <[EMAIL PROTECTED]> writes:
jacob> This application generates dynamically code and executes it, using a
jacob> JIT, a Just In time Compiler. Everything is working OK until the C++
jacob> code generates a throw.
Andrew Haley a écrit :
Richard Henderson writes:
> On Tue, May 02, 2006 at 01:23:56PM +0200, jacob navia wrote:
> > Is there an equivalent API for linux?
>
> __register_frame_info_bases / __deregister_frame_info_bases.
Are these an exported API?
I metioned the existence
I can't explain myself what is going on within this lines in
the .debug_frame section.
Context: AMD64 linux64 system. (Ubuntu)
Within the debug_frame section I find the following assembly instructions:
.byte0x4
.long.LCFI0-.LFB2
The distance between labels LCFI0 and LFB2 is exactl
How to reproduce this problem
-
1) Take some C file. I used for instance dwarf.c from
the new binutils distribution.
2) Generate an assembler listing of this file
3) Using objdump -s dwarf.o I dump all the
sections of the executable in hexadecimal format.
Put the
Hi
I want to use the function
__register_frame_info
to dynamically register DWARF2 unwind frames.
Where is the library I should link with??
Environment: linux 64 bits
Thanks in advance
Jacob
P.S. I have posted some messages here before, concerning this problem.
I had to do a long rewritin
Hi
I have now everything in place for dynamically register the
debug frame information that my JIT (Just in time compiler)
generates.
I generate a CIE (Common information block), followed by
a series of FDE (Frame Description Entries) describing
each stack frame. The binary code is the same as g
Hi
Bug in the specs or bug in the code?
I do not know, but one of this is wrong:
In the Linux Standard specs in
http://www.freestandards.org/spec/booksets/LSB-Core-generic/LSB-Core-generic/ehframechpt.html
it is written in the specification of the FDE (Frame Description Entry)
the following:
Hi
Context:
I am writing a JIT and need to register the frame information about
the generated program within the context of a larger C++ program
compiled with g++. Stack layout is like this:
catch established by C++
JITTED code generated dynamically
JITTED code
JITTE
Andrew Haley wrote:
The way you do not reply to mails replying to your questions doesn't
encourage people to help you. Please try harder to answer.
I did answer last time but directly to the poster that replied, and
forgot to CC the list.
Excuse me for that.
I suspect that the gcc unwin
Daniel Jacobowitz wrote:
On Thu, Jul 13, 2006 at 04:46:19PM +0200, jacob navia wrote:
In the Linux Standard specs in
http://www.freestandards.org/spec/booksets/LSB-Core-generic/LSB-Core-generic/ehframechpt.html
it is written in the specification of the FDE (Frame Description Entry)
the
Daniel Jacobowitz wrote:
On Thu, Jul 13, 2006 at 05:06:25PM +0200, jacob navia wrote:
So, what happens when _Unwind_Find_registered_FDE is called? Does it
find the EH data you have registered?
Yes but then it stops there instead of going upwards and finding the catch!
It is as
Seongbae Park wrote:
The above code looks incorrect, for various reasons,
not the least of which is that you're assuming CIE/FDE are fixed-length.
This is a trivial thing I will add later.
There are various factors that affect FDE/CIE
depending on PIC/non-PIC, C or C++, 32bit/64bit, etc -
s
This is just to tell you that now it is working.
I have suceeded in making my JIT generate the right tables for gcc
As it seems, both gcc 4.1 and gcc 3.3 seem to work OK.
Can anyone confirm this?
There isn't any difference between gcc-3.x and gcc4.x at this
level isn't it?
jacob
Andrew Haley a écrit :
jacob navia writes:
> This is just to tell you that now it is working.
>
> I have suceeded in making my JIT generate the right tables for gcc
Excellent.
> As it seems, both gcc 4.1 and gcc 3.3 seem to work OK.
> Can anyone confirm this?
That they wo
64 bit risk CPU.
Availability:
$ git clone https://github.com/jacob-navia/tiny-asm
Building the tiny assembler:
$ gcc -o asm asm.c
There is no Makefile
In some machines, the obstack library is not a part of the libc. (Not linux,
Apple, for instance). For those machines obtsack.c is provided in
Dear Friends:
1) I have (of course) kept your copyright notice at the start of the « asm.h »
header file of my project.
2) I have published my source code using your GPL V3 license
I am not trying to steal you anything. And I would insist that I have great
respect for the people working with g
Hi
The assembler checks at each instruction if the instruction is within the
selected subset of risc-v extensions or not. I do not quite understand why this
check is done here.
I suppose that gcc, before emitting any instruction does this check too,
somewhere. Because if an instruction is emitt
Consider this code:
1202 static fragS * get_frag_for_reloc (fragS *last_frag,
1203 const segment_info_type *seginfo,
1204 const struct reloc_list *r)
1205 {
1206 fragS *f;
1207
1208 for (f = last_frag; f != NULL; f = f->fr_next)
1209 if (f->fr_address <= r->u.
Hi
When caculating the cos/sinus, gcc generates a call to a complicated
routine that takes several thousand instructions to execute.
Suppose the value is stored in some XMM register, say xmm0 and the
result should be in another xmm register, say xmm1.
Why it doesn't generate:
movsd
Le 11/05/13 11:20, Oleg Endo a écrit :
Hi,
This question is not appropriate for this mailing list.
Please take any further discussions to the gcc-help mailing list.
On Sat, 2013-05-11 at 11:15 +0200, jacob navia wrote:
Hi
When caculating the cos/sinus, gcc generates a call to a complicated
Le 11/05/13 11:30, Marc Glisse a écrit :
On Sat, 11 May 2013, jacob navia wrote:
Hi
When caculating the cos/sinus, gcc generates a call to a complicated
routine that takes several thousand instructions to execute.
Suppose the value is stored in some XMM register, say xmm0 and the
result
Le 11/05/13 16:01, Ondřej Bílka a écrit :
As 1) only way is measure that. Compile following an we will see who is
rigth.
cat "
#include
int main(){ int i;
double x=0;
double ret=0;
double f;
for(i=0;i<1000;i++){
ret+=sin(x);
x+=0.3;
}
return ret;
}
" > sin.c
Hi
Looking at the code generated by the riscv backend:
Consider this C source code:
void shup1(QfloatAccump x)
{
QELT newbits,bits;
int i;
bits = x->mantissa[9] >> 63;
x->mantissa[9] <<= 1;
for( i=8; i>0; i-- ) {
newbits = x->mantissa[i] >>
Hi
In a previous post I pointed to a strange code generation`by gcc in the
riscv-64 targets.
To resume:
Suppose a 64 bit operation: c = a OP b;
Gcc does the following:
Instead of loading 64 bits from memory gcc loads 8 bytes into 8
separate registers for both operands. Then it ORs
Hi
I have foujnd the reason for the weird behavior of gcc when reading 64 bits
data.
I found out how to avoid this. The performance of the generated code doubled.
I thank everyone in this forum for their silence to my repeated help requests.
They remind me that:
THE ENTIRE RISK AS TO THE QUAL
Hi
The GNU assembler supports two instructions for the T-Head risk machines called:
th.ipop
th.ipush
With no arguments. These instructions (they are no macros or aliases) are
UNDOCUMENTED in the T-Head instruction manuals that I have, and a google search
yields absolutely nothing.
Can anyone h
ards
> Alex
>
>> On Jan 23, 2024, at 8:42 AM, jacob navia via Gcc wrote:
>>
>> Hi
>> The GNU assembler supports two instructions for the T-Head risk machines
>> called:
>>
>> th.ipop
>> th.ipush
>>
>> With no arguments. Thes
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