Migrate the pagefault struct from xe_gt_pagefault.c to the
xe_gt_pagefault.h header file, along with the associated enum values.
v2: Normalize names for common header (Matt Brost)
Signed-off-by: Jonathan Cavitt
---
drivers/gpu/drm/xe/xe_gt_pagefault.c | 41 +---
drivers/
-Original Message-
From: Lin, Shuicheng
Sent: Friday, March 7, 2025 3:26 PM
To: Cavitt, Jonathan ; intel...@lists.freedesktop.org
Cc: Gupta, saurabhg ; Zuo, Alex ;
joonas.lahti...@linux.intel.com; Brost, Matthew ;
Zhang, Jianxun ; dri-devel@lists.freedesktop.org
Subject: RE: [PATCH v6 0
在 2025/3/11 14:40, Bingbu Cao 写道:
[You don't often get email from bingbu@linux.intel.com. Learn why this is
important at https://aka.ms/LearnAboutSenderIdentification ]
Huan Yang and Vivek,
I am trying to use udmabuf for my test, and I cannot vmap the udmabuf
buffers now. vmap_pfn_apply(
On 25-03-10 22:05:51, Aleksandrs Vinarskis wrote:
> Take into account LTTPR capabilities when selecting maximum allowed
> link rate, number of data lines. Initialize LTTPR before
> msm_dp_panel_read_sink_caps, as
> a) Link params computation need to take into account LTTPR's caps
> b) It appears DP
On 11/03/2025 07:16, Vignesh Raman wrote:
> The mediatek display driver fails to probe on mt8173 and mt8183 in
> v6.14-rc4, with the following errors:
Which boards?
>
> mt8173:
> platform 1401b000.dsi: deferred probe pending: mtk-dsi: Failed to get hs clock
> platform 14025000.hdmi: deferred pro
Hi Alistair,
On Tue, 11 Mar 2025 16:57:49 +1100 Alistair Popple wrote:
>
> I'm not sure what the process is here, but having either reviewed or authored
> these patches I can add that the fix up carried below looks correct.
Thanks. This means that people can have a bit more confidence in the
re
On Mon, Mar 10, 2025 at 04:58:22PM -0400, Anusha Srivatsa wrote:
> Move away from using deprecated API and use _multi
> variants if available. Use mipi_dsi_msleep()
> and mipi_dsi_usleep_range() instead of msleep()
> and usleep_range() respectively.
>
> Used Coccinelle to find the multiple occuren
Il 11/03/25 09:05, Boris Brezillon ha scritto:
On Mon, 10 Mar 2025 16:59:19 -0300
Ariel D'Alessandro wrote:
Currently, Panfrost only supports MMU configuration in "LEGACY" (as
Bifrost calls it) mode, a (modified) version of LPAE "Large Physical
Address Extension", which in Linux we've called "
On Mon, Mar 10, 2025 at 08:42:29PM +0200, Dmitry Baryshkov wrote:
> On Mon, 10 Mar 2025 at 16:55, Maxime Ripard wrote:
> >
> > Hi,
> >
> > On Fri, Mar 07, 2025 at 07:55:52AM +0200, Dmitry Baryshkov wrote:
> > > From: Dmitry Baryshkov
> > >
> > > As pointed out by Laurent, OP bits are supposed to
On 10.03.2025 22:30, Cavitt, Jonathan wrote:
> -Original Message-
> From: Wajdeczko, Michal
> Sent: Monday, March 10, 2025 11:20 AM
> To: Cavitt, Jonathan ;
> intel...@lists.freedesktop.org
> Cc: Gupta, saurabhg ; Zuo, Alex
> ; joonas.lahti...@linux.intel.com; Brost, Matthew
> ; Zha
Hi Aleksandrs,
Just a drive-by comment.
On Mon, Mar 10, 2025 at 10:05:52PM +0100, Aleksandrs Vinarskis wrote:
> @@ -1084,10 +1091,13 @@ static int msm_dp_ctrl_update_vx_px(struct
> msm_dp_ctrl_private *ctrl)
> }
>
> static bool msm_dp_ctrl_train_pattern_set(struct msm_dp_ctrl_private *ctrl,
Hi Christoph and Ryan,
Can you help us check vmap_pfn's pfn check is right? Did here mischecked
pfn_valid?
Thank you.
在 2025/3/11 17:02, Bingbu Cao 写道:
Christoph and Ryan,
Could you help check this? Thanks.
On 3/11/25 4:54 PM, Huan Yang wrote:
在 2025/3/11 16:42, Bingbu Cao 写道:
[You don't
On 05/03/2025 14:35, Thomas Zimmermann wrote:
Ast's AST_VIDMEM_SIZE_ constants enumerate supported video-memory
sizes from 8 MiB to 128 MiB. Replace them with Linux' SZ_ constants
of the same value. When expanded, the literal values remain the same.
The size constant for 128 MiB is unused and th
On 05/03/2025 14:35, Thomas Zimmermann wrote:
Add register constants for VGACR99 and use them when detecting the
size of the VGA memory. Aligns the code with the programming manual.
Also replace literal size values with Linux' SZ_ size constants.
Thanks, it looks good to me.
Reviewed-by: Jocel
On 05/03/2025 14:35, Thomas Zimmermann wrote:
The ast drivers stores the cursor image at the end of the video memory.
Add helpers to calculate the offset and size.
Thanks, it looks good to me.
Reviewed-by: Jocelyn Falempe
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_curso
On 05/03/2025 17:30, Thomas Zimmermann wrote:
Add register constants for VGACRAA and use them when detecting the
size of the VGA memory. Aligns the code with the programming manual.
Thanks, it looks good to me.
Reviewed-by: Jocelyn Falempe
Signed-off-by: Thomas Zimmermann
---
drivers/gpu
On 05/03/2025 17:30, Thomas Zimmermann wrote:
Add register constants for VGACR99 and use them when detecting the
size of the VGA memory. Aligns the code with the programming manual.
Also replace literal size values with Linux' SZ_ size constants.
Thanks, it looks good to me.
Reviewed-by: Jocel
On 05/03/2025 17:30, Thomas Zimmermann wrote:
The ast driver stores the primary plane's image in the framebuffer
memory up to where the cursor is located. Add helpers to calculate
the offset and size.
Thanks, it looks good to me.
Reviewed-by: Jocelyn Falempe
Signed-off-by: Thomas Zimmermann
On 05/03/2025 17:30, Thomas Zimmermann wrote:
Helpers compute the offset and size of the available framebuffer
memory. Remove the obsolete field vram_fb_available from struct
ast_device. Also define the cursor-signature size next to its only
user.
Thanks, it looks good to me.
Reviewed-by: Joce
On 3/4/2025 3:58 PM, Nemesa Garg wrote:
Add the macro for casf HAS_CASF.
A bit explanation about the macro and why is this introduced will be good.
Signed-off-by: Nemesa Garg
---
drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/dr
On 05/03/2025 17:30, Thomas Zimmermann wrote:
The cursor scanout address requires alignment to a multiple of 8,
but does not require page alignment. Change the offset calculation
accordingly. Frees up a few more bytes for the primary framebuffer.
The framebuffer is page aligned, so I'm not sure
On Tue, Mar 11, 2025 at 05:50:09PM +0200, Dmitry Baryshkov wrote:
> On Tue, Mar 11, 2025 at 09:36:37AM +0100, Maxime Ripard wrote:
> > On Mon, Mar 10, 2025 at 08:42:29PM +0200, Dmitry Baryshkov wrote:
> > > On Mon, 10 Mar 2025 at 16:55, Maxime Ripard wrote:
> > > >
> > > > Hi,
> > > >
> > > > On F
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 256.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Lyude Paul
Cc: Karol Herbst
Cc: Lyude Paul
Cc: Danilo Krummrich
---
drivers/gpu/drm/nouveau/nouveau_display.c | 7 ---
1 fi
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 8.
Signed-off-by: Thomas Zimmermann
Cc: Chun-Kuang Hu
Cc: Philipp Zabel
Cc: Matthias Brugger
Cc: AngeloGioacchino Del Regno
---
drivers/gpu/drm/mediatek/mtk_gem.c | 13 --
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch
and buffer size. Align the pitch to a multiple of 8.
Signed-off-by: Thomas Zimmermann
Cc: Oleksandr Andrushchenko
---
drivers/gpu/drm/xen/xen_drm_front.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/dr
Add drm_modes_size_dumb(), a helper to calculate the dumb-buffer
scanline pitch and allocation size. Implementations of struct
drm_driver.dumb_create can call the new helper for their size
computations.
There is currently quite a bit of code duplication among DRM's
memory managers. Each calculates
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. No alignment required.
Signed-off-by: Thomas Zimmermann
Cc: Inki Dae
Cc: Seung-Woo Kim
Cc: Kyungmin Park
Cc: Krzysztof Kozlowski
Cc: Alim Akhtar
---
drivers/gpu/drm/exynos/exynos_drm_gem.c | 8 +---
1 file
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch
and buffer size. Align the pitch to a multiple of 8. Align the
buffer size according to hardware requirements.
Xe's internal calculation allowed for 64-bit wide buffer sizes, but
the ioctl's internal checks always verified against 32-
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch according to hardware requirements.
Signed-off-by: Thomas Zimmermann
Acked-by: Thierry Reding
Cc: Thierry Reding
Cc: Mikko Perttunen
---
drivers/gpu/drm/tegra/gem.c | 8 +---
1 file changed, 5
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 4.
Signed-off-by: Thomas Zimmermann
Cc: David Airlie
Cc: Gerd Hoffmann
Cc: Gurchetan Singh
Cc: Chia-I Wu
---
drivers/gpu/drm/virtio/virtgpu_gem.c | 11 +--
1 file changed
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Inline code from drm_gem_vram_fill_create_dumb() without
the existing size computation. Align the pitch to a multiple of 8.
Only hibmc and vboxvideo use gem-vram. Hibmc invokes the call to
drm_gem_vram_fill_create_dum
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 64.
Signed-off-by: Thomas Zimmermann
Acked-by: Heiko Stuebner
Cc: Sandy Huang
Cc: "Heiko Stübner"
Cc: Andy Yan
---
drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 12 ++--
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch according to hardware requirements.
Signed-off-by: Thomas Zimmermann
Cc: Laurent Pinchart
Cc: Tomi Valkeinen
---
drivers/gpu/drm/xlnx/zynqmp_kms.c | 7 +--
1 file changed, 5 insertions(+), 2 de
On Tue, Mar 11, 2025 at 09:41:13AM +0100, Maxime Ripard wrote:
> Hi,
>
> On Mon, Mar 10, 2025 at 08:53:24PM +0200, Dmitry Baryshkov wrote:
> > On Mon, 10 Mar 2025 at 17:08, Maxime Ripard wrote:
> > >
> > > On Fri, Mar 07, 2025 at 07:55:53AM +0200, Dmitry Baryshkov wrote:
> > > > From: Dmitry Bary
Hi
Am 11.03.25 um 14:10 schrieb Jocelyn Falempe:
On 05/03/2025 17:30, Thomas Zimmermann wrote:
The cursor scanout address requires alignment to a multiple of 8,
but does not require page alignment. Change the offset calculation
accordingly. Frees up a few more bytes for the primary framebuffer.
On Tue, Mar 11, 2025 at 09:36:37AM +0100, Maxime Ripard wrote:
> On Mon, Mar 10, 2025 at 08:42:29PM +0200, Dmitry Baryshkov wrote:
> > On Mon, 10 Mar 2025 at 16:55, Maxime Ripard wrote:
> > >
> > > Hi,
> > >
> > > On Fri, Mar 07, 2025 at 07:55:52AM +0200, Dmitry Baryshkov wrote:
> > > > From: Dmit
On 10/03/2025 13:30, Ashley Smith wrote:
> The timeout logic provided by drm_sched leads to races when we try
> to suspend it while the drm_sched workqueue queues more jobs. Let's
> overhaul the timeout handling in panthor to have our own delayed work
> that's resumed/suspended when a group is resu
On 10.03.2025 18:18, Jonathan Cavitt wrote:
> Migrate the pagefault struct from xe_gt_pagefault.c to the
nit: we use "migrate" verb for different purposes.
maybe here (and in the title) the plain "move" will be better?
> xe_gt_pagefault.h header file, along with the associated enum values.
hm
Hi,
On Mon, Mar 10, 2025 at 1:58 PM Anusha Srivatsa wrote:
>
> @@ -70,6 +70,7 @@ static int r63353_panel_power_on(struct r63353_panel
> *rpanel)
> {
> struct mipi_dsi_device *dsi = rpanel->dsi;
> struct device *dev = &dsi->dev;
> + struct mipi_dsi_multi_context dsi_ctx = {
5.15-stable review patch. If anyone has any objections, please let me know.
--
From: Thomas Zimmermann
[ Upstream commit 666e1960464140cc4bc9203c203097e70b54c95a ]
The code for detecting and updating the connector status in
cdn_dp_pd_event_work() has a number of problems.
- I
Applied. Thanks!
On Mon, Mar 10, 2025 at 8:18 AM SRINIVASAN SHANMUGAM
wrote:
>
>
> On 3/10/2025 4:17 PM, Dan Carpenter wrote:
>
> These lines are indented one tab too far. Delete the extra tabs.
>
> Signed-off-by: Dan Carpenter
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 4 ++--
> 1 fil
On Tue, Mar 11, 2025 at 05:54:40PM +0530, Ayushi Makhija wrote:
> Add DSI Controller v2.5.1 support for SA8775P SoC.
>
> Signed-off-by: Ayushi Makhija
> ---
> drivers/gpu/drm/msm/dsi/dsi_cfg.c | 18 ++
> drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
> 2 files changed, 19 insertions(+
On Tue, Mar 11, 2025 at 05:54:39PM +0530, Ayushi Makhija wrote:
> The SA8775P SoC uses the 5nm (v4.2) DSI PHY driver with
> different enable regulator load.
>
> Signed-off-by: Ayushi Makhija
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.h |
On Tue, Mar 11, 2025 at 05:54:44PM +0530, Ayushi Makhija wrote:
> The anx7625_link_bridge() checks if a device is not a panel
> bridge and add DRM_BRIDGE_OP_HPD and DRM_BRIDGE_OP_DETECT to
> the bridge operations. However, on port 1 of the anx7625
> bridge, any device added is always treated as a p
This adds the UAPI for the Asahi driver targeting the GPU in the Apple
M1 and M2 series systems on chip. The UAPI design is based on other
modern Vulkan-capable drivers, including Xe and Panthor. Memory
management is based on explicit VM management. Synchronization is
exclusively explicit sync.
Th
On Mon, Mar 10, 2025 at 06:41:08PM +0800, Damon Ding wrote:
> Add analogix_dpaux_wait_hpd_asserted() to help confirm the HPD state
> before doing AUX transfers.
>
> Signed-off-by: Damon Ding
> ---
> .../drm/bridge/analogix/analogix_dp_core.c| 21 +++
> 1 file changed, 21 inse
On 21/02/2025 17:26, Dmitry Baryshkov wrote:
> Minot nit below
>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
>> index
>> 43a254cf57da571e2ec8aad38028477652f9283c..3e0bdd1100ebb0d302a852ceeaf8af86835e69a1
>> 100644
>> --- a/drivers/g
> > +/**
> > + * struct drm_asahi_gem_bind - Arguments passed to
> > + * DRM_IOCTL_ASAHI_GEM_BIND
> > + */
> > +struct drm_asahi_gem_bind {
> > + /** @op: Bind operation (enum drm_asahi_bind_op) */
> > + __u32 op;
> > +
> > + /** @flags: One or more of ASAHI_BIND_* (BIND only) */
-Original Message-
From: Brost, Matthew
Sent: Monday, March 10, 2025 9:51 PM
To: Cavitt, Jonathan
Cc: intel...@lists.freedesktop.org; Gupta, saurabhg ;
Zuo, Alex ; joonas.lahti...@linux.intel.com; Zhang, Jianxun
; Lin, Shuicheng ;
dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v7
On 05/03/2025 17:30, Thomas Zimmermann wrote:
The ast drivers stores the cursor image at the end of the video memory.
Add helpers to calculate the offset and size.
Thanks, it looks good to me.
Reviewed-by: Jocelyn Falempe
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_curso
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 8.
Push the current calculation into the only direct caller imx. Imx's
hardware requires the framebuffer width to be aligned to 8. The
driver's current approach is actually incorrect,
The ioctls MODE_CREATE_DUMB and MODE_MAP_DUMB return results into a
memory buffer supplied by user space. On errors, it is possible that
intermediate values are being returned. The exact semantics depends
on the DRM driver's implementation of these ioctls. Although this is
most-likely not a securit
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 128.
The hibmc driver's new hibmc_dumb_create() is similar to the one
in GEM VRAM helpers. The driver was the only caller of
drm_gem_vram_fill_create_dumb(). Remove the now unused help
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch according to hardware requirements.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Sui Jingfeng
Cc: Sui Jingfeng
---
drivers/gpu/drm/loongson/lsdc_gem.c | 29 -
1 file ch
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch
and buffer size. Alignment is specified in bytes, but the hardware
requires the scanline pitch to be a multiple of 32 pixels. Therefore
compute the byte size of 32 pixels in the given color mode and align
the pitch accordingly. This re
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 8.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_gem_shmem_helper.c | 16 +---
1 file changed, 5 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/d
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. The hardware requires the framebuffer width to be a
multiple of 8. The scanline pitch has be large enough to support
this. Therefore compute the byte size of 8 pixels in the given color
mode and align the pitch accordi
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 128.
v4:
- align pitch to 128 bytes (Russell)
Signed-off-by: Thomas Zimmermann
Cc: Russell King
---
drivers/gpu/drm/armada/armada_gem.c | 16 +++-
1 file changed, 7 ins
Hi,
I think the first thing we need to address is that we will need to
differentiate between HDMI 1.4 devices and HDMI 2.0.
It applies to YUV420, which is HDMI 2.0-only, and I guess your patches
are good enough if you consider YUV420 support only, but scrambler setup
for example is a thing we wan
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch
and buffer size. No alignment required.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Zack Rusin
Cc: Zack Rusin
Cc: Broadcom internal kernel review list
---
drivers/gpu/drm/vmwgfx/vmwgfx_surface.c | 21 -
1 fi
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 8.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Tomi Valkeinen
Cc: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/omap_gem.c | 15 +++
1 file changed, 7 insertions(+), 8 d
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch
and buffer size. No alignment required.
Signed-off-by: Thomas Zimmermann
Cc: Dave Airlie
Cc: Gerd Hoffmann
---
drivers/gpu/drm/qxl/qxl_dumb.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/dr
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch according to hardware requirements.
Signed-off-by: Thomas Zimmermann
Cc: Laurent Pinchart
Cc: Kieran Bingham
---
drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c | 7 +--
1 file changed, 5 inserti
Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch according to hardware requirements.
Signed-off-by: Thomas Zimmermann
Cc: Biju Das
---
drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff
Yeah, you are right, but I believe it would be better to retain the checks.
Anyway, I have submitted the V3 patch which has dropped the checks.
Thanks and Regards,
Shixiong Ou.
在 2025/3/10 03:42, Helge Deller 写道:
On 3/9/25 09:16, Shixiong Ou wrote:
From: Shixiong Ou
Call device_remove_file(
On 11/20/24 07:18, keith zhao wrote:
Verisilicon/DC8200 display controller IP has 2 display pipes and each
pipe support a primary plane and a cursor plane .
In addition, there are 4 overlay planes as 2 display pipes common resources.
The first display pipe is bound to the inno HDMI encoder.
The
Hi,
On Tue, Mar 11, 2025 at 10:29:28AM +0800, Liu Ying wrote:
> On 03/10/2025, Maxime Ripard wrote:
> > On Fri, Mar 07, 2025 at 11:25:40AM +0800, Liu Ying wrote:
> >> On 03/07/2025, Rob Herring wrote:
> >>> On Thu, Mar 06, 2025 at 12:35:49PM +0100, Maxime Ripard wrote:
> On Thu, Mar 06, 2025
Huan,
Thanks for your response.
On 3/11/25 3:12 PM, Huan Yang wrote:
>
> 在 2025/3/11 14:40, Bingbu Cao 写道:
>> [You don't often get email from bingbu@linux.intel.com. Learn why this
>> is important at https://aka.ms/LearnAboutSenderIdentification ]
>>
>> Huan Yang and Vivek,
>>
>> I am tryin
Move some options out into a new debug specific kconfig file in order to
make things a bit cleaner.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
Cc: Philipp Stanner
---
drivers/gpu/drm/Kconfig | 109 ++
drivers
On 07/03/2025 11:21, Oded Gabbay wrote:
> On Thu, Mar 06, 2025 at 03:51:24PM +0200, Avizrat, Yaron wrote:
>> On 05/03/2025 13:57, Jani Nikula wrote:
>>> On Wed, 05 Mar 2025, "Avizrat, Yaron" wrote:
On 29/07/2024 15:17, Ofir Bitton wrote:
> I will be leaving Intel soon, Yaron Avizrat wil
Introduce a few macros to facilitate setting custom (i.e. non-default)
EDID data during connector initialization.
This helps reducing boilerplate code while also drops some redundant
calls to set_connector_edid().
Signed-off-by: Cristian Ciocaltea
---
drivers/gpu/drm/tests/drm_hdmi_state_helper
Evaluating the requirement to use a limited RGB quantization range
involves a verification of the output format, among others, but this is
currently performed before actually computing the format, hence relying
on the old connector state.
Move the call to hdmi_is_limited_range() after hdmi_compute
Try to make use of YUV420 when computing the best output format and
RGB cannot be supported for any of the available color depths.
Signed-off-by: Cristian Ciocaltea
---
drivers/gpu/drm/display/drm_hdmi_state_helper.c | 69 +
1 file changed, 35 insertions(+), 34 deletions(
Provide the basic support to enable using YUV420 as an RGB fallback when
computing the best output format and color depth.
Signed-off-by: Cristian Ciocaltea
---
Changes in v2:
- Provided the missing Fixes tag on first patch (Dmitry)
- Added patch "drm/connector: hdmi: Improve debug message for su
Provide tests to verify drm_atomic_helper_connector_hdmi_check() helper
fallback behavior when using YUV420 output.
Also rename drm_test_check_max_tmds_rate_{bpc|format}_fallback() to
better differentiate from the newly introduced *_yuv420() variants.
Signed-off-by: Cristian Ciocaltea
---
drive
Provide the necessary constraints verification in
sink_supports_format_bpc() in order to support handling of YUV420
output format.
Signed-off-by: Cristian Ciocaltea
---
drivers/gpu/drm/display/drm_hdmi_state_helper.c | 40 +++--
1 file changed, 37 insertions(+), 3 deletions(-
Hi Krzysztof,
On 11/03/25 12:54, Krzysztof Kozlowski wrote:
On 11/03/2025 07:16, Vignesh Raman wrote:
The mediatek display driver fails to probe on mt8173 and mt8183 in
v6.14-rc4, with the following errors:
Which boards?
These are the boards,
https://lava.pages.collabora.com/docs/boards/chr
On 3/4/2025 3:58 PM, Nemesa Garg wrote:
Add the register bits related to filter lut values
and populate the table.
Lets have some more details about the LUT values and the fact that they
are only needed to be loaded once.
With that fixed this looks good to me.
Reviewed-by: Ankit Nautiyal
On 3/4/2025 3:58 PM, Nemesa Garg wrote:
The sharpness property requires the use of one of the scaler
so need to set the sharpness scaler coefficient values.
These values are based on experiments and vary for different
tap value/win size. These values are normalized by taking the
sum of all valu
On 3/4/2025 3:58 PM, Nemesa Garg wrote:
Compute the values for second scaler for sharpness.
Fill the register bits corresponding to the scaler.
v1: Rename the title of patch [Ankit]
Signed-off-by: Nemesa Garg
---
drivers/gpu/drm/i915/display/intel_casf.c | 3 ++
drivers/gpu/drm/i915/disp
On Sat, 08 Mar 2025, Jonathan Cameron wrote:
> On Wed, 5 Mar 2025 16:18:38 +0200
> Svyatoslav Ryhel wrote:
>
> > ср, 5 бер. 2025 р. о 15:45 Jonathan Cameron пише:
> > >
> > > On Fri, 28 Feb 2025 11:30:51 +0200
> > > Svyatoslav Ryhel wrote:
> > >
> > > > пт, 28 лют. 2025 р. о 10:59 Lee Jones
On 21/02/2025 17:25, Dmitry Baryshkov wrote:
>> -static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
>> -struct dpu_plane_state *pstate, const struct msm_format *format)
>> +static void _dpu_crtc_setup_blend_cfg(const struct dpu_hw_ctl *ctl,
>> +
5.4-stable review patch. If anyone has any objections, please let me know.
--
From: Thomas Zimmermann
commit 53036937a101b5faeaf98e7438555fa854a1a844 upstream.
Including m68k's in vga.h on nommu platforms results
in conflicting defines with io_no.h for various I/O macros from
On Mon, 10 Mar 2025 13:10:24 +, Matt Coster wrote:
> This GPU is found in the TI AM68 family of SoCs, with initial support
> added to the k3-j721s2 devicetree and tested on a TI SK-AM68 board.
>
> A suitable firmware binary can currently be found in the IMG
> linux-firmware repository[1] as
On Mon, Mar 10, 2025 at 01:10:26PM +, Matt Coster wrote:
> Unlike AXE-1-16M, BXS-4-64 uses two power domains.
>
> Like the existing AXE-1-16M integration, BXS-4-64 uses the single clock
> integration in the TI k3-j721s2.
>
> Signed-off-by: Matt Coster
> ---
> Changes in v3:
> - Include addin
On Mon, 10 Mar 2025 16:59:20 -0300
Ariel D'Alessandro wrote:
> Now that Panfrost supports AARCH64_4K page table format, let's enable it
> on Mediatek MT8188.
Can you maybe give more details on why this is needed
(legacy shareability/cacheability not suitable for this GPU?)?
>
> Signed-off-by:
On Mon, Mar 10, 2025 at 10:18:04PM +0200, Dmitry Baryshkov wrote:
> On Mon, Mar 10, 2025 at 03:51:53PM +0100, Maxime Ripard wrote:
> > On Sun, Mar 09, 2025 at 10:13:58AM +0200, Dmitry Baryshkov wrote:
> > > From: Dmitry Baryshkov
> > >
> > > Use drm_hdmi_acr_get_n_cts() helper instead of calculat
On 10/03/2025 21:07, Maíra Canal wrote:
>
> From my understanding, I'm keeping the ABI preserved, as brcm,7268-v3d
> needs to have a GCA register (otherwise, you won't be able to flush the
> cache) and brcm,2711-v3d doesn't even have this piece of hardware.
>
> I understand that now I'm imposing
On Mon, 10 Mar 2025 16:59:19 -0300
Ariel D'Alessandro wrote:
> Currently, Panfrost only supports MMU configuration in "LEGACY" (as
> Bifrost calls it) mode, a (modified) version of LPAE "Large Physical
> Address Extension", which in Linux we've called "mali_lpae".
>
> This commit adds support fo
Hi all,
Today's linux-next merge of the rust tree got a conflict in:
drivers/gpu/drm/drm_panic_qr.rs
between commit:
dbed4a797e00 ("drm/panic: Better binary encoding in QR code")
from the drm tree and commit:
fc2f191f850d ("panic_qr: use new #[export] macro")
from the rust tree.
I fix
On Tue, Mar 11, 2025 at 10:17 AM Stephen Rothwell wrote:
>
> I fixed it up (I guess - see below) and can carry the fix as necessary.
Looks good to me, thanks!
Cheers,
Miguel
On 11/03/2025 07:51, Krzysztof Kozlowski wrote:
> On Mon, Mar 10, 2025 at 01:10:26PM +, Matt Coster wrote:
>> Unlike AXE-1-16M, BXS-4-64 uses two power domains.
>>
>> Like the existing AXE-1-16M integration, BXS-4-64 uses the single clock
>> integration in the TI k3-j721s2.
>>
>> Signed-off-by:
Hi,
On Mon, Mar 10, 2025 at 08:53:24PM +0200, Dmitry Baryshkov wrote:
> On Mon, 10 Mar 2025 at 17:08, Maxime Ripard wrote:
> >
> > On Fri, Mar 07, 2025 at 07:55:53AM +0200, Dmitry Baryshkov wrote:
> > > From: Dmitry Baryshkov
> > >
> > > The MSM DisplayPort driver implements several HDMI codec f
On Mon, Mar 10, 2025 at 10:14:52PM +0200, Dmitry Baryshkov wrote:
> On Mon, Mar 10, 2025 at 03:46:33PM +0100, Maxime Ripard wrote:
> > On Sun, Mar 09, 2025 at 10:13:56AM +0200, Dmitry Baryshkov wrote:
> > > From: Dmitry Baryshkov
> > >
> > > HDMI standard defines recommended N and CTS values for
On 3/4/2025 3:58 PM, Nemesa Garg wrote:
As only second scaler can be used for sharpness check if it
is available and also check if panel fitting is also not enabled,
then set the sharpness. Panel fitting will have the preference
over sharpness property.
v2: Add the panel fitting check before e
On Tue, Mar 11, 2025 at 10:38:37AM +0800, Liu Ying wrote:
> On 03/10/2025, Maxime Ripard wrote:
> > On Fri, Mar 07, 2025 at 11:10:00AM +0800, Liu Ying wrote:
> >> On 03/06/2025, Maxime Ripard wrote:
> >>> On Thu, Mar 06, 2025 at 03:02:41PM +0800, Liu Ying wrote:
> On 03/06/2025, Rob Herring wr
On Mon, Mar 10, 2025 at 01:10:25PM +, Matt Coster wrote:
> The first compatible strings added for the AXE-1-16M are not sufficient to
> accurately describe all the IMG Rogue GPUs. The current "img,img-axe"
> string refers to the entire family of Series AXE GPUs, but this is
> primarily a market
Christoph and Ryan,
Could you help check this? Thanks.
On 3/11/25 4:54 PM, Huan Yang wrote:
>
> 在 2025/3/11 16:42, Bingbu Cao 写道:
>> [You don't often get email from bingbu@linux.intel.com. Learn why this
>> is important at https://aka.ms/LearnAboutSenderIdentification ]
>>
>> Huan,
>>
>>
Il 10/03/25 20:59, Ariel D'Alessandro ha scritto:
Now that Panfrost supports AARCH64_4K page table format, let's enable it
on Mediatek MT8188.
Signed-off-by: Ariel D'Alessandro
---
drivers/gpu/drm/panfrost/panfrost_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/pan
Il 10/03/25 20:59, Ariel D'Alessandro ha scritto:
Currently, Panfrost only supports MMU configuration in "LEGACY" (as
Bifrost calls it) mode, a (modified) version of LPAE "Large Physical
Address Extension", which in Linux we've called "mali_lpae".
This commit adds support for conditionally enabl
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