https://bugs.freedesktop.org/show_bug.cgi?id=110118
Bug ID: 110118
Summary: dsfdsf
Product: DRI
Version: XOrg git
Hardware: Other
OS: OpenBSD
Status: NEW
Severity: normal
Priority: medium
Hello Uma,
> -Original Message-
> From: Shankar, Uma
> Sent: Monday, March 11, 2019 9:28 AM
> To: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Lankhorst, Maarten ; Syrjala, Ville
> ; Sharma, Shashank ;
> emil.l.veli...@gmail.com; brian.star...@arm.com; liviu.du..
https://bugs.freedesktop.org/show_bug.cgi?id=110118
Mayur changed:
What|Removed |Added
URL||asdasd.com
--- Comment #1 from Mayur ---
asdas
https://bugs.freedesktop.org/show_bug.cgi?id=110119
Bug ID: 110119
Summary: Login Is not working
Product: DRI
Version: XOrg git
Hardware: Alpha
OS: All
Status: NEW
Severity: major
Priority: mediu
From: Swati Sharma
Added state checker to validate gamma_lut values. This
reads hardware state, and compares the originally requested
state to the state read from hardware.
This implementation can be used for Gen9+ platforms,
I haven't implemented it for legacy platforms. Just want to get
feedba
> -Original Message-
> From: Shankar, Uma
> Sent: Monday, March 11, 2019 9:28 AM
> To: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Lankhorst, Maarten ; Syrjala, Ville
> ; Sharma, Shashank ;
> emil.l.veli...@gmail.com; brian.star...@arm.com; liviu.du...@arm.com;
> -Original Message-
> From: Shankar, Uma
> Sent: Monday, March 11, 2019 9:28 AM
> To: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Lankhorst, Maarten ; Syrjala, Ville
> ; Sharma, Shashank ;
> emil.l.veli...@gmail.com; brian.star...@arm.com; liviu.du...@arm.com;
> -Original Message-
> From: Shankar, Uma
> Sent: Monday, March 11, 2019 9:28 AM
> To: intel-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Lankhorst, Maarten ; Syrjala, Ville
> ; Sharma, Shashank ;
> emil.l.veli...@gmail.com; brian.star...@arm.com; liviu.du...@arm.com;
Hi Rob,
On 14/03/2019 21:14, Rob Herring wrote:
> On Thu, Mar 14, 2019 at 3:07 PM Neil Armstrong
> wrote:
>>
[...]
>
> Here's with edid-decode:
>
> EDID version: 1.3
> Manufacturer: CYX Model 101 Serial Number 16843009
> Made in week 28 of 2018
> Digital display
> Maximum image size: 22 cm x
https://bugzilla.kernel.org/show_bug.cgi?id=201795
--- Comment #19 from thomas.lassdiesonner...@gmx.de ---
Are you telling me, that the new code is better for most other users, and at
the same time works worse in my case, so you won't fix it? Then I appreciate
that you want me to understand this f
https://bugs.freedesktop.org/show_bug.cgi?id=110119
Andre Klapper changed:
What|Removed |Added
Group||spam
Status|NEW
https://bugs.freedesktop.org/show_bug.cgi?id=110118
Andre Klapper changed:
What|Removed |Added
Resolution|--- |INVALID
Group|
Am 14.03.19 um 23:28 schrieb Eric Anholt:
> Rob Herring writes:
>
>> On Thu, Mar 14, 2019 at 3:45 PM Dave Airlie wrote:
>>> On Thu, 14 Feb 2019 at 19:12, Christian König via dri-devel
>>> wrote:
Am 14.02.19 um 03:52 schrieb Alex Deucher via dri-devel:
> [SNIP]
> +static int lima
Hi Alex,
could you help to submit this patch upstream?
在 3/6/2019 4:08 PM, Christian König 写道:
> Am 06.03.19 um 07:37 schrieb Cui, Flora:
>> deadlock test for sdma will cause gpu recoverty.
>> disable the test for now until GPU reset recovery could survive at least
>> 1000 times test.
>>
>> v2: a
From: Yongqiang Niu
This patch add ddp component CCORR
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 32 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 ++
2 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/
From: Yongqiang Niu
This series are based on 4.20-rc1 and provide 18 patches to
support mediatek SOC MT8183
Resend first version
Yongqiang Niu (18):
drm/mediatek: update dt-bindings for mt8183
drm/mediatek: add mutex mod and sof into ddp private data
drm/mediatek: redefine mtk_ddp_sout_se
From: Yongqiang Niu
This patch add function mtk_ddp_comp_get_type
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 10 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_d
From: Yongqiang Niu
This patch add ddp write register common api
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 24
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +
2 files changed, 33 insertions(+)
diff --git a/drivers/gpu/d
On Wed, 13 Mar 2019 at 23:52, Eric Anholt wrote:
>
> We have another thing called the "done fence" that tracks when the
> scheduler considers the job done, and having the shared name was
> confusing.
>
> Signed-off-by: Eric Anholt
Reviewed-by: Dave Emett
> ---
> drivers/gpu/drm/v3d/v3d_drv.h
The LS020B1DD01D is a 2.0" 240x160 16-bit TFT LCD panel.
Signed-off-by: Paul Cercueil
---
Notes:
v2: New patch
.../devicetree/bindings/display/panel/sharp,ls020b1dd01d.txt | 12
1 file changed, 12 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/pan
From: Yongqiang Niu
This patch add component DITHER
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 32 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 ++
2 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk
On 2019-03-14, Daniel Vetter wrote:
> That's why we came up with the trylock + immediate bail out design if
> that fails. Plus really only render the oops int whatever is the
> current display buffer, so that we don't have to do any hw programming
> at all.
I think this is your best option. The r
From: Yongqiang Niu
This patch add ovl0/ovl0_2l usecase
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 38 ++---
1 file changed, 35 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
b/drivers/gpu/drm/med
The Sharp LS020B1DD01D is a simple 2.0" 240x160 16-bit TFT panel.
Signed-off-by: Paul Cercueil
Tested-by: Artur Rojek
---
Notes:
v2: No change
drivers/gpu/drm/panel/panel-simple.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel
Now drm/udl driver uses drm_do_get_edid() function to retreive and
validate all blocks of EDID data. Old approach had insufficient
validation routine and had problems with retreiving of extra blocks
Signed-off-by: Robert Tarasov
---
drivers/gpu/drm/udl/udl_connector.c | 72 +-
On Thu, 2019-03-14 at 12:30 +0200, Mika Westerberg wrote:
> On Wed, Mar 13, 2019 at 07:09:26PM +0100, Timur Kristóf wrote:
> > Hi,
>
> Hi,
>
> > I was sent here by Greg KH from the Linux USB mailing list, I hope
> > this
> > is the right place to ask.
> >
> > PCI-E atomics don't work for me with
From: Yongqiang Niu
This patch add layer_nr for ovl private data
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
On Thu, Mar 14, 2019 at 06:26:00PM +0100, Timur Kristóf wrote:
> I know atomics is a PCIe feature, but in this case the PCIe goes
> through TB3, so I would assume it has something to do with it.
Does it work if you plug the graphics card directly to the PCIe slot?
> Here is the output of 'lspci -
Hi All,
I would like to explain more for the purpose of this patch. During our
daily test on android system, we found that there is always showing
the memory fragmentation after some test cases(etc camera snapshot),
which lead to huge amount of order0 pages which other page blocks
remain none(200M
From: Zhaoyang Huang
Two action for this patch:
1. set a batch size for system heap's shrinker, which can have it buffer
reasonable page blocks in pool for future allocation.
2. reverse the order sequence when free page blocks, the purpose is also
to have system heap keep as more big blocks as it
> 1. Does AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 without any
> AFBC_FORMAT_MOD_XXX uncompressed format just reorder the pixels
> in one 16x16 block same way as GPU "tiled" format? Or just no reorder
> (linear)?
>
> 2. Is there any unreleased AFBC_FORMAT_MOD_XXX bit for this GPU
> "tiled" format?
I bel
On Wed, 13 Mar 2019 at 23:52, Eric Anholt wrote:
>
> We deref v3d->bin_job in the work handler, but v3d->bin_job doesn't
> actually hold a ref on the job.
>
> Signed-off-by: Eric Anholt
Reviewed-by: Dave Emett
> ---
> drivers/gpu/drm/v3d/v3d_irq.c | 3 ++-
> 1 file changed, 2 insertions(+), 1
On Thu, 2019-03-14 at 20:17 +0200, Mika Westerberg wrote:
> > > > Here is the output of 'lspci -vv':
> > > > https://pastebin.com/Qt5RUFVc
> > >
> > > The root port (1c.4) says this:
> > >
> > > DevCap2: Completion Timeout: Range ABC, TimeoutDis+, LTR+,
> > > OBFF
> > > Not Supported ARIFwd
On 2019-03-14, John Ogness wrote:
> On 2019-03-14, Daniel Vetter wrote:
>> That's why we came up with the trylock + immediate bail out design if
>> that fails. Plus really only render the oops int whatever is the
>> current display buffer, so that we don't have to do any hw
>> programming at all.
Hi Daniel,
Le ven. 1 mars 2019 à 9:26, Daniel Vetter a écrit :
On Thu, Feb 28, 2019 at 07:07:56PM -0300, Paul Cercueil wrote:
Add a KMS driver for the Ingenic JZ47xx family of SoCs.
This driver is meant to replace the aging jz4740-fb driver.
Signed-off-by: Paul Cercueil
Tested-by: Artur
On Wed, Mar 13, 2019 at 07:09:26PM +0100, Timur Kristóf wrote:
> Hi,
Hi,
> I was sent here by Greg KH from the Linux USB mailing list, I hope this
> is the right place to ask.
>
> PCI-E atomics don't work for me with Thunderbolt 3.
> I see the following message from my Thunderbolt 3 eGPU in dmes
From: Yongqiang Niu
This patch add support for mediatek SOC MT8183
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 +
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 7 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 131 ++-
drivers/g
From: Yongqiang Niu
This patch add commponent OVL0_2L
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
b/drivers/gpu
From: Yongqiang Niu
This patch redefine mtk_ddp_sout_sel
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 32
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/medi
The GiantPlus GPM940B0 is a 24-bit TFT panel where the RGB components
are transferred sequentially on a 8-bit bus.
Signed-off-by: Paul Cercueil
---
Notes:
v2: New patch
include/uapi/linux/media-bus-format.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/uapi
From: Yongqiang Niu
Update device tree binding documention for the display subsystem for
Mediatek MT8183 SOCs
Signed-off-by: Yongqiang Niu
---
.../devicetree/bindings/display/mediatek/mediatek,disp.txt| 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git
a/Document
From: Yongqiang Niu
This patch add function to connect module with it's previous one
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
b/drivers/gpu/drm/mediatek/
The GiantPlus GPM940B0 is a simple 3.0" 320x240 24-bit TFT panel.
Signed-off-by: Paul Cercueil
Tested-by: Artur Rojek
---
Notes:
v2: Change bus format to MEDIA_BUS_FMT_RGB888_3X8_BE
drivers/gpu/drm/panel/panel-simple.c | 28
1 file changed, 28 insertions(+)
d
On Thu, 2019-03-14 at 19:40 +0200, Mika Westerberg wrote:
> On Thu, Mar 14, 2019 at 06:26:00PM +0100, Timur Kristóf wrote:
> > I know atomics is a PCIe feature, but in this case the PCIe goes
> > through TB3, so I would assume it has something to do with it.
>
> Does it work if you plug the graphi
From: Yongqiang Niu
This patch add component OVL1_2L
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
b/drivers/gpu/
On Thu, 2019-03-14 at 18:35 +0100, Matthias Brugger wrote:
>
> On 14/03/2019 13:05, yongqiang@mediatek.com wrote:
> > From: Yongqiang Niu
> >
> > This series are based on 4.20-rc1 and provide 18 patches to
> > support mediatek SOC MT8183
> > Resend first version
> >
>
> I think you send t
From: Yongqiang Niu
This patch add mmsys private data for ddp path config
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 4 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 102 ++--
drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 10
drive
From: Yongqiang Niu
This patch add gmc_bits for ovl private data
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
b/drivers/gpu/drm/medi
"AGTB" is jargon-y, but then again, so is "AFBC"... Unless Arm wants to
publish the actual name for the format, this works :)
Thank you for the clarification (in the other emails)
Reviewed-by: Alyssa Rosenzweig
___
dri-devel mailing list
dri-devel@list
From: Yongqiang Niu
This patch move rdma sout from mtk_ddp_mout_en into mtk_ddp_sout_sel
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 90 +-
1 file changed, 45 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk
Maxime Ripard writes:
> On Mon, Mar 11, 2019 at 04:11:06PM +, Måns Rullgård wrote:
>> Maxime Ripard writes:
>>
>> > Hi!
>> >
>> > On Mon, Mar 11, 2019 at 01:47:13PM +, Mans Rullgard wrote:
>> >> Sometimes it is desirabled to use a separate i2c controller for ddc
>> >> access. This adds
> AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 denotes the superblock size to be
> used only in case of AFBC buffers.
> For non compressed tiled format, none of the AFBC_FORMAT_MOD_XXX
> should be used.
Alright, understood. Thank you for the clarification :)
___
dri
The GPM940B0 is a 3.0" 320x240 24-bit TFT LCD panel.
Signed-off-by: Paul Cercueil
---
Notes:
v2: New patch
.../devicetree/bindings/display/panel/giantplus,gpm940b0.txt | 12
1 file changed, 12 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/panel/g
On Thu, Mar 14, 2019 at 10:49 AM Sumit Semwal wrote:
>
> Hello Chenbo,Thank you for your RFC series.
>
> On Wed, 27 Feb 2019 at 09:24, Chenbo Feng wrote:
> >
> > Currently, all dma-bufs share the same anonymous inode. While we can count
> > how many dma-buf fds or mappings a process has, we can't
On Thu, Mar 14, 2019 at 06:54:21PM +0100, Timur Kristóf wrote:
> On Thu, 2019-03-14 at 19:40 +0200, Mika Westerberg wrote:
> > On Thu, Mar 14, 2019 at 06:26:00PM +0100, Timur Kristóf wrote:
> > > I know atomics is a PCIe feature, but in this case the PCIe goes
> > > through TB3, so I would assume i
On Tue, 2018-12-25 at 11:57 +0800, Nicolas Boichat wrote:
> On Mon, Dec 24, 2018 at 6:52 PM Yongqiang Niu
> wrote:
> >
> > This patch redefine mtk_ddp_sout_sel
>
> Can you describe a bit more why you are making this change?
the format of "mtk_ddp_sout_sel"was not flexible, after we add more
medi
From: Yongqiang Niu
This patch add connect function for ovl
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index a0
From: Yongqiang Niu
This patch add RDMA1 fifo size into RDMA private data
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
b/drivers/gpu/drm/m
On 3/11/2019 9:27 AM, Uma Shankar wrote:
Enable Dynamic Range and Mastering Infoframe for HDR
content, which is defined in CEA 861.3 spec.
The metadata will be computed based on blending
policy in userspace compositors and passed as a connector
property blob to driver. The same will be sent as
From: Yongqiang Niu
This patch add mutex mod and sof into ddp private data
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 117 ++---
1 file changed, 94 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/
On Tue, 2018-12-25 at 12:15 +0800, Nicolas Boichat wrote:
> On Mon, Dec 24, 2018 at 6:53 PM Yongqiang Niu
> wrote:
> >
> > This patch add gmc_bits for ovl private data
> >
> > Signed-off-by: Yongqiang Niu
> > ---
> > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 23 +--
> > 1 fil
https://bugs.freedesktop.org/show_bug.cgi?id=110120
Bug ID: 110120
Summary: the software crashes when bug occur
Product: DRI
Version: XOrg git
Hardware: Other
OS: All
Status: NEW
Severity: normal
https://bugs.freedesktop.org/show_bug.cgi?id=110120
CR7 changed:
What|Removed |Added
URL||www.google.co.in
--
You are receiving this mail
On Fri, Mar 15, 2019 at 10:43:48AM +0800, Chen-Yu Tsai wrote:
> On Fri, Mar 15, 2019 at 4:16 AM Maxime Ripard
> wrote:
> >
> > Using the new helpers introduced since we wrote that code, we can simplify
> > the code to retrieve the backend ID significantly.
> >
> > The new code will also allow us
https://bugs.freedesktop.org/show_bug.cgi?id=110122
Bug ID: 110122
Summary: HELP PAGE NOT WORKING
Product: DRI
Version: XOrg git
Hardware: x86-64 (AMD64)
OS: Windows (All)
Status: NEW
Severity: minor
add memcpy dispatch test for gfx9
Change-Id: Ic9b280db2ced21b15e228c1c4c217836ab3f44a8
Signed-off-by: Flora Cui
Tested-by: Rui Teng
Reviewed-by: Hawking Zhang
---
tests/amdgpu/basic_tests.c | 163 -
1 file changed, 161 insertions(+), 2 deletions(-)
add memset dispatch test for gfx9
v2: disable dispatch test for other ASICs
Change-Id: I55a410a4ea0a6d19d1aca1f172e1dfcbbd1112fa
Signed-off-by: Flora Cui
Tested-by: Rui Teng
Reviewed-by: Hawking Zhang
---
tests/amdgpu/amdgpu_test.c | 5 +
tests/amdgpu/basic_tests.c | 273
add memcpy draw test for gfx9
Change-Id: Ib80e55b1ab7aa556c4b5adfdd39aedf7d58ba628
Signed-off-by: Flora Cui
Tested-by: Rui Teng
---
tests/amdgpu/basic_tests.c | 264 +++--
1 file changed, 253 insertions(+), 11 deletions(-)
diff --git a/tests/amdgpu/basic
add memset draw test for gfx9
Change-Id: I3a1f2460ec0917e29ce1a891200eeaa1a0565fda
Signed-off-by: Flora Cui
Tested-by: Rui Teng
---
tests/amdgpu/amdgpu_test.c | 5 +
tests/amdgpu/basic_tests.c | 554 +
2 files changed, 559 insertions(+)
diff --git
Hi,
On Fri, Mar 15, 2019 at 10:28:16AM +0800, Chen-Yu Tsai wrote:
> > diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi
> > b/arch/arm/boot/dts/sun8i-a33.dtsi
> > index a6498102..4484d76c88b5 100644
> > --- a/arch/arm/boot/dts/sun8i-a33.dtsi
> > +++ b/arch/arm/boot/dts/sun8i-a33.dtsi
> > @@ -266,
On Fri, Mar 15, 2019 at 10:39:24AM +0800, Chen-Yu Tsai wrote:
> On Fri, Mar 15, 2019 at 4:16 AM Maxime Ripard
> wrote:
> >
> > The soc node in the A80 DTSI has a ranges property, but no matching unit
> > address, which results in a DTC warning. Add the unit address to remove
> > that warning.
> >
https://bugs.freedesktop.org/show_bug.cgi?id=110123
Bug ID: 110123
Summary: Status is Not displaying.
Product: DRI
Version: DRI git
Hardware: x86-64 (AMD64)
OS: Windows (All)
Status: NEW
Severity: minor
https://bugs.freedesktop.org/show_bug.cgi?id=110124
Bug ID: 110124
Summary: help page is not working
Product: DRI
Version: XOrg git
Hardware: x86-64 (AMD64)
OS: Windows (All)
Status: NEW
Severity: minor
On Thu, Mar 14, 2019 at 09:16:21PM +0100, Maxime Ripard wrote:
> Here is the rest of the series that fixes most of our DTC warnings. The
> number of warnings when compiled with W=1 after applying this series is now
> reduced to 2.
>
> The two remaining one are on the A80 and would require some cha
On Fri, Mar 15, 2019 at 5:02 PM Maxime Ripard wrote:
>
> On Fri, Mar 15, 2019 at 10:39:24AM +0800, Chen-Yu Tsai wrote:
> > On Fri, Mar 15, 2019 at 4:16 AM Maxime Ripard
> > wrote:
> > >
> > > The soc node in the A80 DTSI has a ranges property, but no matching unit
> > > address, which results in
On Fri, Mar 15, 2019 at 05:09:22PM +0800, Chen-Yu Tsai wrote:
> On Fri, Mar 15, 2019 at 5:02 PM Maxime Ripard
> wrote:
> >
> > On Fri, Mar 15, 2019 at 10:39:24AM +0800, Chen-Yu Tsai wrote:
> > > On Fri, Mar 15, 2019 at 4:16 AM Maxime Ripard
> > > wrote:
> > > >
> > > > The soc node in the A80 D
On Fri, 15 Mar 2019, swati2.sha...@intel.com wrote:
> From: Swati Sharma
>
> Added state checker to validate gamma_lut values. This
> reads hardware state, and compares the originally requested
> state to the state read from hardware.
>
> This implementation can be used for Gen9+ platforms,
> I ha
On Fri, Mar 15, 2019 at 2:46 AM Dave Airlie wrote:
> From: Dave Airlie
>
> If the downscaling fails and we end up with a best_depth of 0,
> then ignore it.
>
> This actually works around a cascade of failure, but it the
> simplest fix for now.
>
> The scaling patch broke the udl driver, as the u
On Fri, 15 Mar 2019, Dave Airlie wrote:
> On Thu, 14 Mar 2019 at 18:25, Robert Tarasov wrote:
>>
>> Now drm/udl driver uses drm_do_get_edid() function to retreive and
>> validate all blocks of EDID data. Old approach had insufficient
>> validation routine and had problems with retreiving of extra
This patch is an attempt to limit HDMI 2.0 SCDC setup when :
- the SoC embeds an HDMI 1.4 only controller
- the EDID supports SCDC but not scrambling
- the EDID supports SCDC scrambling but not for low TMDS bit rates,
while only supporting low TMDS bit rates
This to avoid communicating with the
On 2019-03-14 6:51 p.m., Helen Koike wrote:
> On 3/14/19 6:15 AM, Michel Dänzer wrote:
>> On 2019-03-13 7:08 p.m., Helen Koike wrote:
>>> On 3/13/19 6:58 AM, Michel Dänzer wrote:
On 2019-03-13 4:42 a.m., Tomasz Figa wrote:
> On Wed, Mar 13, 2019 at 12:52 AM Boris Brezillon
> wrote:
>>
On Fri, Mar 15, 2019 at 5:16 PM Maxime Ripard wrote:
>
> On Fri, Mar 15, 2019 at 05:09:22PM +0800, Chen-Yu Tsai wrote:
> > On Fri, Mar 15, 2019 at 5:02 PM Maxime Ripard
> > wrote:
> > >
> > > On Fri, Mar 15, 2019 at 10:39:24AM +0800, Chen-Yu Tsai wrote:
> > > > On Fri, Mar 15, 2019 at 4:16 AM Ma
On Fri, 15 Mar 2019 11:11:36 +0100
Michel Dänzer wrote:
> On 2019-03-14 6:51 p.m., Helen Koike wrote:
> > On 3/14/19 6:15 AM, Michel Dänzer wrote:
> >> On 2019-03-13 7:08 p.m., Helen Koike wrote:
> >>> On 3/13/19 6:58 AM, Michel Dänzer wrote:
> On 2019-03-13 4:42 a.m., Tomasz Figa wrot
On Thu, Mar 14, 2019 at 10:04:18PM +, Kieran Bingham wrote:
> The drm_crtc_state documentation contains a subtle misspelling of the
> word subtle. Correct it.
>
> Signed-off-by: Kieran Bingham
Reviewed-by: Daniel Vetter
> ---
> include/drm/drm_crtc.h | 2 +-
> 1 file changed, 1 insertion(
On Thu, Mar 14, 2019 at 08:44:45AM -0500, Benoit Parrot wrote:
> During a suspend cycle the atomic state is saved to be used during the
> restore cycle.
>
> However the current state duplication logic does not duplicate private
> objects. This leads to state inconsistencies at resume time.
>
> Wi
On Thu, Mar 14, 2019 at 01:36:59PM +0100, Paul Cercueil wrote:
> Hi Daniel,
>
> Le ven. 1 mars 2019 à 9:26, Daniel Vetter a écrit :
> > On Thu, Feb 28, 2019 at 07:07:56PM -0300, Paul Cercueil wrote:
> > > Add a KMS driver for the Ingenic JZ47xx family of SoCs.
> > > This driver is meant to repl
On Thu, Mar 14, 2019 at 10:52:08AM +0100, John Ogness wrote:
> On 2019-03-14, John Ogness wrote:
> > On 2019-03-14, Daniel Vetter wrote:
> >> That's why we came up with the trylock + immediate bail out design if
> >> that fails. Plus really only render the oops int whatever is the
> >> current di
On Thu, Mar 14, 2019 at 12:44:06PM +, Kazlauskas, Nicholas wrote:
> On 3/14/19 5:50 AM, Daniel Vetter wrote:
> > On Wed, Mar 13, 2019 at 05:41:52PM +, Kazlauskas, Nicholas wrote:
> >> On 3/13/19 1:33 PM, Michel Dänzer wrote:
> >>> On 2019-03-13 5:16 p.m., Kazlauskas, Nicholas wrote:
>
Hi,
On Mon, 3 Dec 2018 at 17:04, Philipp Zabel wrote:
> On Mon, 2018-12-03 at 10:46 -0600, Ryan Pavlik wrote:
> > Add two EDID vendor/product pairs used across a variety of
> > Sensics products, as well as the OSVR HDK and HDK 2.
> >
> > Signed-off-by: Ryan Pavlik
>
> Reviewed-by: Philipp Zabel
On Thu, Mar 14, 2019 at 03:48:45PM -0300, Rodrigo Siqueira wrote:
> Allow atomic_enable and atomic_disable operations from
> drm_crtc_helper_funcs struct optional. With this, the target display
> drivers don't need to define a dummy function if they don't need one.
>
> Changes since v2:
> * Don't
On Fri, Mar 15, 2019 at 03:13:30PM +1000, Dave Airlie wrote:
> From: Dave Airlie
>
> If we unplug a udl device, the usb callback with deinit the
> mode_config struct, however userspace will still have an open
> file descriptor and a framebuffer on that device. When userspace
> closes the fd, we'l
On Thu, Mar 14, 2019 at 6:49 PM Sumit Semwal wrote:
>
> Hello Chenbo,Thank you for your RFC series.
>
> On Wed, 27 Feb 2019 at 09:24, Chenbo Feng wrote:
> >
> > Currently, all dma-bufs share the same anonymous inode. While we can count
> > how many dma-buf fds or mappings a process has, we can't
On 3/11/2019 9:27 AM, Uma Shankar wrote:
Enable writing of HDR metadata infoframe to panel.
The data will be provid by usersapace compositors, based
on blending policies and passsed to driver through a blob
property.
v2: Rebase
v3: Fixed a warning message
v4: Addressed Shashank's review comme
On 3/11/2019 9:28 AM, Uma Shankar wrote:
From: Ville Syrjälä
ADD HLG EOTF to the list of EOTF transfer functions supported.
Hybrid Log-Gamma (HLG) is a high dynamic range (HDR) standard.
HLG defines a nonlinear transfer function in which the lower
half of the signal values use a gamma curve an
Hi Linus,
Please pull fbdev changes for v5.1. Just a couple of small fixes and
cleanups (please see the signed tag description for details).
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
The following changes since commit 8834f5600cf3c8db365e18a3d5
On Fri, Mar 15, 2019 at 11:46:20AM +1000, Dave Airlie wrote:
> From: Dave Airlie
>
> When Daniel removed struct_mutex he didn't fix this call to the unlocked
> variant which is required since we no longer use struct mutex.
>
> This fixes a bunch of:
> WARNING: CPU: 4 PID: 1370 at drivers/gpu/drm
On 2019-03-15 11:25 a.m., Boris Brezillon wrote:
> On Fri, 15 Mar 2019 11:11:36 +0100
> Michel Dänzer wrote:
>
>> On 2019-03-14 6:51 p.m., Helen Koike wrote:
>>> On 3/14/19 6:15 AM, Michel Dänzer wrote:
On 2019-03-13 7:08 p.m., Helen Koike wrote:
> On 3/13/19 6:58 AM, Michel Dänzer w
On 28/02/2019 12.31, Tomi Valkeinen wrote:
> On 28/02/2019 12:27, Tomi Valkeinen wrote:
>> Hi Laurent,
>>
>> On 11/02/2019 11:46, Laurent Pinchart wrote:
>>
>>> + /* Get the sampling edge from the endpoint. */
>>> + of_property_read_u32(ep, "pclk-sample", &pclk_sample);
>>> + of_node_put(ep
Provide helpers to manage the power state, and initial configuration of
the CRTC to match the group implementation.
rcar_du_crtc_get() and rcar_du_crtc_get() are no longer used, and are
removed, simplifying the implementation and removing the initialized
flag which was needed to track the state of
Create a new private state object for the DU groups, and move the
initialisation of a group object to a new function rcar_du_group_init().
Signed-off-by: Kieran Bingham
---
I'll be extending the data that goes into this private structure.
Have I got the creation and handling of the private objec
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