From: Lad Prabhakar
Add a compatible string for the Renesas RZ/V2N SoC variants that include a
Mali-G31 GPU. These variants share the same restrictions on interrupts,
clocks, and power domains as the RZ/G2L SoC, so extend the existing schema
validation accordingly.
Signed-off-by: Lad Prabhakar
Hi Fabrizio,
On Thu, May 1, 2025 at 11:38 AM Fabrizio Castro
wrote:
>
> Hi Alok,
>
> Thanks for your email.
>
> > From: ALOK TIWARI
> > Sent: 01 May 2025 10:51
> > Subject: Re: [PATCH v4 01/15] clk: renesas: rzv2h-cpg: Add support for DSI
> > clocks
>
From: Lad Prabhakar
Simplify the high-speed clock frequency (HSFREQ) calculation by removing
the redundant multiplication and division by 8. The updated equation:
hsfreq = (mode->clock * bpp) / (dsi->lanes);
produces the same result while improving readability and clarity.
Additi
From: Lad Prabhakar
The LCD controller (LCDC) on the RZ/V2H(P) SoC is composed of Frame
Compression Processor (FCPVD), Video Signal Processor (VSPD), and
Display Unit (DU).
There is one LCDC unit available on the RZ/V2H(P) SoC which is connected
to the DSI.
Signed-off-by: Lad Prabhakar
---
v3
From: Lad Prabhakar
In preparation for adding support for the Renesas RZ/V2H(P) SoC, this patch
introduces a mechanism to pass SoC-specific information via OF data in the
DSI driver. This enables the driver to adapt dynamically to various
SoC-specific requirements without hardcoding
From: Lad Prabhakar
Introduce the `RZ_MIPI_DSI_FEATURE_LPCLK` feature flag in
`rzg2l_mipi_dsi_hw_info` to indicate the need for LPCLK configuration.
On the RZ/V2H(P) SoC, the LPCLK clock rate influences the required
DPHY register configuration, whereas on the RZ/G2L SoC, this clock
is not
From: Lad Prabhakar
Pass the HSFREQ in milli-Hz to the `dphy_init()` callback to improve
precision, especially for the RZ/V2H(P) SoC, where PLL dividers require
high accuracy.
These changes prepare the driver for upcoming RZ/V2H(P) SoC support.
Co-developed-by: Fabrizio Castro
Signed-off-by
From: Lad Prabhakar
Introduce `dphy_conf_clks` and `dphy_mode_clk_check` callbacks in
`rzg2l_mipi_dsi_hw_info` to configure the VCLK and validate
supported display modes.
On the RZ/V2H(P) SoC, the DSI PLL dividers need to be as accurate as
possible. To ensure compatibility with both RZ/G2L and
From: Lad Prabhakar
The DU block on the RZ/V2H(P) SoC is identical to the one found on the
RZ/G2L SoC. However, it only supports the DSI interface, whereas the
RZ/G2L supports both DSI and DPI interfaces.
Due to this difference, a SoC-specific compatible string
'renesas,r9a09g057-du'
From: Lad Prabhakar
Introduce the `RZ_MIPI_DSI_FEATURE_16BPP` flag in `rzg2l_mipi_dsi_hw_info`
to indicate support for 16BPP pixel formats. The RZ/V2H(P) SoC supports
16BPP, whereas this feature is missing on the RZ/G2L SoC.
Update the `mipi_dsi_host_attach()` function to check this flag before
From: Lad Prabhakar
Introduce the `dphy_late_init` callback in `rzg2l_mipi_dsi_hw_info` to
allow additional D-PHY register configurations after enabling data and
clock lanes. This is required for the RZ/V2H(P) SoC but not for the
RZ/G2L SoC.
Modify `rzg2l_mipi_dsi_startup()` to invoke
From: Lad Prabhakar
Add DSI support for Renesas RZ/V2H(P) SoC.
Co-developed-by: Fabrizio Castro
Signed-off-by: Fabrizio Castro
Signed-off-by: Lad Prabhakar
---
v3->v4
- In rzv2h_dphy_find_ulpsexit() made the array static const.
v2->v3:
- Simplifed V2H DSI timings array to save
From: Lad Prabhakar
Add support for PLLDSI and PLLDSI divider clocks.
Introduce the `renesas-rzv2h-dsi.h` header to centralize and share
PLLDSI-related data structures, limits, and algorithms between the RZ/V2H
CPG and DSI drivers.
The DSI PLL is functionally similar to the CPG's PLLDSI
From: Lad Prabhakar
The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to that of
the RZ/G2L SoC. While the LINK registers are the same for both SoCs, the
D-PHY registers differ. Additionally, the number of resets for DSI on
RZ/V2H(P) is two compared to three on the RZ/G2L.
To
From: Lad Prabhakar
Update the RZ/G2L MIPI DSI driver to calculate HSFREQ using the actual
VCLK rate instead of the mode clock. The relationship between HSCLK and
VCLK is:
vclk * bpp <= hsclk * 8 * lanes
Retrieve the VCLK rate using `clk_get_rate(dsi->vclk)`, ensuring that
From: Lad Prabhakar
From: Lad Prabhakar
Hi All,
This patch series adds support for the Display Unit (DU) and MIPI DSI
interface on the Renesas RZ/V2H(P) SoC. The initial patches add PLLDSI
clocks and reset entries for the DSI and LCDC and the later patches add
support for the DU and DSI
From: Lad Prabhakar
The VCLK range for Renesas RZ/G2L SoC is 148.5 MHz to 5.803 MHz. Add a
minimum clock check in the mode_valid callback to ensure that the clock
value does not fall below the valid range.
Co-developed-by: Fabrizio Castro
Signed-off-by: Fabrizio Castro
Signed-off-by: Lad
From: Lad Prabhakar
Add clock and reset entries for the DSI and LCDC peripherals.
Co-developed-by: Fabrizio Castro
Signed-off-by: Fabrizio Castro
Signed-off-by: Lad Prabhakar
---
v3->v4:
- No changes
v2->v3:
- Reverted CSDIV0_DIVCTL2() to use DDIV_PACK()
- Renamed plleth_lpcl
Hi Geert,
Thank you for the review.
On Tue, Apr 22, 2025 at 8:41 AM Geert Uytterhoeven wrote:
>
> Hi Prabhakar,
>
> On Fri, 18 Apr 2025 at 20:47, Prabhakar wrote:
> > From: Lad Prabhakar
> >
> > Pass the HSFREQ in milli-Hz to the `dphy_init()` callback to improve
Hi Biju,
Thank you for the review.
On Sat, Apr 19, 2025 at 8:28 AM Biju Das wrote:
>
> Hi Prabhakar,
>
> Thanks for the patch.
>
> > -Original Message-
> > From: Prabhakar
> > Sent: 18 April 2025 19:47
> > Subject: [PATCH v3 15/15] drm: renesas: r
From: Lad Prabhakar
Introduce the `dphy_late_init` callback in `rzg2l_mipi_dsi_hw_info` to
allow additional D-PHY register configurations after enabling data and
clock lanes. This is required for the RZ/V2H(P) SoC but not for the
RZ/G2L SoC.
Modify `rzg2l_mipi_dsi_startup()` to invoke
From: Lad Prabhakar
In preparation for adding support for the Renesas RZ/V2H(P) SoC, this patch
introduces a mechanism to pass SoC-specific information via OF data in the
DSI driver. This enables the driver to adapt dynamically to various
SoC-specific requirements without hardcoding
From: Lad Prabhakar
Add DSI support for Renesas RZ/V2H(P) SoC.
Co-developed-by: Fabrizio Castro
Signed-off-by: Fabrizio Castro
Signed-off-by: Lad Prabhakar
---
v2->v3:
- Simplifed V2H DSI timings array to save space
- Switched to use fsleep() instead of udelay()
v1->v2:
- Dropped
From: Lad Prabhakar
Introduce the `RZ_MIPI_DSI_FEATURE_16BPP` flag in `rzg2l_mipi_dsi_hw_info`
to indicate support for 16BPP pixel formats. The RZ/V2H(P) SoC supports
16BPP, whereas this feature is missing on the RZ/G2L SoC.
Update the `mipi_dsi_host_attach()` function to check this flag before
From: Lad Prabhakar
Update the RZ/G2L MIPI DSI driver to calculate HSFREQ using the actual
VCLK rate instead of the mode clock. The relationship between HSCLK and
VCLK is:
vclk * bpp <= hsclk * 8 * lanes
Retrieve the VCLK rate using `clk_get_rate(dsi->vclk)`, ensuring that
From: Lad Prabhakar
Introduce the `RZ_MIPI_DSI_FEATURE_LPCLK` feature flag in
`rzg2l_mipi_dsi_hw_info` to indicate the need for LPCLK configuration.
On the RZ/V2H(P) SoC, the LPCLK clock rate influences the required
DPHY register configuration, whereas on the RZ/G2L SoC, this clock
is not
From: Lad Prabhakar
Pass the HSFREQ in milli-Hz to the `dphy_init()` callback to improve
precision, especially for the RZ/V2H(P) SoC, where PLL dividers require
high accuracy.
These changes prepare the driver for upcoming RZ/V2H(P) SoC support.
Co-developed-by: Fabrizio Castro
Signed-off-by
From: Lad Prabhakar
Introduce `dphy_conf_clks` and `dphy_mode_clk_check` callbacks in
`rzg2l_mipi_dsi_hw_info` to configure the VCLK and validate
supported display modes.
On the RZ/V2H(P) SoC, the DSI PLL dividers need to be as accurate as
possible. To ensure compatibility with both RZ/G2L and
From: Lad Prabhakar
The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to that of
the RZ/G2L SoC. While the LINK registers are the same for both SoCs, the
D-PHY registers differ. Additionally, the number of resets for DSI on
RZ/V2H(P) is two compared to three on the RZ/G2L.
To
From: Lad Prabhakar
The DU block on the RZ/V2H(P) SoC is identical to the one found on the
RZ/G2L SoC. However, it only supports the DSI interface, whereas the
RZ/G2L supports both DSI and DPI interfaces.
Due to this difference, a SoC-specific compatible string
'renesas,r9a09g057-du'
From: Lad Prabhakar
Simplify the high-speed clock frequency (HSFREQ) calculation by removing
the redundant multiplication and division by 8. The updated equation:
hsfreq = (mode->clock * bpp) / (dsi->lanes);
produces the same result while improving readability and clarity.
Additi
From: Lad Prabhakar
The LCD controller (LCDC) on the RZ/V2H(P) SoC is composed of Frame
Compression Processor (FCPVD), Video Signal Processor (VSPD), and
Display Unit (DU).
There is one LCDC unit available on the RZ/V2H(P) SoC which is connected
to the DSI.
Signed-off-by: Lad Prabhakar
---
v2
From: Lad Prabhakar
The VCLK range for Renesas RZ/G2L SoC is 148.5 MHz to 5.803 MHz. Add a
minimum clock check in the mode_valid callback to ensure that the clock
value does not fall below the valid range.
Co-developed-by: Fabrizio Castro
Signed-off-by: Fabrizio Castro
Signed-off-by: Lad
From: Lad Prabhakar
Hi All,
This patch series adds support for the Display Unit (DU) and MIPI DSI
interface on the Renesas RZ/V2H(P) SoC. The initial patches add PLLDSI
clocks and reset entries for the DSI and LCDC and the later patches add
support for the DU and DSI drivers. The DU block is
From: Lad Prabhakar
Add support for PLLDSI and PLLDSI divider clocks.
Introduce the `renesas-rzv2h-dsi.h` header to centralize and share
PLLDSI-related data structures, limits, and algorithms between the RZ/V2H
CPG and DSI drivers.
The DSI PLL is functionally similar to the CPG's PLLDSI
From: Lad Prabhakar
Add clock and reset entries for the DSI and LCDC peripherals.
Co-developed-by: Fabrizio Castro
Signed-off-by: Fabrizio Castro
Signed-off-by: Lad Prabhakar
---
v2->v3:
- Reverted CSDIV0_DIVCTL2() to use DDIV_PACK()
- Renamed plleth_lpclk_div4 -> cdiv4_plleth
Hi Geert,
On Wed, Apr 16, 2025 at 10:27 AM Geert Uytterhoeven
wrote:
>
> Hi Prabhakar, Fabrizio,
>
> Thanks for your patch!
>
> On Tue, 8 Apr 2025 at 22:09, Prabhakar wrote:
> > From: Lad Prabhakar
> >
> > Add support for PLLDSI and PLLDSI divider cloc
Hi Geert,
Thank you for the review.
On Wed, Apr 16, 2025 at 10:35 AM Geert Uytterhoeven
wrote:
>
> Hi Prabhakar, Fabrizio,
>
> On Tue, 8 Apr 2025 at 22:09, Prabhakar wrote:
> > From: Lad Prabhakar
> >
> > Add DSI support for Renesas RZ/V2H(P) SoC.
> >
Hi Geert,
Thank you for the review.
On Tue, Apr 15, 2025 at 4:51 PM Geert Uytterhoeven wrote:
>
> Hi Prabhakar,
>
> On Tue, 8 Apr 2025 at 22:09, Prabhakar wrote:
> > From: Lad Prabhakar
> >
> > Add clock and reset entries for the DSI and LCDC peripherals.
>
Hi Geert,
Thank you for the review.
On Wed, Apr 16, 2025 at 10:27 AM Geert Uytterhoeven
wrote:
>
> Hi Prabhakar, Fabrizio,
>
> Thanks for your patch!
>
> On Tue, 8 Apr 2025 at 22:09, Prabhakar wrote:
> > From: Lad Prabhakar
> >
> > Add support for PLLDSI an
Hi Geert,
Thank you for the review.
On Tue, Apr 15, 2025 at 4:57 PM Geert Uytterhoeven wrote:
>
> Hi Prabhakar,
>
> On Tue, 8 Apr 2025 at 22:09, Prabhakar wrote:
> > From: Lad Prabhakar
> >
> > Add support for PLLDSI and PLLDSI divider clocks.
> >
> >
Hi Biju,
Thank you for the review.
On Sat, Apr 12, 2025 at 9:01 AM Biju Das wrote:
>
> Hi Prabhakar,
>
> Thanks for the patch.
>
> > -Original Message-
> > From: Prabhakar
> > Sent: 08 April 2025 21:09
> > Subject: [PATCH v2 15/15] drm: renesas: r
From: Lad Prabhakar
Introduce `dphy_conf_clks` and `dphy_mode_clk_check` callbacks in
`rzg2l_mipi_dsi_hw_info` to configure the VCLK and validate
supported display modes.
On the RZ/V2H(P) SoC, the DSI PLL dividers need to be as accurate as
possible. To ensure compatibility with both RZ/G2L and
From: Lad Prabhakar
Update the RZ/G2L MIPI DSI driver to calculate HSFREQ using the actual
VCLK rate instead of the mode clock. The relationship between HSCLK and
VCLK is:
vclk * bpp <= hsclk * 8 * lanes
Retrieve the VCLK rate using `clk_get_rate(dsi->vclk)`, ensuring that
From: Lad Prabhakar
The LCD controller (LCDC) on the RZ/V2H(P) SoC is composed of Frame
Compression Processor (FCPVD), Video Signal Processor (VSPD), and
Display Unit (DU).
There is one LCDC unit available on the RZ/V2H(P) SoC which is connected
to the DSI.
Signed-off-by: Lad Prabhakar
---
v1
Hi Geert,
Thank you for the review.
On Wed, Apr 9, 2025 at 9:16 AM Geert Uytterhoeven wrote:
>
> Hi Prabhakar,
>
> On Tue, 8 Apr 2025 at 22:09, Prabhakar wrote:
> > From: Lad Prabhakar
> >
> > Pass the HSFREQ in milli-Hz to the `dphy_init()` callback to improve
From: Lad Prabhakar
Add DSI support for Renesas RZ/V2H(P) SoC.
Co-developed-by: Fabrizio Castro
Signed-off-by: Fabrizio Castro
Signed-off-by: Lad Prabhakar
---
v1->v2:
- Dropped unused macros
- Added missing LPCLK flag to rzvv2h info
---
.../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c|
From: Lad Prabhakar
Introduce the `RZ_MIPI_DSI_FEATURE_LPCLK` feature flag in
`rzg2l_mipi_dsi_hw_info` to indicate the need for LPCLK configuration.
On the RZ/V2H(P) SoC, the LPCLK clock rate influences the required
DPHY register configuration, whereas on the RZ/G2L SoC, this clock
is not
From: Lad Prabhakar
Add clock and reset entries for the DSI and LCDC peripherals.
Co-developed-by: Fabrizio Castro
Signed-off-by: Fabrizio Castro
Signed-off-by: Lad Prabhakar
---
v1->v2:
- No changes
---
drivers/clk/renesas/r9a09g057-cpg.c | 63 +
drivers/
From: Lad Prabhakar
Pass the HSFREQ in milli-Hz to the `dphy_init()` callback to improve
precision, especially for the RZ/V2H(P) SoC, where PLL dividers require
high accuracy.
These changes prepare the driver for upcoming RZ/V2H(P) SoC support.
Co-developed-by: Fabrizio Castro
Signed-off-by
From: Lad Prabhakar
Hi All,
This patch series adds support for the Display Unit (DU) and MIPI DSI
interface on the Renesas RZ/V2H(P) SoC. The initial patches add PLLDSI
clocks and reset entries for the DSI and LCDC and the later patches add
support for the DU and DSI drivers. The DU block is
From: Lad Prabhakar
Introduce the `RZ_MIPI_DSI_FEATURE_16BPP` flag in `rzg2l_mipi_dsi_hw_info`
to indicate support for 16BPP pixel formats. The RZ/V2H(P) SoC supports
16BPP, whereas this feature is missing on the RZ/G2L SoC.
Update the `mipi_dsi_host_attach()` function to check this flag before
From: Lad Prabhakar
Introduce the `dphy_late_init` callback in `rzg2l_mipi_dsi_hw_info` to
allow additional D-PHY register configurations after enabling data and
clock lanes. This is required for the RZ/V2H(P) SoC but not for the
RZ/G2L SoC.
Modify `rzg2l_mipi_dsi_startup()` to invoke
From: Lad Prabhakar
In preparation for adding support for the Renesas RZ/V2H(P) SoC, this patch
introduces a mechanism to pass SoC-specific information via OF data in the
DSI driver. This enables the driver to adapt dynamically to various
SoC-specific requirements without hardcoding
From: Lad Prabhakar
Simplify the high-speed clock frequency (HSFREQ) calculation by removing
the redundant multiplication and division by 8. The updated equation:
hsfreq = (mode->clock * bpp) / (dsi->lanes);
produces the same result while improving readability and clarity.
Additi
From: Lad Prabhakar
The VCLK range for Renesas RZ/G2L SoC is 148.5 MHz to 5.803 MHz. Add a
minimum clock check in the mode_valid callback to ensure that the clock
value does not fall below the valid range.
Co-developed-by: Fabrizio Castro
Signed-off-by: Fabrizio Castro
Signed-off-by: Lad
From: Lad Prabhakar
The DU block on the RZ/V2H(P) SoC is identical to the one found on the
RZ/G2L SoC. However, it only supports the DSI interface, whereas the
RZ/G2L supports both DSI and DPI interfaces.
Due to this difference, a SoC-specific compatible string
'renesas,r9a09g057-du'
From: Lad Prabhakar
The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to that of
the RZ/G2L SoC. While the LINK registers are the same for both SoCs, the
D-PHY registers differ. Additionally, the number of resets for DSI on
RZ/V2H(P) is two compared to three on the RZ/G2L.
To
From: Lad Prabhakar
Add support for PLLDSI and PLLDSI divider clocks.
The `renesas-rzv2h-dsi.h` header file is added to share the PLL divider
algorithm between the CPG and DSI drivers.
Co-developed-by: Fabrizio Castro
Signed-off-by: Fabrizio Castro
Signed-off-by: Lad Prabhakar
---
v1->
@42:512x300+200+200@XR15
>
> modetest -M rzg2l-du -w {32,37}:alpha:{0,65535}
> modetest -M rzg2l-du -w {32,37}:zpos:{0,1}
>
> Signed-off-by: Biju Das
> ---
> drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.c | 9 +
> 1 file changed, 9 insertions(+)
>
Tested-by: L
using
> the DRM_GEM_DMA_DRIVER_OPS_WITH_DUMB_CREATE() helper macro.
>
> Signed-off-by: Laurent Pinchart
> ---
> Kieran, would you be able to test this ?
> ---
> drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Lad Prabhakar
Teste
rzg2l_du_vsp_formats, maintaining the same ordering in both tables.
>
> Signed-off-by: Kieran Bingham
> ---
> drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c | 141 ++-
> 1 file changed, 136 insertions(+), 5 deletions(-)
>
Tested-by: Lad Prabhakar
Cheers,
Prabhakar
&g
From: Lad Prabhakar
Add Mali-G31 GPU node to SoC DTSI.
Signed-off-by: Lad Prabhakar
---
arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 51 ++
1 file changed, 51 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
b/arch/arm64/boot/dts/renesas/r9a09g057
From: Lad Prabhakar
Enable Mali-G31 (GPU) node on EVK board.
Signed-off-by: Lad Prabhakar
---
.../boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
b/arch/arm64/boot/dts
From: Lad Prabhakar
Add a compatible string for the Renesas RZ/V2H(P) SoC variants that
include a Mali-G31 GPU. These variants share the same restrictions on
interrupts, clocks, and power domains as the RZ/G2L SoC, so extend
the existing schema validation accordingly.
Signed-off-by: Lad
From: Lad Prabhakar
Hi All,
This patch series adds support for the Mali-G31 GPU on the RZ/V2H(P) SoC.
The changes include updating the device tree bindings, adding the GPU node
to the SoC device tree, and enabling the GPU on the RZ/V2H evaluation kit.
Lad Prabhakar (3):
dt-bindings: gpu
t; .../gpu/drm/renesas/rz-du/rzg2l_du_encoder.c | 18 ++
> 1 file changed, 18 insertions(+)
>
Reviewed-by: Lad Prabhakar
Cheers,
Prabhakar
> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
> b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
>
> v1->v2:
> * Added Fixes tag.
> ---
> drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c | 8 +---
> 1 file changed, 1 insertion(+), 7 deletions(-)
>
Reviewed-by: Lad Prabhakar
Cheers,
Prabhakar
> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
> b/drivers/
Hi Laurent,
On Wed, Jun 26, 2024 at 6:51 AM Laurent Pinchart
wrote:
>
> Hi Prabhakar,
>
> Thank you for the patch.
>
> On Tue, Jun 25, 2024 at 01:32:44PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar
> >
> > All the RZ/G2L DU specific components are locat
tform/ti/am437x/am437x-vpfe.c | 12 +---
> drivers/media/platform/ti/davinci/vpif_capture.c | 14 +++---
> 2 files changed, 12 insertions(+), 14 deletions(-)
>
Reviewed-by: Prabhakar
Cheers,
Prabhakar
From: Lad Prabhakar
All the RZ/G2L DU specific components are located under the rz-du folder,
so it makes sense to move the RZ/G2L MIPI DSI driver there instead of
keeping it in the rcar-du folder. This change improves the organization
and modularity of the driver configuration by grouping
6 deletions(-)
>
Reviewed-by: Lad Prabhakar
Cheers,
Prabhakar
lowed ('resets' was unexpected)
From schema:
Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml
While at it mark resets property as required as all the DT sources
in the kernel specify resets and update the example node.
Signed-off-by: Lad Prabhakar
Revie
Hi Krzysztof,
Thank you for the review.
On Tue, Aug 30, 2022 at 10:23 AM Krzysztof Kozlowski
wrote:
>
> On 30/08/2022 00:58, Lad Prabhakar wrote:
> > With 'unevaluatedProperties' support implemented, there's a number of
> > warnings when running dtbs_check:
&g
Hi Laurent,
On Tue, Aug 30, 2022 at 12:08 AM Laurent Pinchart
wrote:
>
> Hi Prabhakar,
>
> Thank you for the patch.
>
> On Mon, Aug 29, 2022 at 10:58:16PM +0100, Lad Prabhakar wrote:
> > With 'unevaluatedProperties' support implemented, there's a number
om schema:
Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml
The main problem is that SoC DTSI's are including resets property, whereas
the renesas,dw-hdmi.yaml has 'unevaluatedProperties: false'. So just add
optional resets property to the binding.
Signed-of
The Renesas RZ/V2L SoC (a.k.a R9A07G054) has a Bifrost Mali-G31 GPU,
add a compatible string for it.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a
Hi Inki,
On Fri, Jan 14, 2022 at 11:08 AM Inki Dae wrote:
>
> Hi Lad Prabhakar,
>
> 21. 12. 23. 오전 4:01에 Lad Prabhakar 이(가) 쓴 글:
> > platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static
> > allocation of IRQ resources in DT core code, this causes an issue
>
ining.
In preparation for removal of static setup of IRQ resource from DT core
code use platform_get_irq().
Signed-off-by: Lad Prabhakar
---
Hi,
Ideally I would expect the mixer_resources_init() to be called from probe
instead from the bind callback. If platform_get_irq() returns -EPROBE_DEFER
the bin
-renesas-soc/
patch/20211209001056.29774-1-prabhakar.mahadev-lad...@bp.renesas.com/
Cheers,
Prabhakar
Lad Prabhakar (5):
drm/exynos/exynos7_drm_decon: Use platform_get_irq_byname() to get the
interrupt
drm/exynos: mixer: Use platform_get_irq() to get the interrupt
drm/exynos/exynos_drm_fimd
ining.
In preparation for removal of static setup of IRQ resource from DT core
code use platform_get_irq_byname().
Signed-off-by: Lad Prabhakar
---
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/
ining.
In preparation for removal of static setup of IRQ resource from DT core
code use platform_get_irq().
Signed-off-by: Lad Prabhakar
---
drivers/gpu/drm/exynos/exynos_drm_gsc.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gsc.c
b/d
ining.
In preparation for removal of static setup of IRQ resource from DT core
code use platform_get_irq_byname().
Signed-off-by: Lad Prabhakar
---
drivers/gpu/drm/exynos/exynos7_drm_decon.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/
ining.
In preparation for removal of static setup of IRQ resource from DT core
code use platform_get_irq().
Signed-off-by: Lad Prabhakar
---
drivers/gpu/drm/exynos/exynos_drm_fimc.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c
ru
> Cc: gr-everest-linux...@marvell.com
> Cc: "David S. Miller"
> Cc: Jakub Kicinski
> Cc: net...@vger.kernel.org
> Signed-off-by: Kees Cook
> ---
Reviewed-by: Prabhakar Kushwaha
Hi Geert,
> -Original Message-
> From: Geert Uytterhoeven
> Sent: 28 September 2020 08:26
> To: Lad, Prabhakar
> Cc: Prabhakar Mahadev Lad ; Magnus
> Damm ; Rob Herring
> ; DRI Development ;
> Linux-Renesas ; open
> list:OPEN FIRMWARE AND FLATTENED DEV
Hi Laurent,
On Mon, Aug 24, 2020 at 1:48 AM Laurent Pinchart
wrote:
>
> Hi Prabhakar,
>
> Thank you for the patch.
>
> On Thu, Aug 13, 2020 at 03:00:41PM +0100, Lad Prabhakar wrote:
> > The iwg21d comes with a 7" capacitive touch screen, therefore
> > add su
rcar_dw_hdmi driver is also used on Renesas RZ/G2 SoC's, update the
same to reflect the description for DRM_RCAR_DW_HDMI config.
Signed-off-by: Lad Prabhakar
Reviewed-by: Chris Paterson
---
drivers/gpu/drm/rcar-du/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --
The iwg21d comes with a 7" capacitive touch screen, therefore
add support for it.
Signed-off-by: Lad Prabhakar
Reviewed-by: Marian-Cristian Rotariu
---
v1->v2
* This patch is part of series [1] (rest of the patches have be accepted
by Geert [2]).
* Added regulator for lvds
* Added r
Hi Geert,
Thank you for the review.
On Thu, Aug 13, 2020 at 10:05 AM Geert Uytterhoeven
wrote:
>
> Hi Prabhakar, Laurent, Kieran,
>
> On Wed, Aug 12, 2020 at 4:02 PM Lad Prabhakar
> wrote:
> > From: Marian-Cristian Rotariu
> >
> > Document the RZ/G2H (a.k
Hi Laurent,
On Thu, Aug 13, 2020 at 11:59 AM Laurent Pinchart
wrote:
>
> Hello,
>
> On Thu, Aug 13, 2020 at 11:38:03AM +0100, Lad, Prabhakar wrote:
> > On Thu, Aug 13, 2020 at 10:05 AM Geert Uytterhoeven wrote:
> > > On Wed, Aug 12, 2020 at 4:02 PM Lad Prabhakar
Hi Laurent,
On Thu, Aug 13, 2020 at 12:11 PM Laurent Pinchart
wrote:
>
> Hi Prabhakar,
>
> On Thu, Aug 13, 2020 at 12:08:58PM +0100, Lad, Prabhakar wrote:
> > On Thu, Aug 13, 2020 at 11:59 AM Laurent Pinchart wrote:
> > > On Thu, Aug 13, 2020 at 11:38:03AM +0100, Lad,
Hi Laurent,
Thank you for the review.
On Tue, Aug 11, 2020 at 12:26 PM Laurent Pinchart
wrote:
>
> Hi Prabhakar,
>
> Thank you for the patch.
>
> On Fri, Aug 07, 2020 at 06:49:54PM +0100, Lad Prabhakar wrote:
> > The iwg21d comes with a 7" capacitive touch screen,
Setup up the required clocks for the DU to be functional.
Signed-off-by: Lad Prabhakar
---
arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h.dts
b/arch/arm64/boot/dts/renesas
Hi All,
This patch series adds support for DU, HDMI and LVDS to RZ/G2H SoC.
Cheers,
Prabhakar
Lad Prabhakar (1):
arm64: dts: renesas: r8a774e1-hihope-rzg2h: Setup DU clocks
Marian-Cristian Rotariu (8):
dt-bindings: display: renesas,du: Document r8a774e1 bindings
drm: rcar-du: Add support
Hi Laurent,
On Wed, Aug 12, 2020 at 5:39 PM Laurent Pinchart
wrote:
>
> Hi Prabhakar,
>
> Thank you for the patches.
>
> On Wed, Aug 12, 2020 at 03:02:08PM +0100, Lad Prabhakar wrote:
> > Hi All,
> >
> > This patch series adds support for DU, HDMI and LVDS to
From: Marian-Cristian Rotariu
Document RZ/G2H (R8A774E1) SoC bindings.
Signed-off-by: Marian-Cristian Rotariu
Signed-off-by: Lad Prabhakar
---
.../devicetree/bindings/display/bridge/renesas,dw-hdmi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree
From: Marian-Cristian Rotariu
The LVDS encoder on RZ/G2H (R8A774E1) SoC is identical to R-Car Gen3 so
just reuse the rcar_lvds_gen3_info structure to hookup R8A774E1 to LVDS
encoder driver.
Signed-off-by: Marian-Cristian Rotariu
Signed-off-by: Lad Prabhakar
---
drivers/gpu/drm/rcar-du
From: Marian-Cristian Rotariu
Document the RZ/G2H (R8A774E1) LVDS bindings.
Signed-off-by: Marian-Cristian Rotariu
Signed-off-by: Lad Prabhakar
---
.../devicetree/bindings/display/bridge/renesas,lvds.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree
From: Marian-Cristian Rotariu
Hookup RZ/G2H (R8A774E1) to DU driver. R8A774E1 has one RGB output,
one LVDS output and one HDMI output.
Signed-off-by: Marian-Cristian Rotariu
Signed-off-by: Lad Prabhakar
---
drivers/gpu/drm/rcar-du/rcar_du_drv.c | 30 +++
1 file
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