Re: [PATCH v6 1/4] clk: renesas: rzv2h-cpg: Add support for DSI clocks

Hi Biju, On Thu, Jun 19, 2025 at 6:05 AM Biju Das wrote: > > Hi Prabhakar, > > > -Original Message- > > From: Biju Das > > Sent: 18 June 2025 14:26 > > Subject: RE: [PATCH v6 1/4] clk: renesas: rzv2h-cpg: Add support for DSI > > clocks > &

Re: [PATCH v6 4/4] drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC

On Mon, Jun 16, 2025 at 11:54 AM Biju Das wrote: > > > > > -Original Message- > > From: Lad, Prabhakar > > Sent: Monday, June 16, 2025 11:48 AM > > To: Biju Das > > Cc: Geert Uytterhoeven ; Andrzej Hajda > > ; Neil Armstrong ; > >

Re: [PATCH v6 4/4] drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC

Hi Biju, On Mon, Jun 16, 2025 at 11:54 AM Biju Das wrote: > > > > > -Original Message- > > From: Lad, Prabhakar > > Sent: Monday, June 16, 2025 11:48 AM > > To: Biju Das > > Cc: Geert Uytterhoeven ; Andrzej Hajda > > ; Neil Armstrong ; &

Re: [PATCH v6 4/4] drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC

Hi Biju, Thank you for the review. On Fri, Jun 13, 2025 at 7:17 AM Biju Das wrote: > > Hi Prabhakar, > > > -Original Message- > > From: Prabhakar > > Sent: 30 May 2025 18:19 > > Subject: [PATCH v6 4/4] drm: renesas: rz-du: mipi_dsi: Add support for &g

Re: [PATCH v6 1/4] clk: renesas: rzv2h-cpg: Add support for DSI clocks

Hi Biju, Thank you for the review. On Fri, Jun 13, 2025 at 6:57 AM Biju Das wrote: > > Hi Prabhakar, > > > -Original Message- > > From: Prabhakar > > Sent: 30 May 2025 18:19 > .castro...@renesas.com>; Prabhakar Mahadev Lad > lad...@bp.renesas.

Re: [PATCH] dt-bindings: display: renesas,rzg2l-du: Add support for RZ/V2N SoC

Hi Laurent, Thank you for the review. On Tue, Jun 10, 2025 at 10:58 AM Laurent Pinchart wrote: > > Hi Prabhakar, > > Thank you for the patch. > > On Tue, Jun 10, 2025 at 12:19:05AM +0100, Prabhakar wrote: > > From: Lad Prabhakar > > > > Document support f

[PATCH v7 2/9] drm: renesas: rz-du: mipi_dsi: Simplify HSFREQ calculation

From: Lad Prabhakar Simplify the high-speed clock frequency (HSFREQ) calculation by removing the redundant multiplication and division by 8. The updated equation: hsfreq = mode->clock * bpp / dsi->lanes; produces the same result while improving readability and clarity. Additi

[PATCH] dt-bindings: display: renesas, rzg2l-du: Add support for RZ/V2N SoC

From: Lad Prabhakar Document support for the DU IP found on the Renesas RZ/V2N (R9A09G056) SoC. The DU IP is functionally identical to that on the RZ/V2H(P) SoC, so no driver changes are needed. The existing `renesas,r9a09g057-du` compatible will be used as a fallback for the RZ/V2N SoC. Signed

[PATCH v7 4/9] drm: renesas: rz-du: mipi_dsi: Add OF data support

From: Lad Prabhakar n preparation for adding support for the Renesas RZ/V2H(P) SoC, this patch introduces a mechanism to pass SoC-specific information via OF data in the DSI driver. This enables the driver to adapt dynamically to various SoC-specific requirements without hardcoding

[PATCH v7 5/9] drm: renesas: rz-du: mipi_dsi: Make "rst" reset control optional for RZ/V2H(P)

From: Lad Prabhakar In preparation for adding support for the Renesas RZ/V2H(P) SoC, make the "rst" reset control optional in the MIPI DSI driver. The RZ/V2H(P) SoC does not provide this reset line, and attempting to acquire it using the mandatory API causes probe failure. Sw

[PATCH v7 7/9] drm: renesas: rz-du: mipi_dsi: Add feature flag for 16BPP support

From: Lad Prabhakar Introduce the `RZ_MIPI_DSI_FEATURE_16BPP` flag in `rzg2l_mipi_dsi_hw_info` to indicate support for 16BPP pixel formats. The RZ/V2H(P) SoC supports 16BPP, whereas this feature is missing on the RZ/G2L SoC. Update the `mipi_dsi_host_attach()` function to check this flag before

[PATCH v7 9/9] drm: renesas: rz-du: mipi_dsi: Add function pointers for configuring VCLK and mode validation

From: Lad Prabhakar Introduce `dphy_conf_clks` and `dphy_mode_clk_check` callbacks in `rzg2l_mipi_dsi_hw_info` to configure the VCLK and validate supported display modes. On the RZ/V2H(P) SoC, the DSI PLL dividers need to be as accurate as possible. To ensure compatibility with both RZ/G2L and

[PATCH v7 6/9] drm: renesas: rz-du: mipi_dsi: Use mHz for D-PHY frequency calculations

From: Lad Prabhakar Pass the HSFREQ in milli-Hz to the `dphy_init()` callback to improve precision, especially for the RZ/V2H(P) SoC, where PLL dividers require high accuracy. These changes prepare the driver for upcoming RZ/V2H(P) SoC support. Co-developed-by: Fabrizio Castro Signed-off-by

[PATCH v7 0/9] drm: renesas: rz-du: mipi_dsi: Prepare driver to support RZ/V2H(P) SoC

From: Lad Prabhakar Hi All, This patch series prepares the MIPI DSI driver to support the Renesas RZ/V2H(P) SoC. These patches were originally part of series [0], but I have split them into two parts to make them easier to review and merge. v6->v7: - Rebased the changes on drm-misc/n

[PATCH v7 3/9] drm: renesas: rz-du: mipi_dsi: Use VCLK for HSFREQ calculation

From: Lad Prabhakar Update the RZ/G2L MIPI DSI driver to calculate HSFREQ using the actual VCLK rate instead of the mode clock. The relationship between HSCLK and VCLK is: vclk * bpp <= hsclk * 8 * lanes Retrieve the VCLK rate using `clk_get_rate(dsi->vclk)`, ensuring that

[PATCH v7 8/9] drm: renesas: rz-du: mipi_dsi: Add dphy_late_init() callback for RZ/V2H(P)

From: Lad Prabhakar Introduce the `dphy_late_init` callback in `rzg2l_mipi_dsi_hw_info` to allow additional D-PHY register configurations after enabling data and clock lanes. This is required for the RZ/V2H(P) SoC but not for the RZ/G2L SoC. Modify `rzg2l_mipi_dsi_startup()` to invoke

[PATCH v7 1/9] drm: renesas: rz-du: mipi_dsi: Add min check for VCLK range

From: Lad Prabhakar The VCLK range for Renesas RZ/G2L SoC is 5.803 MHz to 148.5 MHz. Add a minimum clock check in the mode_valid callback to ensure that the clock value does not fall below the valid range. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad

Re: [PATCH v6 05/12] drm: renesas: rz-du: mipi_dsi: Use VCLK for HSFREQ calculation

Hi Laurent, Thank you for the review. On Mon, Jun 2, 2025 at 10:42 AM Laurent Pinchart wrote: > > Hi Prabhakar, > > Thank you for the patch. > > On Fri, May 30, 2025 at 05:58:59PM +0100, Prabhakar wrote: > > From: Lad Prabhakar > > > > Update the RZ/G2L

Re: [PATCH v6 02/12] drm: renesas: rz-du: Add support for RZ/V2H(P) SoC

On Sat, May 31, 2025 at 7:36 AM Biju Das wrote: > > Hi Prabhakar, > > > -Original Message- > > From: Prabhakar > > Sent: 30 May 2025 17:59 > > Subject: [PATCH v6 02/12] drm: renesas: rz-du: Add support for RZ/V2H(P) SoC > > > > From: Lad Pr

Re: [PATCH v6 01/12] dt-bindings: display: renesas,rzg2l-du: Add support for RZ/V2H(P) SoC

On Sat, May 31, 2025 at 7:35 AM Biju Das wrote: > > Hi Prabhakar, > > > -Original Message- > > From: Prabhakar > > Sent: 30 May 2025 17:59 > > Subject: [PATCH v6 01/12] dt-bindings: display: renesas,rzg2l-du: Add > > support for RZ/V2H(P) SoC >

[PATCH v6 1/4] clk: renesas: rzv2h-cpg: Add support for DSI clocks

From: Lad Prabhakar Add support for PLLDSI and PLLDSI divider clocks. Introduce the `renesas-rzv2h-dsi.h` header to centralize and share PLLDSI-related data structures, limits, and algorithms between the RZ/V2H CPG and DSI drivers. The DSI PLL is functionally similar to the CPG's PLLDSI

[PATCH v6 00/12] Add DU support for RZ/V2H(P) SoC

From: Lad Prabhakar Hi All, This patch series adds support for the Display Unit (DU) and prepares the MIPI DSI driver to support the Renesas RZ/V2H(P) SoC. These patches were originally part of series [0], but I have split them into two parts to make them easier to review and merge. This patch

[PATCH v6 3/4] dt-bindings: display: bridge: renesas, dsi: Add support for RZ/V2H(P) SoC

From: Lad Prabhakar The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to that of the RZ/G2L SoC. While the LINK registers are the same for both SoCs, the D-PHY registers differ. Additionally, the number of resets for DSI on RZ/V2H(P) is two compared to three on the RZ/G2L. To

[PATCH v6 4/4] drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC

From: Lad Prabhakar Add DSI support for Renesas RZ/V2H(P) SoC. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar --- v5->v6: - Made use of GENMASK() macro for PLLCLKSET0R_PLL_*, PHYTCLKSETR_* and PHYTHSSETR_* macros. - Replaced 1000UL with

[PATCH v6 2/4] clk: renesas: r9a09g057: Add clock and reset entries for DSI and LCDC

From: Lad Prabhakar Add clock and reset entries for the DSI and LCDC peripherals. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar --- v5->v6: - Renamed CLK_DIV_PLLETH_LPCLK to CLK_CDIV4_PLLETH_LPCLK - Renamed CLK_CSDIV_PLLETH_LPCLK

[PATCH v6 0/4] Add support for DU/DSI clocks and DSI driver support for the Renesas RZ/V2H(P) SoC

From: Lad Prabhakar Hi All, This patch series adds DU/DSI clocks and provides support for the MIPI DSI interface on the RZ/V2H(P) SoC. It was originally part of series [0], but has now been split into 4 patches due to dependencies on the clock driver, making it easier to review and merge. [0

[PATCH v6 08/12] drm: renesas: rz-du: mipi_dsi: Use mHz for D-PHY frequency calculations

From: Lad Prabhakar Pass the HSFREQ in milli-Hz to the `dphy_init()` callback to improve precision, especially for the RZ/V2H(P) SoC, where PLL dividers require high accuracy. These changes prepare the driver for upcoming RZ/V2H(P) SoC support. Co-developed-by: Fabrizio Castro Signed-off-by

[PATCH v6 09/12] drm: renesas: rz-du: mipi_dsi: Add feature flag for 16BPP support

From: Lad Prabhakar Introduce the `RZ_MIPI_DSI_FEATURE_16BPP` flag in `rzg2l_mipi_dsi_hw_info` to indicate support for 16BPP pixel formats. The RZ/V2H(P) SoC supports 16BPP, whereas this feature is missing on the RZ/G2L SoC. Update the `mipi_dsi_host_attach()` function to check this flag before

[PATCH v6 05/12] drm: renesas: rz-du: mipi_dsi: Use VCLK for HSFREQ calculation

From: Lad Prabhakar Update the RZ/G2L MIPI DSI driver to calculate HSFREQ using the actual VCLK rate instead of the mode clock. The relationship between HSCLK and VCLK is: vclk * bpp <= hsclk * 8 * lanes Retrieve the VCLK rate using `clk_get_rate(dsi->vclk)`, ensuring that

[PATCH v6 02/12] drm: renesas: rz-du: Add support for RZ/V2H(P) SoC

From: Lad Prabhakar The LCD controller (LCDC) on the RZ/V2H(P) SoC is composed of Frame Compression Processor (FCPVD), Video Signal Processor (VSPD), and Display Unit (DU). There is one LCDC unit available on the RZ/V2H(P) SoC which is connected to the DSI. Signed-off-by: Lad Prabhakar

[PATCH v6 04/12] drm: renesas: rz-du: mipi_dsi: Simplify HSFREQ calculation

From: Lad Prabhakar Simplify the high-speed clock frequency (HSFREQ) calculation by removing the redundant multiplication and division by 8. The updated equation: hsfreq = mode->clock * bpp / dsi->lanes; produces the same result while improving readability and clarity. Additi

[PATCH v6 07/12] drm: renesas: rz-du: mipi_dsi: Make "rst" reset control optional for RZ/V2H(P)

From: Lad Prabhakar In preparation for adding support for the Renesas RZ/V2H(P) SoC, make the "rst" reset control optional in the MIPI DSI driver. The RZ/V2H(P) SoC does not provide this reset line, and attempting to acquire it using the mandatory API causes probe failure. Sw

[PATCH v6 12/12] drm: renesas: rz-du: mipi_dsi: Add support for LPCLK clock handling

From: Lad Prabhakar Add LPCLK clock support in the RZ/G2L MIPI DSI driver via the optional clock API. This clock is required by some SoCs like RZ/V2H(P) for proper DPHY configuration, whereas it is absent on others like RZ/G2L. Introduce a new `lpclk` field in the `rzg2l_mipi_dsi` structure and

[PATCH v6 06/12] drm: renesas: rz-du: mipi_dsi: Add OF data support

From: Lad Prabhakar In preparation for adding support for the Renesas RZ/V2H(P) SoC, this patch introduces a mechanism to pass SoC-specific information via OF data in the DSI driver. This enables the driver to adapt dynamically to various SoC-specific requirements without hardcoding

[PATCH v6 10/12] drm: renesas: rz-du: mipi_dsi: Add dphy_late_init() callback for RZ/V2H(P)

From: Lad Prabhakar Introduce the `dphy_late_init` callback in `rzg2l_mipi_dsi_hw_info` to allow additional D-PHY register configurations after enabling data and clock lanes. This is required for the RZ/V2H(P) SoC but not for the RZ/G2L SoC. Modify `rzg2l_mipi_dsi_startup()` to invoke

[PATCH v6 11/12] drm: renesas: rz-du: mipi_dsi: Add function pointers for configuring VCLK and mode validation

From: Lad Prabhakar Introduce `dphy_conf_clks` and `dphy_mode_clk_check` callbacks in `rzg2l_mipi_dsi_hw_info` to configure the VCLK and validate supported display modes. On the RZ/V2H(P) SoC, the DSI PLL dividers need to be as accurate as possible. To ensure compatibility with both RZ/G2L and

[PATCH v6 03/12] drm: renesas: rz-du: mipi_dsi: Add min check for VCLK range

From: Lad Prabhakar The VCLK range for Renesas RZ/G2L SoC is 5.803 MHz to 148.5 MHz. Add a minimum clock check in the mode_valid callback to ensure that the clock value does not fall below the valid range. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad

[PATCH v6 01/12] dt-bindings: display: renesas, rzg2l-du: Add support for RZ/V2H(P) SoC

From: Lad Prabhakar The DU block on the RZ/V2H(P) SoC is identical to the one found on the RZ/G2L SoC. However, it only supports the DSI interface, whereas the RZ/G2L supports both DSI and DPI interfaces. Due to this difference, a SoC-specific compatible string 'renesas,r9a09g057-du'

Re: [PATCH v5 4/4] drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC

Hi Geert, On Wed, May 28, 2025 at 1:32 PM Geert Uytterhoeven wrote: > > Hi Prabhakar, > > On Wed, 28 May 2025 at 11:48, Lad, Prabhakar > wrote: > > On Fri, May 23, 2025 at 4:19 PM Geert Uytterhoeven > > wrote: > > > On Mon, 12 May 2025 at 20:43, Prabha

Re: [PATCH v5 1/4] clk: renesas: rzv2h-cpg: Add support for DSI clocks

Hi Geert, On Wed, May 28, 2025 at 8:09 AM Geert Uytterhoeven wrote: > > Hi Prabhakar, > > On Tue, 27 May 2025 at 23:51, Lad, Prabhakar > wrote: > > On Fri, May 23, 2025 at 3:45 PM Geert Uytterhoeven > > wrote: > > > On Mon, 12 May 2025 at 20:43, Prabha

Re: [PATCH v5 4/4] drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC

Hi Geert, Thank you for the review. On Fri, May 23, 2025 at 4:19 PM Geert Uytterhoeven wrote: > > Hi Prabhakar, Fabrizio, > > On Mon, 12 May 2025 at 20:43, Prabhakar wrote: > > From: Lad Prabhakar > > > > Add DSI support for Renesas RZ/V2H(P) SoC. > >

Re: [PATCH v5 2/4] clk: renesas: r9a09g057: Add clock and reset entries for DSI and LCDC

Hi Geert, Thank you for the review. On Fri, May 23, 2025 at 3:46 PM Geert Uytterhoeven wrote: > > Hi Prabhakar, Fabrizio, > > On Mon, 12 May 2025 at 20:43, Prabhakar wrote: > > From: Lad Prabhakar > > > > Add clock and reset entries for the DSI and LCDC periph

Re: [PATCH v5 3/4] dt-bindings: display: bridge: renesas,dsi: Add support for RZ/V2H(P) SoC

Hi Geert, Thank you for the review. On Fri, May 23, 2025 at 3:58 PM Geert Uytterhoeven wrote: > > Hi Prabhakar, > > On Mon, 12 May 2025 at 20:43, Prabhakar wrote: > > From: Lad Prabhakar > > > > The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical

Re: [PATCH v5 1/4] clk: renesas: rzv2h-cpg: Add support for DSI clocks

Hi Geert, Thank you for the review. On Fri, May 23, 2025 at 3:45 PM Geert Uytterhoeven wrote: > > Hi Prabhakar, Fabrizio, > > On Mon, 12 May 2025 at 20:43, Prabhakar wrote: > > From: Lad Prabhakar > > > > Add support for PLLDSI and PLLDSI divider clocks. > &

Re: [PATCH v5 05/12] drm: renesas: rz-du: mipi_dsi: Use VCLK for HSFREQ calculation

Hi Laurent, Thank you for the review. On Tue, May 20, 2025 at 3:16 PM Laurent Pinchart wrote: > > Hi Prabhakar, > > On Mon, May 12, 2025 at 07:23:23PM +0100, Prabhakar wrote: > > From: Lad Prabhakar > > > > Update the RZ/G2L MIPI DSI driver to calculate HSFREQ

Re: [PATCH v5 06/12] drm: renesas: rz-du: mipi_dsi: Add OF data support

Hi Laurent, Thank you for the review. On Tue, May 20, 2025 at 3:22 PM Laurent Pinchart wrote: > > Hi Prabhakar, > > Thank you for the patch. > > On Mon, May 12, 2025 at 07:23:24PM +0100, Prabhakar wrote: > > From: Lad Prabhakar > > > > In preparation for add

Re: [PATCH v5 10/12] drm: renesas: rz-du: mipi_dsi: Add dphy_late_init() callback for RZ/V2H(P)

Hi Laurent, Thank you for the review. On Tue, May 20, 2025 at 3:28 PM Laurent Pinchart wrote: > > Hi Prabhakar, > > Thank you for the patch. > > On Mon, May 12, 2025 at 07:23:28PM +0100, Prabhakar wrote: > > From: Lad Prabhakar > > > > Introd

Re: [PATCH v5 04/12] drm: renesas: rz-du: mipi_dsi: Simplify HSFREQ calculation

Hi Laurent, Thank you for the review. On Tue, May 20, 2025 at 3:05 PM Laurent Pinchart wrote: > > Hi Prabhakar, > > Thank you for the patch. > > On Mon, May 12, 2025 at 07:23:22PM +0100, Prabhakar wrote: > > From: Lad Prabhakar > > > > Simplify th

Re: [PATCH v5 05/12] drm: renesas: rz-du: mipi_dsi: Use VCLK for HSFREQ calculation

Hi Geert, Thank you for the review. On Tue, May 20, 2025 at 3:55 PM Geert Uytterhoeven wrote: > > Hi Prabhakar, > > On Mon, 12 May 2025 at 20:23, Prabhakar wrote: > > From: Lad Prabhakar > > > > Update the RZ/G2L MIPI DSI driver to calculate HSFREQ using the a

Re: [PATCH v5 03/12] drm: renesas: rz-du: mipi_dsi: Add min check for VCLK range

Hi Laurent, Thank you for the review. On Tue, May 20, 2025 at 2:58 PM Laurent Pinchart wrote: > > Hi Prabhakar, > > On Mon, May 12, 2025 at 07:23:21PM +0100, Prabhakar wrote: > > From: Lad Prabhakar > > > > The VCLK range for Renesas RZ/G2L SoC is 148.5 MHz t

[PATCH v5 4/4] drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC

From: Lad Prabhakar Add DSI support for Renesas RZ/V2H(P) SoC. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar --- v4->v5: - No changes v3->v4 - In rzv2h_dphy_find_ulpsexit() made the array static const. v2->v3: - Simplifed V2H DSI timi

[PATCH v5 3/4] dt-bindings: display: bridge: renesas, dsi: Add support for RZ/V2H(P) SoC

From: Lad Prabhakar The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to that of the RZ/G2L SoC. While the LINK registers are the same for both SoCs, the D-PHY registers differ. Additionally, the number of resets for DSI on RZ/V2H(P) is two compared to three on the RZ/G2L. To

[PATCH v5 2/4] clk: renesas: r9a09g057: Add clock and reset entries for DSI and LCDC

From: Lad Prabhakar Add clock and reset entries for the DSI and LCDC peripherals. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar --- v4->v5: - No changes v3->v4: - No changes v2->v3: - Reverted CSDIV0_DIVCTL2() to use DDIV_PACK()

[PATCH v5 1/4] clk: renesas: rzv2h-cpg: Add support for DSI clocks

From: Lad Prabhakar Add support for PLLDSI and PLLDSI divider clocks. Introduce the `renesas-rzv2h-dsi.h` header to centralize and share PLLDSI-related data structures, limits, and algorithms between the RZ/V2H CPG and DSI drivers. The DSI PLL is functionally similar to the CPG's PLLDSI

[PATCH v5 0/4] Add support for DU/DSI clocks and DSI driver support for the Renesas RZ/V2H(P) SoC

From: Lad Prabhakar Hi All, This patch series adds DU/DSI clocks and provides support for the MIPI DSI interface on the RZ/V2H(P) SoC. It was originally part of series [0], but has now been split into 4 patches due to dependencies on the clock driver, making it easier to review and merge. [0

[PATCH v5 09/12] drm: renesas: rz-du: mipi_dsi: Add feature flag for 16BPP support

From: Lad Prabhakar Introduce the `RZ_MIPI_DSI_FEATURE_16BPP` flag in `rzg2l_mipi_dsi_hw_info` to indicate support for 16BPP pixel formats. The RZ/V2H(P) SoC supports 16BPP, whereas this feature is missing on the RZ/G2L SoC. Update the `mipi_dsi_host_attach()` function to check this flag before

[PATCH v5 06/12] drm: renesas: rz-du: mipi_dsi: Add OF data support

From: Lad Prabhakar In preparation for adding support for the Renesas RZ/V2H(P) SoC, this patch introduces a mechanism to pass SoC-specific information via OF data in the DSI driver. This enables the driver to adapt dynamically to various SoC-specific requirements without hardcoding

[PATCH v5 11/12] drm: renesas: rz-du: mipi_dsi: Add function pointers for configuring VCLK and mode validation

From: Lad Prabhakar Introduce `dphy_conf_clks` and `dphy_mode_clk_check` callbacks in `rzg2l_mipi_dsi_hw_info` to configure the VCLK and validate supported display modes. On the RZ/V2H(P) SoC, the DSI PLL dividers need to be as accurate as possible. To ensure compatibility with both RZ/G2L and

[PATCH v5 12/12] drm: renesas: rz-du: mipi_dsi: Add support for LPCLK clock handling

From: Lad Prabhakar Add LPCLK clock support in the RZ/G2L MIPI DSI driver via the optional clock API. This clock is required by some SoCs like RZ/V2H(P) for proper DPHY configuration, whereas it is absent on others like RZ/G2L. Introduce a new `lpclk` field in the `rzg2l_mipi_dsi` structure and

[PATCH v5 10/12] drm: renesas: rz-du: mipi_dsi: Add dphy_late_init() callback for RZ/V2H(P)

From: Lad Prabhakar Introduce the `dphy_late_init` callback in `rzg2l_mipi_dsi_hw_info` to allow additional D-PHY register configurations after enabling data and clock lanes. This is required for the RZ/V2H(P) SoC but not for the RZ/G2L SoC. Modify `rzg2l_mipi_dsi_startup()` to invoke

[PATCH v5 08/12] drm: renesas: rz-du: mipi_dsi: Use mHz for D-PHY frequency calculations

From: Lad Prabhakar Pass the HSFREQ in milli-Hz to the `dphy_init()` callback to improve precision, especially for the RZ/V2H(P) SoC, where PLL dividers require high accuracy. These changes prepare the driver for upcoming RZ/V2H(P) SoC support. Co-developed-by: Fabrizio Castro Signed-off-by

[PATCH v5 04/12] drm: renesas: rz-du: mipi_dsi: Simplify HSFREQ calculation

From: Lad Prabhakar Simplify the high-speed clock frequency (HSFREQ) calculation by removing the redundant multiplication and division by 8. The updated equation: hsfreq = (mode->clock * bpp) / (dsi->lanes); produces the same result while improving readability and clarity. Additi

[PATCH v5 05/12] drm: renesas: rz-du: mipi_dsi: Use VCLK for HSFREQ calculation

From: Lad Prabhakar Update the RZ/G2L MIPI DSI driver to calculate HSFREQ using the actual VCLK rate instead of the mode clock. The relationship between HSCLK and VCLK is: vclk * bpp <= hsclk * 8 * lanes Retrieve the VCLK rate using `clk_get_rate(dsi->vclk)`, ensuring that

[PATCH v5 07/12] drm: renesas: rz-du: mipi_dsi: Make "rst" reset control optional for RZ/V2H(P)

From: Lad Prabhakar In preparation for adding support for the Renesas RZ/V2H(P) SoC, make the "rst" reset control optional in the MIPI DSI driver. The RZ/V2H(P) SoC does not provide this reset line, and attempting to acquire it using the mandatory API causes probe failure. Sw

[PATCH v5 00/12] Add DU support for RZ/V2H(P) SoC

From: Lad Prabhakar Hi All, This patch series adds support for the Display Unit (DU) and prepares the MIPI DSI driver to support the Renesas RZ/V2H(P) SoC. These patches were originally part of series [0], but I have split them into two parts to make them easier to review and merge. This patch

[PATCH v5 03/12] drm: renesas: rz-du: mipi_dsi: Add min check for VCLK range

From: Lad Prabhakar The VCLK range for Renesas RZ/G2L SoC is 148.5 MHz to 5.803 MHz. Add a minimum clock check in the mode_valid callback to ensure that the clock value does not fall below the valid range. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad

[PATCH v5 02/12] drm: renesas: rz-du: Add support for RZ/V2H(P) SoC

From: Lad Prabhakar The LCD controller (LCDC) on the RZ/V2H(P) SoC is composed of Frame Compression Processor (FCPVD), Video Signal Processor (VSPD), and Display Unit (DU). There is one LCDC unit available on the RZ/V2H(P) SoC which is connected to the DSI. Signed-off-by: Lad Prabhakar

[PATCH v5 01/12] dt-bindings: display: renesas, rzg2l-du: Add support for RZ/V2H(P) SoC

From: Lad Prabhakar The DU block on the RZ/V2H(P) SoC is identical to the one found on the RZ/G2L SoC. However, it only supports the DSI interface, whereas the RZ/G2L supports both DSI and DPI interfaces. Due to this difference, a SoC-specific compatible string 'renesas,r9a09g057-du'

Re: [PATCH v4 14/15] drm: renesas: rz-du: mipi_dsi: Add support for LPCLK handling

Hi Biju, Thank you for the review. On Sun, May 4, 2025 at 2:00 PM Biju Das wrote: > > Hi Prabhakar, > > Thanks for the patch. > > > -Original Message- > > From: Prabhakar > > Sent: 30 April 2025 21:41 > > Subject: [PATCH v4 14/15] drm: re

Re: [PATCH v4 09/15] drm: renesas: rz-du: mipi_dsi: Add OF data support

Hi Biju, Thank you for the review. On Sun, May 4, 2025 at 1:41 PM Biju Das wrote: > > Hi Prabhakar, > > > -Original Message- > > From: Prabhakar > > Sent: 30 April 2025 21:41 > > Subject: [PATCH v4 09/15] drm: renesas: rz-du: mipi_dsi: Add OF data su

Re: [PATCH v4 08/15] drm: renesas: rz-du: mipi_dsi: Use VCLK for HSFREQ calculation

Hi Biju, Thank you for the review. On Sun, May 4, 2025 at 1:33 PM Biju Das wrote: > > Hi Prabhakar, > > > -Original Message- > > From: Prabhakar > > Sent: 30 April 2025 21:41 > > Subject: [PATCH v4 08/15] drm: renesas: rz-du: mipi_dsi: Use VCLK for &g

[PATCH] dt-bindings: gpu: mali-bifrost: Add compatible for RZ/V2N SoC

From: Lad Prabhakar Add a compatible string for the Renesas RZ/V2N SoC variants that include a Mali-G31 GPU. These variants share the same restrictions on interrupts, clocks, and power domains as the RZ/G2L SoC, so extend the existing schema validation accordingly. Signed-off-by: Lad Prabhakar

Re: [PATCH v4 01/15] clk: renesas: rzv2h-cpg: Add support for DSI clocks

Hi Fabrizio, On Thu, May 1, 2025 at 11:38 AM Fabrizio Castro wrote: > > Hi Alok, > > Thanks for your email. > > > From: ALOK TIWARI > > Sent: 01 May 2025 10:51 > > Subject: Re: [PATCH v4 01/15] clk: renesas: rzv2h-cpg: Add support for DSI > > clocks >

[PATCH v4 07/15] drm: renesas: rz-du: mipi_dsi: Simplify HSFREQ calculation

From: Lad Prabhakar Simplify the high-speed clock frequency (HSFREQ) calculation by removing the redundant multiplication and division by 8. The updated equation: hsfreq = (mode->clock * bpp) / (dsi->lanes); produces the same result while improving readability and clarity. Additi

[PATCH v4 05/15] drm: renesas: rz-du: Add support for RZ/V2H(P) SoC

From: Lad Prabhakar The LCD controller (LCDC) on the RZ/V2H(P) SoC is composed of Frame Compression Processor (FCPVD), Video Signal Processor (VSPD), and Display Unit (DU). There is one LCDC unit available on the RZ/V2H(P) SoC which is connected to the DSI. Signed-off-by: Lad Prabhakar --- v3

[PATCH v4 09/15] drm: renesas: rz-du: mipi_dsi: Add OF data support

From: Lad Prabhakar In preparation for adding support for the Renesas RZ/V2H(P) SoC, this patch introduces a mechanism to pass SoC-specific information via OF data in the DSI driver. This enables the driver to adapt dynamically to various SoC-specific requirements without hardcoding

[PATCH v4 14/15] drm: renesas: rz-du: mipi_dsi: Add support for LPCLK handling

From: Lad Prabhakar Introduce the `RZ_MIPI_DSI_FEATURE_LPCLK` feature flag in `rzg2l_mipi_dsi_hw_info` to indicate the need for LPCLK configuration. On the RZ/V2H(P) SoC, the LPCLK clock rate influences the required DPHY register configuration, whereas on the RZ/G2L SoC, this clock is not

[PATCH v4 10/15] drm: renesas: rz-du: mipi_dsi: Use mHz for D-PHY frequency calculations

From: Lad Prabhakar Pass the HSFREQ in milli-Hz to the `dphy_init()` callback to improve precision, especially for the RZ/V2H(P) SoC, where PLL dividers require high accuracy. These changes prepare the driver for upcoming RZ/V2H(P) SoC support. Co-developed-by: Fabrizio Castro Signed-off-by

[PATCH v4 13/15] drm: renesas: rz-du: mipi_dsi: Add function pointers for configuring VCLK and mode validation

From: Lad Prabhakar Introduce `dphy_conf_clks` and `dphy_mode_clk_check` callbacks in `rzg2l_mipi_dsi_hw_info` to configure the VCLK and validate supported display modes. On the RZ/V2H(P) SoC, the DSI PLL dividers need to be as accurate as possible. To ensure compatibility with both RZ/G2L and

[PATCH v4 03/15] dt-bindings: display: renesas, rzg2l-du: Add support for RZ/V2H(P) SoC

From: Lad Prabhakar The DU block on the RZ/V2H(P) SoC is identical to the one found on the RZ/G2L SoC. However, it only supports the DSI interface, whereas the RZ/G2L supports both DSI and DPI interfaces. Due to this difference, a SoC-specific compatible string 'renesas,r9a09g057-du'

[PATCH v4 11/15] drm: renesas: rz-du: mipi_dsi: Add feature flag for 16BPP support

From: Lad Prabhakar Introduce the `RZ_MIPI_DSI_FEATURE_16BPP` flag in `rzg2l_mipi_dsi_hw_info` to indicate support for 16BPP pixel formats. The RZ/V2H(P) SoC supports 16BPP, whereas this feature is missing on the RZ/G2L SoC. Update the `mipi_dsi_host_attach()` function to check this flag before

[PATCH v4 12/15] drm: renesas: rz-du: mipi_dsi: Add dphy_late_init() callback for RZ/V2H(P)

From: Lad Prabhakar Introduce the `dphy_late_init` callback in `rzg2l_mipi_dsi_hw_info` to allow additional D-PHY register configurations after enabling data and clock lanes. This is required for the RZ/V2H(P) SoC but not for the RZ/G2L SoC. Modify `rzg2l_mipi_dsi_startup()` to invoke

[PATCH v4 15/15] drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC

From: Lad Prabhakar Add DSI support for Renesas RZ/V2H(P) SoC. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar --- v3->v4 - In rzv2h_dphy_find_ulpsexit() made the array static const. v2->v3: - Simplifed V2H DSI timings array to save

[PATCH v4 01/15] clk: renesas: rzv2h-cpg: Add support for DSI clocks

From: Lad Prabhakar Add support for PLLDSI and PLLDSI divider clocks. Introduce the `renesas-rzv2h-dsi.h` header to centralize and share PLLDSI-related data structures, limits, and algorithms between the RZ/V2H CPG and DSI drivers. The DSI PLL is functionally similar to the CPG's PLLDSI

[PATCH v4 04/15] dt-bindings: display: bridge: renesas, dsi: Add support for RZ/V2H(P) SoC

From: Lad Prabhakar The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to that of the RZ/G2L SoC. While the LINK registers are the same for both SoCs, the D-PHY registers differ. Additionally, the number of resets for DSI on RZ/V2H(P) is two compared to three on the RZ/G2L. To

[PATCH v4 08/15] drm: renesas: rz-du: mipi_dsi: Use VCLK for HSFREQ calculation

From: Lad Prabhakar Update the RZ/G2L MIPI DSI driver to calculate HSFREQ using the actual VCLK rate instead of the mode clock. The relationship between HSCLK and VCLK is: vclk * bpp <= hsclk * 8 * lanes Retrieve the VCLK rate using `clk_get_rate(dsi->vclk)`, ensuring that

[PATCH v4 00/15] Add support for DU and DSI on the Renesas RZ/V2H(P) SoC

From: Lad Prabhakar From: Lad Prabhakar Hi All, This patch series adds support for the Display Unit (DU) and MIPI DSI interface on the Renesas RZ/V2H(P) SoC. The initial patches add PLLDSI clocks and reset entries for the DSI and LCDC and the later patches add support for the DU and DSI

[PATCH v4 06/15] drm: renesas: rz-du: mipi_dsi: Add min check for VCLK range

From: Lad Prabhakar The VCLK range for Renesas RZ/G2L SoC is 148.5 MHz to 5.803 MHz. Add a minimum clock check in the mode_valid callback to ensure that the clock value does not fall below the valid range. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad

[PATCH v4 02/15] clk: renesas: r9a09g057: Add clock and reset entries for DSI and LCDC

From: Lad Prabhakar Add clock and reset entries for the DSI and LCDC peripherals. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar --- v3->v4: - No changes v2->v3: - Reverted CSDIV0_DIVCTL2() to use DDIV_PACK() - Renamed plleth_lpcl

Re: [PATCH v3 10/15] drm: renesas: rz-du: mipi_dsi: Use mHz for D-PHY frequency calculations

Hi Geert, Thank you for the review. On Tue, Apr 22, 2025 at 8:41 AM Geert Uytterhoeven wrote: > > Hi Prabhakar, > > On Fri, 18 Apr 2025 at 20:47, Prabhakar wrote: > > From: Lad Prabhakar > > > > Pass the HSFREQ in milli-Hz to the `dphy_init()` callback to improve

Re: [PATCH v3 15/15] drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC

Hi Biju, Thank you for the review. On Sat, Apr 19, 2025 at 8:28 AM Biju Das wrote: > > Hi Prabhakar, > > Thanks for the patch. > > > -Original Message- > > From: Prabhakar > > Sent: 18 April 2025 19:47 > > Subject: [PATCH v3 15/15] drm: renesas: r

[PATCH v3 12/15] drm: renesas: rz-du: mipi_dsi: Add dphy_late_init() callback for RZ/V2H(P)

From: Lad Prabhakar Introduce the `dphy_late_init` callback in `rzg2l_mipi_dsi_hw_info` to allow additional D-PHY register configurations after enabling data and clock lanes. This is required for the RZ/V2H(P) SoC but not for the RZ/G2L SoC. Modify `rzg2l_mipi_dsi_startup()` to invoke

[PATCH v3 09/15] drm: renesas: rz-du: mipi_dsi: Add OF data support

From: Lad Prabhakar In preparation for adding support for the Renesas RZ/V2H(P) SoC, this patch introduces a mechanism to pass SoC-specific information via OF data in the DSI driver. This enables the driver to adapt dynamically to various SoC-specific requirements without hardcoding

[PATCH v3 15/15] drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC

From: Lad Prabhakar Add DSI support for Renesas RZ/V2H(P) SoC. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar --- v2->v3: - Simplifed V2H DSI timings array to save space - Switched to use fsleep() instead of udelay() v1->v2: - Dropped

[PATCH v3 11/15] drm: renesas: rz-du: mipi_dsi: Add feature flag for 16BPP support

From: Lad Prabhakar Introduce the `RZ_MIPI_DSI_FEATURE_16BPP` flag in `rzg2l_mipi_dsi_hw_info` to indicate support for 16BPP pixel formats. The RZ/V2H(P) SoC supports 16BPP, whereas this feature is missing on the RZ/G2L SoC. Update the `mipi_dsi_host_attach()` function to check this flag before

[PATCH v3 08/15] drm: renesas: rz-du: mipi_dsi: Use VCLK for HSFREQ calculation

From: Lad Prabhakar Update the RZ/G2L MIPI DSI driver to calculate HSFREQ using the actual VCLK rate instead of the mode clock. The relationship between HSCLK and VCLK is: vclk * bpp <= hsclk * 8 * lanes Retrieve the VCLK rate using `clk_get_rate(dsi->vclk)`, ensuring that

[PATCH v3 14/15] drm: renesas: rz-du: mipi_dsi: Add support for LPCLK handling

From: Lad Prabhakar Introduce the `RZ_MIPI_DSI_FEATURE_LPCLK` feature flag in `rzg2l_mipi_dsi_hw_info` to indicate the need for LPCLK configuration. On the RZ/V2H(P) SoC, the LPCLK clock rate influences the required DPHY register configuration, whereas on the RZ/G2L SoC, this clock is not

[PATCH v3 10/15] drm: renesas: rz-du: mipi_dsi: Use mHz for D-PHY frequency calculations

From: Lad Prabhakar Pass the HSFREQ in milli-Hz to the `dphy_init()` callback to improve precision, especially for the RZ/V2H(P) SoC, where PLL dividers require high accuracy. These changes prepare the driver for upcoming RZ/V2H(P) SoC support. Co-developed-by: Fabrizio Castro Signed-off-by

[PATCH v3 13/15] drm: renesas: rz-du: mipi_dsi: Add function pointers for configuring VCLK and mode validation

From: Lad Prabhakar Introduce `dphy_conf_clks` and `dphy_mode_clk_check` callbacks in `rzg2l_mipi_dsi_hw_info` to configure the VCLK and validate supported display modes. On the RZ/V2H(P) SoC, the DSI PLL dividers need to be as accurate as possible. To ensure compatibility with both RZ/G2L and

[PATCH v3 04/15] dt-bindings: display: bridge: renesas, dsi: Add support for RZ/V2H(P) SoC

From: Lad Prabhakar The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to that of the RZ/G2L SoC. While the LINK registers are the same for both SoCs, the D-PHY registers differ. Additionally, the number of resets for DSI on RZ/V2H(P) is two compared to three on the RZ/G2L. To

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