From: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com> Introduce the `RZ_MIPI_DSI_FEATURE_LPCLK` feature flag in `rzg2l_mipi_dsi_hw_info` to indicate the need for LPCLK configuration.
On the RZ/V2H(P) SoC, the LPCLK clock rate influences the required DPHY register configuration, whereas on the RZ/G2L SoC, this clock is not present. To accommodate this difference, add an `lpclk` clock handle in `rzg2l_mipi_dsi` and update the probe function to conditionally acquire LPCLK if the SoC supports it. Co-developed-by: Fabrizio Castro <fabrizio.castro...@renesas.com> Signed-off-by: Fabrizio Castro <fabrizio.castro...@renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com> --- v3->v4 - No changes v2->v3: - No changes v1->v2: - Added LPCLK as feature flag --- drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c index df43ff59e08e..22a386ca8ae3 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -30,6 +30,7 @@ #define RZ_MIPI_DSI_FEATURE_DPHY_RST BIT(0) #define RZ_MIPI_DSI_FEATURE_16BPP BIT(1) +#define RZ_MIPI_DSI_FEATURE_LPCLK BIT(2) struct rzg2l_mipi_dsi; @@ -63,6 +64,7 @@ struct rzg2l_mipi_dsi { struct drm_bridge *next_bridge; struct clk *vclk; + struct clk *lpclk; enum mipi_dsi_pixel_format format; unsigned int num_data_lanes; @@ -788,6 +790,12 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev) if (IS_ERR(dsi->vclk)) return PTR_ERR(dsi->vclk); + if (dsi->info->features & RZ_MIPI_DSI_FEATURE_LPCLK) { + dsi->lpclk = devm_clk_get(dsi->dev, "lpclk"); + if (IS_ERR(dsi->lpclk)) + return PTR_ERR(dsi->lpclk); + } + if (dsi->info->features & RZ_MIPI_DSI_FEATURE_DPHY_RST) { dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst"); if (IS_ERR(dsi->rstc)) -- 2.49.0