On 5/20/2025 5:55 PM, Jani Nikula wrote:
On Tue, 20 May 2025, Ankit Nautiyal wrote:
Commit 584cf613c24a ("drm/i915/dp: Reject HBR3 when sink doesn't support
TPS4") introduced a blanket rejection of HBR3 link rate when the sink does
not support TPS4. While this was intended to address instabil
On 5/21/2025 5:23 PM, Jouni Högander wrote:
Add PANEL REPLAY CAPABILITY register (0xb1) bits.
v3:
- added DP_DSC_DECODE_CAPABILITY definitions
- use defined shift instead of hardcoded value
v2: comment about DP2.1 changed as DP2.1a
Signed-off-by: Jouni Högander
Reviewed-by: Ankit Nau
On 5/21/2025 3:02 PM, Jouni Högander wrote:
Add PANEL REPLAY CAPABILITY register (0xb1) bits.
v2: comment about DP2.1 changed as DP2.1a
Signed-off-by: Jouni Högander
---
include/drm/display/drm_dp.h | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/include/drm
On 5/20/2025 10:23 PM, Jouni Högander wrote:
Add function to configre LFPS sending for Panel Replay according to link
training sequence in HAS document.
This assumes we are using AUX Less always if it's supported by the sink and
the source.
v2:
- drop HAS reference
- replay kerneldoc co
On 5/20/2025 10:23 PM, Jouni Högander wrote:
Add new definition for size of Panel Replay DPCD capability registers
area. Rename existing definitions to group capability registers together.
Signed-off-by: Jouni Högander
LGTM
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display
On 5/20/2025 10:23 PM, Jouni Högander wrote:
Add PANEL REPLAY CAPABILITY register (0xb1) bits.
Signed-off-by: Jouni Högander
---
include/drm/display/drm_dp.h | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/dr
On 5/20/2025 10:23 PM, Jouni Högander wrote:
This patch is allowing Panel Replay with VRR. All VRR modes are supposed to
I think you missed to remove `patch` from the commit message.
Regards,
Ankit
work with Panel Replay.
Bspec: 68920, 68925
Signed-off-by: Jouni Högander
Reviewed-by:
On 5/20/2025 10:23 PM, Jouni Högander wrote:
It is specified in Bspec where port alpm configuration is supposed to be
performed. Change accordingly.
v2:
- drop HAS reference
- ensure PORT_ALPM registers are not writen on older platform
Bspec: 68849
Signed-off-by: Jouni Högander
Revie
On 5/20/2025 10:23 PM, Jouni Högander wrote:
There are several Panel Replay capability register in DPCD. Read them
all for later use.
v2:
- avoid using hardcoded indices
- read all Panel Replay capability registers
Signed-off-by: Jouni Högander
Reviewed-by: Ankit Nautiyal
---
.
On 5/14/2025 4:17 PM, Jani Nikula wrote:
On Wed, 14 May 2025, Jani Nikula wrote:
On Wed, 14 May 2025, Ankit Nautiyal wrote:
This reverts commit 584cf613c24a4250d9be4819efc841aa2624d5b6.
Some eDP panels support HBR3 but not TPS4 and rely on a fixed mode that
requires HBR3. After the origina
On 4/8/2025 10:31 AM, Suraj Kandpal wrote:
According to our internal spec we need to now check if both
panel luminance and smooth brightness are available in panel for
us to be able to change brightness using luminance value.
Since DP_EDP_SMOOTH_BRIGHTNESS_CAPABLE is introduced in eDP2.0 and
On 4/10/2025 11:11 AM, Nautiyal, Ankit K wrote:
On 4/8/2025 10:31 AM, Suraj Kandpal wrote:
According to our internal spec we need to now check if both
panel luminance and smooth brightness are available in panel for
us to be able to change brightness using luminance value.
Since
On 4/8/2025 10:31 AM, Suraj Kandpal wrote:
Add DP_EDP_SMOOTH_BRIGHTNESS register bit definition for
EDP_GENERAL_CAPABILITY 2 register.
Signed-off-by: Suraj Kandpal
---
include/drm/display/drm_dp.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/display/drm_dp.h b/include/dr
On 4/2/2025 6:26 PM, Nemesa Garg wrote:
To enable or disable the sharpness check the
casf_enable flag. While enabling the sharpness
write the programmable coefficients, sharpness
register bits and also enable the scaler.
Load the filter lut value which needs to be done
one time while enabling t
On 4/2/2025 6:26 PM, Nemesa Garg wrote:
The sharpness strength value is determined by user input,
while the winsize is based on the resolution.
The casf_enable flag should be set if the platform supports
sharpness adjustments and the user API strength is not zero.
Once sharpness is enabled, upd
On 4/2/2025 6:26 PM, Nemesa Garg wrote:
Set the configuration for CASF and capture it
in crtc_state and get the configuration by
reading back. Add the support to compare the
software and hardware state of CASF.
v2: Update subject[Ankit]
v3: Add the state compare[Ankit]
Signed-off-by: Nemesa G
On 4/2/2025 6:26 PM, Nemesa Garg wrote:
Both sharpness and panel fitter uses pipe scaler,
s/uses/use
Other than that, patch looks good to me.
Reviewed-by: Ankit Nautiyal
but only one can be enabled at a time. Furthermore
sharpness uses second scaler. So for CASF, check if
second scaler
On 3/21/2025 9:36 PM, Nemesa Garg wrote:
Set the mode of scaler to HQ for casf.
Signed-off-by: Nemesa Garg
---
drivers/gpu/drm/i915/display/skl_scaler.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c
b/drivers/gpu/drm/i915/display/skl_scal
On 3/21/2025 9:36 PM, Nemesa Garg wrote:
Expose the drm crtc sharpness strength property which will enable
or disable the sharpness/casf based on user input. With this user
can set/update the strength of the sharpness or casf filter.
v2: Update subject[Ankit]
Signed-off-by: Nemesa Garg
Rev
On 3/21/2025 9:36 PM, Nemesa Garg wrote:
To enable or disable the sharpness check the
casf_enable flag. While enabling the sharpness
write the programmable coefficients, sharpness
register bits and also enable the scaler.
Load the filter lut value which needs to be done
one time while enabling
On 3/21/2025 9:36 PM, Nemesa Garg wrote:
Write the casf registers bits to enable the sharpness
Hmm, there is no write here. We are setting the configuration for CASF
and capturing it in crtc_state, and we are getting the configuration
after a read back.
Also, as mentioned, in previous pat
On 3/21/2025 9:36 PM, Nemesa Garg wrote:
Compare the sharpness win_size, strength and enable bits
Signed-off-by: Nemesa Garg
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/d
On 3/21/2025 9:36 PM, Nemesa Garg wrote:
sharpness
This again is part of subject.
As only second scaler can be used for sharpness check if it
is available and also check if panel fitting is not enabled,
then set the sharpness as both uses pipe scaler so only one
can be enabled at a time.
On 3/21/2025 9:36 PM, Nemesa Garg wrote:
coefficients
This is part of the subject, need to fix.
Regards,
Ankit
The sharpness property requires the use of one of the scaler
so need to set the sharpness scaler coefficient values.
These values are based on experiments and vary for different
On 3/21/2025 9:36 PM, Nemesa Garg wrote:
register
I think this is part of the subject, need to fix this.
The strength value for sharpness is based on user input and
the winsize is based on resolution. Set the casf_enable flag
if there is a platform support and uapi strength is not zero.
O
On 3/21/2025 9:36 PM, Nemesa Garg wrote:
HAS_CASF macro will be used to check whether platform
support the content adaptive sharpness capability or
not.
Perhaps reworded to maintain imperative mood:
Add HAS_CASF macro to check..
Otherwise LGTM.
Reviewed-by: Ankit Nautiyal
v2: Update co
On 3/4/2025 3:58 PM, Nemesa Garg wrote:
Add new registers and related bits. Compute the strength
value and tap value based on display mode.
Lets have some more details about what is strength and win size and why
is this required for sharpness.
In this what is missing is the readback part whi
On 3/4/2025 3:58 PM, Nemesa Garg wrote:
Add the macro for casf HAS_CASF.
A bit explanation about the macro and why is this introduced will be good.
Signed-off-by: Nemesa Garg
---
drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/dr
On 3/4/2025 3:58 PM, Nemesa Garg wrote:
As only second scaler can be used for sharpness check if it
is available and also check if panel fitting is also not enabled,
then set the sharpness. Panel fitting will have the preference
over sharpness property.
v2: Add the panel fitting check before e
On 3/4/2025 3:58 PM, Nemesa Garg wrote:
Once the casf_compute config is called then the
strength and win_size bit of sharpness ctl register
will be set. Read back the bits in get_config.
Signed-off-by: Nemesa Garg
---
drivers/gpu/drm/i915/display/intel_casf.c| 11 +++
drivers/gpu/d
On 3/4/2025 3:58 PM, Nemesa Garg wrote:
Add a check for enabling/disabling the casf
and enable the sharpness bit. Also load the
filter lut value which is needed one time.
Signed-off-by: Nemesa Garg
---
drivers/gpu/drm/i915/display/intel_casf.c| 18 +++
drivers/gpu/drm/i915/disp
On 3/4/2025 3:58 PM, Nemesa Garg wrote:
Expose the drm crtc sharpness property
which will ultimately enable the sharpness.
The drm crtc property is sharpness strength.
So lets have the subject and commit message in line with that.
Regards,
Ankit
Signed-off-by: Nemesa Garg
---
driver
On 3/4/2025 3:58 PM, Nemesa Garg wrote:
Compute the values for second scaler for sharpness.
Fill the register bits corresponding to the scaler.
v1: Rename the title of patch [Ankit]
Signed-off-by: Nemesa Garg
---
drivers/gpu/drm/i915/display/intel_casf.c | 3 ++
drivers/gpu/drm/i915/disp
On 3/4/2025 3:58 PM, Nemesa Garg wrote:
The sharpness property requires the use of one of the scaler
so need to set the sharpness scaler coefficient values.
These values are based on experiments and vary for different
tap value/win size. These values are normalized by taking the
sum of all valu
On 3/4/2025 3:58 PM, Nemesa Garg wrote:
Add the register bits related to filter lut values
and populate the table.
Lets have some more details about the LUT values and the fact that they
are only needed to be loaded once.
With that fixed this looks good to me.
Reviewed-by: Ankit Nautiyal
On 2/19/2025 5:23 PM, Nemesa Garg wrote:
Load the lut values during pipe enable.
v2: Add the display version check
v3: Fix build issue
v4: Rebase
v5: Add HAS_CASF macro. [Ankit]
Add scaler_id check while reading state. [Ankit]
v6: Modify the disable condition.
Signed-off-by: Nemesa Garg
On 2/19/2025 5:23 PM, Nemesa Garg wrote:
Add new registers and related bits. Compute the strength
value and tap value based on display mode.
v2: Replace i915/dev_priv with display[Jani]
v3: Create separate file for defining register[Jani]
Add display->drm in debug prints[Jani]
v4: Rebase
On 2/19/2025 5:23 PM, Nemesa Garg wrote:
As only second scaler can be used for sharpness check if it
is available and also check if panel fitting is also not enabled,
then set the sharpness. Panel fitting will have the preference
over sharpness property.
v2: Add the panel fitting check before
On 2/19/2025 5:23 PM, Nemesa Garg wrote:
Write the scaler registers for sharpness.
v1: Rename the title of patch [Ankit]
Signed-off-by: Nemesa Garg
---
drivers/gpu/drm/i915/display/intel_casf.c | 2 +
drivers/gpu/drm/i915/display/skl_scaler.c | 45 +++
drivers/gpu/dr
On 2/19/2025 5:23 PM, Nemesa Garg wrote:
The sharpness property requires the use of one of the scaler
so need to set the sharpness scaler coefficient values.
These values are based on experiments and vary for different
tap value/win size. These values are normalized by taking the
sum of all val
On 2/6/2025 1:34 PM, Zhuo, Qiuxu wrote:
Hi,
I got the compile error as below.
My GCC is: gcc (Ubuntu 7.5.0-3ubuntu1~18.04) 7.5.0
kernel: v6.14-rc1
Hi Qiuxu,
Thanks for the mail.
Fix was sent and merged in drm-intel-next :
https://cgit.freedesktop.org/drm/drm-intel/commit/?h=drm-intel-next
On 12/16/2024 11:45 PM, Suraj Kandpal wrote:
According to spec VDR_CUSTOM_WIDTH register gets programmed after pll
specific VDR registers and TX Lane programming registers are done.
Moreover we only program into C10_VDR_CONTROL1 to update config and
setup master lane once all VDR registers are
On 11/29/2024 9:56 AM, Ville Syrjala wrote:
From: Ville Syrjälä
drm_mode_vrefresh() is trying to avoid divide by zero
by checking whether htotal or vtotal are zero. But we may
still end up with a div-by-zero of vtotal*htotal*...
Cc: sta...@vger.kernel.org
Reported-by: syzbot+622bba18029bcde6
On 10/14/2024 3:09 PM, Giedrius Statkevičius wrote:
Avoid hardcoding the LSPCON settle timeout because it takes a longer
time on certain chips made by certain vendors. Use the function that
already exists to determine the timeout.
Signed-off-by: Giedrius Statkevičius
---
drivers/gpu/drm/dis
On 10/2/2024 1:19 PM, Colin Ian King wrote:
There is a spelling mistake in a drm_WARN message. Fix it.
Signed-off-by: Colin Ian King
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/g
LGTM
Reviewed-by: Ankit Nautiyal
On 7/9/2024 12:30 AM, Imre Deak wrote:
Add a helper to dump the DPCD descriptor for an LTTPR PHY. This is based
on [1] and [2] moving the helper to DRM core as suggested by Ville.
[1] https://lore.kernel.org/all/20240703155937.1674856-5-imre.d...@intel.com
[2]
On 6/12/2024 3:24 PM, Mitul Golani wrote:
Update calculation to avoid overflow.
Fixes: 1676ecd303ac ("drm/i915: Compute CMRR and calculate vtotal")
Cc: Mitul Golani
Cc: Ankit Nautiyal
Cc: Suraj Kandpal
Cc: Jani Nikula
Cc: Stephen Rothwell
Signed-off-by: Mitul Golani
Reviewed-by: Ankit
On 6/12/2024 3:24 PM, Mitul Golani wrote:
Describe newly added parameter target_rr_divider in struct
drm_dp_as_sdp.
Fixes: a20c6d954d75 ("drm/dp: Add refresh rate divider to struct representing AS
SDP")
Cc: Mitul Golani
Cc: Arun R Murthy
Cc: Suraj Kandpal
Cc: Ankit Nautiyal
Cc: Jani Nikul
On 6/7/2024 8:59 AM, Nautiyal, Ankit K wrote:
On 6/5/2024 10:31 PM, Mitul Golani wrote:
Update the indentation for the VRR register definition and
its bits, and fix checkpatch issues to ensure smooth movement
of registers and bits.
Signed-off-by: Mitul Golani
LGTM
Reviewed-by: Ankit
On 6/5/2024 10:31 PM, Mitul Golani wrote:
Update the indentation for the VRR register definition and
its bits, and fix checkpatch issues to ensure smooth movement
of registers and bits.
Signed-off-by: Mitul Golani
LGTM
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/i915_reg.h |
On 6/3/2024 11:18 AM, Mitul Golani wrote:
Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.
--v2:
- Use intel_de_read64_2x32 in intel_vrr_get
On 6/3/2024 11:18 AM, Mitul Golani wrote:
Move VRR related register definitions to a separate file called
intel_vrr_regs.h.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c | 1 +
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 113 ++
driver
On 6/3/2024 11:19 AM, Mitul Golani wrote:
Compute params for Adaptive Sync SDP when Fixed Average Vtotal
mode is enabled.
--v2:
Since vrr.enable is set in case of cmrr also, handle accordingly(Ankit).
--v3:
- Since vrr.enable is set in case of cmrr also, handle
accordingly(Ankit).
- check cmr
On 5/30/2024 11:34 AM, Mitul Golani wrote:
Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.
--v2:
- Use intel_de_read64_2x32 in intel_vrr_ge
On 5/30/2024 11:34 AM, Mitul Golani wrote:
Compute vrr vsync params in case of FAVT as well instead of
only to AVT mode of operation.
--v2:
- Remove redundant computation for vrr_vsync_start
and vrr_vsync_end(Ankit).
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c
On 5/30/2024 11:34 AM, Mitul Golani wrote:
Compute params for Adaptive Sync SDP when Fixed Average Vtotal
mode is enabled.
--v2:
Since vrr.enable is set in case of cmrr also, handle accordingly(Ankit).
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_dp.c | 17 +++
On 5/30/2024 11:34 AM, Mitul Golani wrote:
Add support of pack and unpack for target_rr_divider.
--v2:
- Set Target Refresh Rate Divider bit when related
AS SDP bit is set (Ankit).
--v3:
- target_rr_divider is bools so set accordingly (Ankit).
Signed-off-by: Mitul Golani
LGTM.
Reviewed-by
On 5/30/2024 11:34 AM, Mitul Golani wrote:
Compute Fixed Average Vtotal/CMRR with resepect to
userspace VRR enablement. Also calculate required
parameters in case of CMRR is enabled. During
intel_vrr_compute_config, CMRR is getting enabled
based on userspace has enabled Variable refresh mode
w
On 5/30/2024 11:34 AM, Mitul Golani wrote:
Add/update trans_vrr_ctl flag when crtc_state->cmrr.enable
is set, With this commit setting the stage for subsequent
CMRR enablement.
--v2:
- Check pipe active state in cmrr enabling. [Jani]
- Remove usage of bitwise OR on booleans. [Jani]
- Revert un
On 5/27/2024 1:56 PM, Animesh Manna wrote:
From: Jouni Högander
eDP1.5 adds some more bits into DP_RECEIVER_ALPM_CAP and
DP_RECEIVER_ALPM_CONFIG registers. Add definitions for these.
Signed-off-by: Jouni Högander
---
include/drm/display/drm_dp.h | 5 -
1 file changed, 4 insertions(+)
On 4/19/2024 6:05 PM, Jani Nikula wrote:
On Thu, 04 Apr 2024, "Nautiyal, Ankit K" wrote:
On 3/19/2024 3:16 PM, Maxime Ripard wrote:
On Mon, Mar 18, 2024 at 04:37:58PM +0200, Jani Nikula wrote:
On Mon, 11 Mar 2024, Mitul Golani wrote:
An Adaptive-Sync-capable DP protocol
On 3/19/2024 3:16 PM, Maxime Ripard wrote:
On Mon, Mar 18, 2024 at 04:37:58PM +0200, Jani Nikula wrote:
On Mon, 11 Mar 2024, Mitul Golani wrote:
An Adaptive-Sync-capable DP protocol converter indicates its
support by setting the related bit in the DPCD register. This
is valid for DP and ed
On 3/27/2024 7:55 PM, Imre Deak wrote:
On Wed, Mar 27, 2024 at 02:30:53PM +0530, Nautiyal, Ankit K wrote:
On 3/21/2024 1:41 AM, Imre Deak wrote:
Add a function to get the AUX device of the parent of an MST port, used
by a follow-up i915 patch in the patchset.
Cc: Lyude Paul
Cc: dri-devel
On 3/21/2024 1:41 AM, Imre Deak wrote:
Add a function to get the AUX device of the parent of an MST port, used
by a follow-up i915 patch in the patchset.
Cc: Lyude Paul
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 16 +
On 3/21/2024 1:41 AM, Imre Deak wrote:
Enabling the 5k@60Hz uncompressed mode on the MediaTek/Dell U3224KBA
monitor results in a blank screen, at least on MTL platforms on UHBR
link rates with some (<30) uncompressed bpp values. Enabling compression
fixes the problem, so do that for now. Window
On 3/21/2024 1:41 AM, Imre Deak wrote:
Factor out a function to check for UHBR channel coding support used by a
follow-up patch in the patchset.
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak
LGTM.
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c |
On 3/21/2024 1:41 AM, Imre Deak wrote:
Factor out a function to check if an MST port is logical, used by a
follow-up i915 patch in the patchset.
Cc: Lyude Paul
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 6 +++---
includ
On 3/21/2024 1:41 AM, Imre Deak wrote:
Fix the calculation of the DSC line buffer depth. This is limited both
by the source's and sink's maximum line buffer depth, but the former one
was not taken into account. On all Intel platform's the source's maximum
buffer depth is 13, so the overall limi
On 3/13/2024 9:26 AM, Mitul Golani wrote:
Compute vrr_vsync_start/end, which sets the position
for hardware to send the Vsync at a fixed position
relative to the end of the Vblank.
--v2:
- Updated VSYNC_START/END macros to VRR_VSYNC_START/END. (Ankit)
- Updated bit fields of VRR_VSYNC_START/EN
On 3/7/2024 11:23 AM, Mitul Golani wrote:
Add read/write calls for Adaptive Sync SDP.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display
On 3/7/2024 11:23 AM, Mitul Golani wrote:
Compute vrr_vsync_start/end, which sets the position
for hardware to send the Vsync at a fixed position
relative to the end of the Vblank.
--v2:
- Updated VSYNC_START/END macros to VRR_VSYNC_START/END. (Ankit)
- Updated bit fields of VRR_VSYNC_START/EN
On 3/7/2024 11:23 AM, Mitul Golani wrote:
Add the necessary structures and functions to handle reading and
unpacking Adaptive Sync Secondary Data Packets. Also add support
to write and pack AS SDP.
--v2:
- Correct use of REG_BIT and REG_GENMASK. [Jani]
- Use as_sdp instead of async. [Jani]
- R
On 3/1/2024 2:15 PM, Mitul Golani wrote:
Write/Read Adaptive sync SDP only when Sink and Source is enabled
for the same. Also along with write TRANS_VRR_VSYNC values.
The subject line and commit message need to be updated.
Now we are just enabling Adaptive sync SDP.
Regards,
Ankit
Sig
On 3/1/2024 2:15 PM, Mitul Golani wrote:
Compute vrr_vsync_start/end, which sets the position
for hardware to send the Vsync at a fixed position
relative to the end of the Vblank.
--v2:
- Updated VSYNC_START/END macros to VRR_VSYNC_START/END. (Ankit)
- Updated bit fields of VRR_VSYNC_START/END
On 3/1/2024 2:15 PM, Mitul Golani wrote:
Enable infoframe and add state checker for Adaptive Sync
SDP enablement.
--v1:
- crtc_state->infoframes.enable, to add on correct place holder.
Signed-off-by: Mitul Golani
LGTM.
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/int
On 3/1/2024 2:15 PM, Mitul Golani wrote:
Add necessary function definitions to compute AS SDP data.
The new intel_dp_compute_as_sdp function computes AS SDP
values based on the display configuration, ensuring proper
handling of Variable Refresh Rate (VRR).
--v2:
- Added DP_SDP_ADAPTIVE_SYNC to
On 3/1/2024 2:14 PM, Mitul Golani wrote:
Add a wrapper function to check if both the source and
sink support Adaptive Sync SDP.
--v1:
Just use drm/i915/dp in subject line.
Signed-off-by: Mitul Golani
LGTM.
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 8 +
On 3/1/2024 2:14 PM, Mitul Golani wrote:
Add the necessary structures and functions to handle reading and
unpacking Adaptive Sync Secondary Data Packets. Also add support
to write and pack AS SDP.
--v2:
- Correct use of REG_BIT and REG_GENMASK. [Jani]
- Use as_sdp instead of async. [Jani]
- Re
Add drm/i915/display in subject line.
With that fixed this is:
Reviewed-by: Ankit Nautiyal
On 3/1/2024 2:14 PM, Mitul Golani wrote:
Add crtc state dump for Adaptive Sync SDP to know which
crtc specifically caused the failure.
Signed-off-by: Mitul Golani
---
.../gpu/drm/i915/display/intel_
On 3/1/2024 2:14 PM, Mitul Golani wrote:
Add structure representing Adaptive Sync Secondary Data Packet (AS SDP).
Also, add Adaptive Sync SDP logging in drm_dp_helper.c to facilitate
debugging.
--v2:
- Update logging. [Jani, Ankit]
- Use 'as_sdp' instead of 'async' [Ankit]
- Correct define pla
On 3/1/2024 2:14 PM, Mitul Golani wrote:
Add an API that indicates support for Adaptive Sync SDP in
the sink, which can be utilized by the rest of the DP programming.
--v1:
- Format commit message properly.
Signed-off-by: Mitul Golani
LGTM.
Reviewed-by: Ankit Nautiyal
---
drivers/gp
On 2/29/2024 10:09 PM, Mitul Golani wrote:
Add necessary function definitions to compute AS SDP data.
The new intel_dp_compute_as_sdp function computes AS SDP
values based on the display configuration, ensuring proper
handling of Variable Refresh Rate (VRR).
--v2:
- Added DP_SDP_ADAPTIVE_SYNC
On 2/29/2024 10:09 PM, Mitul Golani wrote:
Add the necessary structures and functions to handle reading and
unpacking Adaptive Sync Secondary Data Packets. Also add support
to write and pack AS SDP.
--v2:
- Correct use of REG_BIT and REG_GENMASK. [Jani]
- Use as_sdp instead of async. [Jani]
-
On 2/29/2024 4:53 PM, Jani Nikula wrote:
On Thu, 29 Feb 2024, "Nautiyal, Ankit K" wrote:
On 2/28/2024 8:08 PM, Mitul Golani wrote:
+enum operation_mode {
+ DP_AS_SDP_AVT_DYNAMIC_VTOTAL = 0x00,
+ DP_AS_SDP_AVT_FIXED_VTOTAL = 0x01,
+ DP_AS_SDP_FAVT_TRR_NOT_REAC
On 2/28/2024 8:08 PM, Mitul Golani wrote:
Enable infoframe and add state checker for Adaptive Sync
SDP enablement.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_display.c | 46
drivers/gpu/drm/i915/display/intel_dp.c | 2 +
2 files changed,
On 2/28/2024 8:08 PM, Mitul Golani wrote:
Add necessary function definitions to compute AS SDP data.
The new intel_dp_compute_as_sdp function computes AS SDP
values based on the display configuration, ensuring proper
handling of Variable Refresh Rate (VRR).
--v2:
- Added DP_SDP_ADAPTIVE_SYNC t
On 2/28/2024 8:08 PM, Mitul Golani wrote:
Add a wrapper function to check if both the source and
sink support Adaptive Sync SDP.
Signed-off-by: Mitul Golani
Just use drm/i915/dp in subject line
Otherwise LGTM.
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_displ
On 2/28/2024 8:08 PM, Mitul Golani wrote:
Add the necessary structures and functions to handle reading and
unpacking Adaptive Sync Secondary Data Packets. Also add support
to write and pack AS SDP.
--v2:
- Correct use of REG_BIT and REG_GENMASK. [Jani]
- Use as_sdp instead of async. [Jani]
- R
On 2/28/2024 8:08 PM, Mitul Golani wrote:
Add structure representing Adaptive Sync Secondary Data Packet (AS SDP).
Also, add Adaptive Sync SDP logging in drm_dp_helper.c to facilitate
debugging.
--v2:
- Update logging. [Jani, Ankit]
- Use 'as_sdp' instead of 'async' [Ankit]
- Correct define pl
On 2/28/2024 8:08 PM, Mitul Golani wrote:
Add an API that indicates support for Adaptive Sync SDP in
the sink, which can be utilized by the rest of the DP programming.
--v1:
- Format commit message properly.
Signed-off-by: Mitul Golani
LGTM.
Reviewed-by: Ankit Nautiyal
---
drivers/gp
On 2/22/2024 5:42 PM, Mitul Golani wrote:
Compute vrr_vsync_start/end which sets the position
for hardware to send the Vsync at a fixed position
relative to the end of the Vblank.
--v2:
- Update, VSYNC_START/END macros to VRR_VSYNC_START/END.(Ankit)
- Update bit fields of VRR_VSYNC_START/END.
On 2/22/2024 5:42 PM, Mitul Golani wrote:
Add necessary functions definitions to enable
and compute AS SDP data. The new `intel_dp_compute_as_sdp`
function computes AS SDP values based on the display
configuration, ensuring proper handling of Variable Refresh
Rate (VRR).
--v2:
- Add DP_SDP_ADA
On 2/22/2024 5:42 PM, Mitul Golani wrote:
Add the necessary structures and functions to handle reading and
unpacking Adaptive Sync Secondary Data Packets. Also add support
to write and pack AS SDP.
--v2:
- Correct use of REG_BIT and REG_GENMASK. [Jani]
- Use as_sdp instead of async. [Jani]
- R
On 2/16/2024 7:50 PM, Mitul Golani wrote:
Add the necessary structures and functions to handle reading and
unpacking Adaptive Sync Secondary Data Packets. Also add support
to write and pack AS SDP.
--v2:
- Correct use of REG_BIT and REG_GENMASK. [Jani]
- Use as_sdp instead of async. [Jani]
- R
On 2/16/2024 7:50 PM, Mitul Golani wrote:
Write/Read Adaptive sync SDP only when Sink and Source is enabled
for the same. Also along with write TRANS_VRR_VSYNC values.
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4
.../gpu/drm/i915/display/inte
On 2/16/2024 7:50 PM, Mitul Golani wrote:
Compute vrr_vsync_start/end which sets the position
for hardware to send the Vsync at a fixed position
relative to the end of the Vblank.
--v2:
- Update, VSYNC_START/END macros to VRR_VSYNC_START/END.(Ankit)
- Update bit fields of VRR_VSYNC_START/END.
On 2/16/2024 7:50 PM, Mitul Golani wrote:
Add necessary functions definitions to enable
and compute AS SDP data. The new `intel_dp_compute_as_sdp`
function computes AS SDP values based on the display
configuration, ensuring proper handling of Variable Refresh
Rate (VRR).
--v2:
- Add DP_SDP_ADA
On 2/16/2024 7:50 PM, Mitul Golani wrote:
Add the necessary structures and functions to handle reading and
unpacking Adaptive Sync Secondary Data Packets. Also add support
to write and pack AS SDP.
--v2:
- Correct use of REG_BIT and REG_GENMASK. [Jani]
- Use as_sdp instead of async. [Jani]
- R
On 2/16/2024 7:50 PM, Mitul Golani wrote:
Add structure representing Adaptive Sync Secondary Data
Packet (AS SDP). Also, add Adaptive Sync SDP logging in
drm_dp_helper.c to facilitate debugging.
--v2:
- Update logging. [Jani, Ankit]
- use as_sdp instead of async [Ankit]
- Correct define placeh
On 11/10/2023 3:40 PM, Ankit Nautiyal wrote:
This patch series adds support for DSC fractional compressed bpp
for MTL+. The series starts with some fixes, followed by patches that
lay groundwork to iterate over valid compressed bpps to select the
'best' compressed bpp with optimal link configur
1 - 100 of 315 matches
Mail list logo
