On 5/20/2025 5:55 PM, Jani Nikula wrote:
On Tue, 20 May 2025, Ankit Nautiyal wrote:
Commit 584cf613c24a ("drm/i915/dp: Reject HBR3 when sink doesn't support
TPS4") introduced a blanket rejection of HBR3 link rate when the sink does
not support TPS4. While this was inte
On 5/21/2025 5:23 PM, Jouni Högander wrote:
Add PANEL REPLAY CAPABILITY register (0xb1) bits.
v3:
- added DP_DSC_DECODE_CAPABILITY definitions
- use defined shift instead of hardcoded value
v2: comment about DP2.1 changed as DP2.1a
Signed-off-by: Jouni Högander
Reviewed-by: Ankit
On 5/21/2025 3:02 PM, Jouni Högander wrote:
Add PANEL REPLAY CAPABILITY register (0xb1) bits.
v2: comment about DP2.1 changed as DP2.1a
Signed-off-by: Jouni Högander
---
include/drm/display/drm_dp.h | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/include/drm
pattern would make sense, as this is used
for other CX0 register.
Regardless of the above, patch looks good to me.
Reviewed-by: Ankit Nautiyal
+
+ intel_cx0_rmw(encoder, lane_mask, PHY_CMN1_CONTROL(tx, 0),
+ CONTROL0_MAC_TRANSMIT_LFPS,
+
On 5/20/2025 10:23 PM, Jouni Högander wrote:
Add new definition for size of Panel Replay DPCD capability registers
area. Rename existing definitions to group capability registers together.
Signed-off-by: Jouni Högander
LGTM
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915
t. DSC Decode cap is only bit #2, as per DP 2.1.
Regards,
Ankit
+# define DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR
(1 << 3)
+# define DP_PANEL_REPLAY_DSC_CRC_OF_MULTIPLE_SUS_SUPPORTED (1
<< 4)
+# define DP_PANEL_R
On 5/20/2025 10:23 PM, Jouni Högander wrote:
This patch is allowing Panel Replay with VRR. All VRR modes are supposed to
I think you missed to remove `patch` from the commit message.
Regards,
Ankit
work with Panel Replay.
Bspec: 68920, 68925
Signed-off-by: Jouni Högander
Reviewed-by
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_alpm.c| 48
drivers/gpu/drm/i915/display/intel_alpm.h| 2 +
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 1 +
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++
4 files changed, 39
On 5/20/2025 10:23 PM, Jouni Högander wrote:
There are several Panel Replay capability register in DPCD. Read them
all for later use.
v2:
- avoid using hardcoded indices
- read all Panel Replay capability registers
Signed-off-by: Jouni Högander
Reviewed-by: Ankit Nautiyal
tead reject HBR3 for specific panel that are
not able to handle HBR3 [1].
[1] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5969
Fixes: 584cf613c24a ("drm/i915/dp: Reject HBR3 when sink doesn't support TPS4")
Cc: sta...@vger.kernel.org
Cc: Jani Nikula
Cc: Ville Syr
For DP, TPS4 is a requirement for supporting HBR3, but for eDP its a
bit ambiguous. Some broken eDP sinks declare support for HBR3 without
TPS4, but are unable to produce a stable output. For these panels
add a quirk to reject HBR3 rate if TPS4 is not supported.
Signed-off-by: Ankit Nautiyal
On 5/14/2025 4:17 PM, Jani Nikula wrote:
On Wed, 14 May 2025, Jani Nikula wrote:
On Wed, 14 May 2025, Ankit Nautiyal wrote:
This reverts commit 584cf613c24a4250d9be4819efc841aa2624d5b6.
Some eDP panels support HBR3 but not TPS4 and rely on a fixed mode that
requires HBR3. After the
Revert the existing patch that rejects HBR3 for all eDP panels that
do not support TPS4. Add a patch to add a quirk for specific panels that
support HBR3 without TPS4 and are unstable with higher rate.
Reject HBR3 only for these panels.
Ankit Nautiyal (2):
Revert "drm/i915/dp: Reject HBR3
change.
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5969
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 49 -
1 file changed, 7 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers
DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE was introduced in eDP1.5
is it like that we intended this for eDP2.0 only and not for eDP1.5 panels?
This will perhaps change the behavior for existing eDP1.5 panel. Do we
need to add a fix me?
Regards,
Ankit
Signed-off-by: Suraj Kandpal
On 4/10/2025 11:11 AM, Nautiyal, Ankit K wrote:
On 4/8/2025 10:31 AM, Suraj Kandpal wrote:
According to our internal spec we need to now check if both
panel luminance and smooth brightness are available in panel for
us to be able to change brightness using luminance value.
Since
define DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE (1 << 4)
+# define DP_EDP_SMOOTH_BRIGHTNESS_CAPABLE (1 << 6)
Perhaps add eDP 2.0 in comments, as this Bit seems to be added in eDP2.0.
Regards,
Ankit
#define DP_EDP_GENERAL_CAP_3 0x704/* eDP 1.4 */
# define DP_EDP
the sharpness.
v2: Introduce casf_enable here[Ankit]
v3: Use is_disabling in casf_disabling[Ankit]
Signed-off-by: Nemesa Garg
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_casf.c| 27
drivers/gpu/drm/i915/display/intel_casf.h| 2 ++
drivers
, update the strength bit of the
register whenever the user changes the strength value,
as the enable bit and winsize bit remain constant.
v2: Introduce get_config for casf[Ankit]
Signed-off-by: Nemesa Garg
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/Makefile | 1
On 4/2/2025 6:26 PM, Nemesa Garg wrote:
Set the configuration for CASF and capture it
in crtc_state and get the configuration by
reading back. Add the support to compare the
software and hardware state of CASF.
v2: Update subject[Ankit]
v3: Add the state compare[Ankit]
Signed-off-by: Nemesa
On 4/2/2025 6:26 PM, Nemesa Garg wrote:
Both sharpness and panel fitter uses pipe scaler,
s/uses/use
Other than that, patch looks good to me.
Reviewed-by: Ankit Nautiyal
but only one can be enabled at a time. Furthermore
sharpness uses second scaler. So for CASF, check if
second scaler
t the reasoning.
Regards,
Ankit
+
/* set scaler mode */
if (plane_state && plane_state->hw.fb &&
plane_state->hw.fb->format->is_yuv &&
On 3/21/2025 9:36 PM, Nemesa Garg wrote:
Expose the drm crtc sharpness strength property which will enable
or disable the sharpness/casf based on user input. With this user
can set/update the strength of the sharpness or casf filter.
v2: Update subject[Ankit]
Signed-off-by: Nemesa Garg
the sharpness.
v2: Introduce casf_enable here[Ankit]
Signed-off-by: Nemesa Garg
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_casf.c| 27
drivers/gpu/drm/i915/display/intel_casf.h| 2 ++
drivers/gpu/drm/i915/display/intel_display.c
patch, the compare part can be clubbed here.
So we will have setting the config, getting the config and comparison in
this patch.
Regards,
Ankit
and to compute the strength of casf using casf_compute_config.
Also verify whether the enable bit is set or not and strength
value is correctly
compute, and get the config
for CASF.
Regards,
Ankit
PIPE_CONF_CHECK_X(gamma_mode);
if (display->platform.cherryview)
.
This can be improved. Avoid having one long sentence for the commit message.
Regards,
Ankit
v2: Add the panel fitting check before enabling sharpness
v3: Reframe commit message[Arun]
v4: Replace string based comparison with plane_state[Jani]
v5: Rebase
v6: Fix build issue
v7: Remove scaler
On 3/21/2025 9:36 PM, Nemesa Garg wrote:
coefficients
This is part of the subject, need to fix.
Regards,
Ankit
The sharpness property requires the use of one of the scaler
so need to set the sharpness scaler coefficient values.
These values are based on experiments and vary for
.
Once the sharpness is enabled then just update the strength
bit of the register everytime whenever user changes the strength
as enable bit and winsize bit remains constant.
v2: Introduce get_config for casf[Ankit]
Signed-off-by: Nemesa Garg
---
drivers/gpu/drm/i915/Makefile | 1
On 3/21/2025 9:36 PM, Nemesa Garg wrote:
HAS_CASF macro will be used to check whether platform
support the content adaptive sharpness capability or
not.
Perhaps reworded to maintain imperative mood:
Add HAS_CASF macro to check..
Otherwise LGTM.
Reviewed-by: Ankit Nautiyal
v2: Update
NESS_FILTER_SIZE_7X7REG_FIELD_PREP(FILTER_SIZE_MASK, 2)
+
+#endif /* __INTEL_CASF_REGS__ */
+
Remove extra line.
Regards,
Ankit
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 599ddce96371..66b6fba
ay) >= 20)
I think all other macros are in alphabetical order so would be good to
follow suite.
CMRR and AS_SDP are the exception, for which I am partly to be blamed as
a reviwer.
But lets do the right thing for CASF.
Regards,
Ankit
#define INTEL_NUM_PIPES(__display)
enabling sharpness
v3: Reframe commit message[Arun]
v4: Replace string based comparison with plane_state[Jani]
v5: Rebase
v6: Fix build issue
v7: Remove scaler id from verify_crtc_state[Ankit]
v8: Change the patch title. Add code comment.
Move the config part in patch#6. [Ankit]
Signed-off-by
ength = 0;
+ return 0;
+ }
+
All this can be part of the patch#3.
Then this function will be just calling the compute config and get
config part.
Also the subject can be improved as the patch is calling compute_config
and get_config for sharpening feature.
Regards,
Ankit
c
rength);
+
+ sharpness_ctl |= crtc_state->hw.casf_params.win_size;
+
+ intel_de_write(display, SHARPNESS_CTL(crtc->pipe), sharpness_ctl);
+}
+
Here the intel_casf_enable should be introduced for the first time as
mentioned previously just like the intel_casf_disable is introduced.
Reg
On 3/4/2025 3:58 PM, Nemesa Garg wrote:
Expose the drm crtc sharpness property
which will ultimately enable the sharpness.
The drm crtc property is sharpness strength.
So lets have the subject and commit message in line with that.
Regards,
Ankit
Signed-off-by: Nemesa Garg
On 3/4/2025 3:58 PM, Nemesa Garg wrote:
Compute the values for second scaler for sharpness.
Fill the register bits corresponding to the scaler.
v1: Rename the title of patch [Ankit]
Signed-off-by: Nemesa Garg
---
drivers/gpu/drm/i915/display/intel_casf.c | 3 ++
drivers/gpu/drm/i915
value from crtc_state[Jani]
v5: Fix build issue
v6: Add new function for writing coefficients[Ankit]
v7: Add cooments and add a scaler id check [Ankit]
Signed-off-by: Nemesa Garg
---
drivers/gpu/drm/i915/display/intel_casf.c | 124 ++
drivers/gpu/drm/i915/display
On 3/4/2025 3:58 PM, Nemesa Garg wrote:
Add the register bits related to filter lut values
and populate the table.
Lets have some more details about the LUT values and the fact that they
are only needed to be loaded once.
With that fixed this looks good to me.
Reviewed-by: Ankit Nautiyal
On 2/19/2025 5:23 PM, Nemesa Garg wrote:
Load the lut values during pipe enable.
v2: Add the display version check
v3: Fix build issue
v4: Rebase
v5: Add HAS_CASF macro. [Ankit]
Add scaler_id check while reading state. [Ankit]
v6: Modify the disable condition.
Signed-off-by: Nemesa Garg
ase
v5: Fix build issue
v6: Remove erraneous condition[Ankit]
v7: Change the place of compute function
v8: Add strength, size in crtc_state_dump.
Add bits for filter size. [Ankit]
Signed-off-by: Nemesa Garg
---
drivers/gpu/drm/i915/display/intel_casf.c | 96 +++
driv
enabling sharpness
v3: Reframe commit message[Arun]
v4: Replace string based comparison with plane_state[Jani]
v5: Rebase
v6: Fix build issue
v7: Remove scaler id from verify_crtc_state[Ankit]
v8: Change the patch title. Add code comment.
Move the config part in patch#6. [Ankit]
Signed-off-by
On 2/19/2025 5:23 PM, Nemesa Garg wrote:
Write the scaler registers for sharpness.
v1: Rename the title of patch [Ankit]
Signed-off-by: Nemesa Garg
---
drivers/gpu/drm/i915/display/intel_casf.c | 2 +
drivers/gpu/drm/i915/display/skl_scaler.c | 45 +++
drivers/gpu
value from crtc_state[Jani]
v5: Fix build issue
v6: Add new function for writing coefficients[Ankit]
v7: Add cooments and add a scaler id check [Ankit]
Signed-off-by: Nemesa Garg
Reviewed-by: Naga Venkata Srikanth V
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm
-next&id=a67221b5eb8d59fb7e1f0df3ef9945b6a0f32cca
Regards,
Ankit
--- compile error log ---
CC drivers/gpu/drm/i915/display/intel_dp.o
In file included from :0:0:
In function ‘intel_dp_dsc_compute_pipe_bpp_limits.isra.77’,
inlined from ‘intel_dp_compute_config_limits’ at
drivers
written into.
Bspec: 67636
Fixes: 51390cc0e00a ("drm/i915/mtl: Add Support for C10 PHY message bus and pll
programming")
Signed-off-by: Suraj Kandpal
Add the Bspec: 67636 as part of the trailer.
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_cx0_
gt;htotal * mode->vtotal, den, &den))
Can mode->htotal * mode->vtotal result in overflow?
and we should add:
if (check_mul_overflow(mode->htotal, mode->vtotal, &prod))
return 0;
Regards,
Ankit
+ return 0;
+
return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(num, 1000), den);
}
EXPORT_SYMBOL(drm_mode_vrefresh);
looks good to me.
Reviewed-by: Ankit Nautiyal
{
u8 data = 0;
int ret;
- int time_out = 200;
enum drm_lspcon_mode current_mode;
if (mode == DRM_LSPCON_MODE_PCON)
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c
b/drivers/gpu/drm/i915/display/inte
On 10/2/2024 1:19 PM, Colin Ian King wrote:
There is a spelling mistake in a drm_WARN message. Fix it.
Signed-off-by: Colin Ian King
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
LGTM
Reviewed-by: Ankit Nautiyal
On 7/9/2024 12:30 AM, Imre Deak wrote:
Add a helper to dump the DPCD descriptor for an LTTPR PHY. This is based
on [1] and [2] moving the helper to DRM core as suggested by Ville.
[1] https://lore.kernel.org/all/20240703155937.1674856-5-imre.d...@intel.com
[2
On 6/12/2024 3:24 PM, Mitul Golani wrote:
Update calculation to avoid overflow.
Fixes: 1676ecd303ac ("drm/i915: Compute CMRR and calculate vtotal")
Cc: Mitul Golani
Cc: Ankit Nautiyal
Cc: Suraj Kandpal
Cc: Jani Nikula
Cc: Stephen Rothwell
Signed-off-by: Mitul Golani
R
On 6/12/2024 3:24 PM, Mitul Golani wrote:
Describe newly added parameter target_rr_divider in struct
drm_dp_as_sdp.
Fixes: a20c6d954d75 ("drm/dp: Add refresh rate divider to struct representing AS
SDP")
Cc: Mitul Golani
Cc: Arun R Murthy
Cc: Suraj Kandpal
Cc: Ankit Nautiyal
On 6/7/2024 8:59 AM, Nautiyal, Ankit K wrote:
On 6/5/2024 10:31 PM, Mitul Golani wrote:
Update the indentation for the VRR register definition and
its bits, and fix checkpatch issues to ensure smooth movement
of registers and bits.
Signed-off-by: Mitul Golani
LGTM
Reviewed-by: Ankit
On 6/5/2024 10:31 PM, Mitul Golani wrote:
Update the indentation for the VRR register definition and
its bits, and fix checkpatch issues to ensure smooth movement
of registers and bits.
Signed-off-by: Mitul Golani
LGTM
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/i915_reg.h
intel_display_reg_defs.h. (Jani)
- Rename file name to intel_vrr_regs.h instead of reg.h (Jani)
--v7:
- Remove adding CMRR flag to vrr_ctl register during set_transcoder_timing,
as it is already being done during intel_vrr_enable. (Ankit)
Signed-off-by: Mitul Golani
LGTM.
Reviewed-by: Ankit
heckpatch warnings in those lines.
Perhaps you can first add a patch to fix those indexation issues in VRR
related registers in i915.reg and then simple move those regs in the new
file.
Regards,
Ankit
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6
On 6/3/2024 11:19 AM, Mitul Golani wrote:
Compute params for Adaptive Sync SDP when Fixed Average Vtotal
mode is enabled.
--v2:
Since vrr.enable is set in case of cmrr also, handle accordingly(Ankit).
--v3:
- Since vrr.enable is set in case of cmrr also, handle
accordingly(Ankit).
- check
state->cmrr.enable) {
+ intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv,
cpu_transcoder),
+ VRR_CTL_CMRR_ENABLE | trans_vrr_ctl(crtc_state));
This is not required here. We enable CMRR bit in intel_vrr_enable along
with VRR_ENABLE bit.
R
On 5/30/2024 11:34 AM, Mitul Golani wrote:
Compute vrr vsync params in case of FAVT as well instead of
only to AVT mode of operation.
--v2:
- Remove redundant computation for vrr_vsync_start
and vrr_vsync_end(Ankit).
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_vrr.c
On 5/30/2024 11:34 AM, Mitul Golani wrote:
Compute params for Adaptive Sync SDP when Fixed Average Vtotal
mode is enabled.
--v2:
Since vrr.enable is set in case of cmrr also, handle accordingly(Ankit).
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_dp.c | 17
On 5/30/2024 11:34 AM, Mitul Golani wrote:
Add support of pack and unpack for target_rr_divider.
--v2:
- Set Target Refresh Rate Divider bit when related
AS SDP bit is set (Ankit).
--v3:
- target_rr_divider is bools so set accordingly (Ankit).
Signed-off-by: Mitul Golani
LGTM.
Reviewed
precision.
- Avoid using DIV_ROUND_UP and improve scanline precision.
--v6:
- Make CMRR a small subset of FAVT mode.
--v7:
- Update commit message to avoid confusion with Legacy VRR (Ankit).
- Add cmrr.enable in last, so remove from this patch.
--v8:
- Set cmrr.enable in current patch instead of
up condition in intel_vrr_enable. [Jani]
--v4:
- Removing RFC tag.
--v5:
- CMRR handling in co-existatnce of LRR and DRRS.
--v7:
- Rebase on top of AS SDP merge.
--v8:
- Remove cmrr_enabling/disabling and update commit message. (Ankit)
--v9:
- Revert removed line(Ankit).
Signed-off-by: Mitul Gol
’s
other bits are defined in DP Standard.
In any case, patch looks good to me.
Reviewed-by: Ankit Nautiyal
Regards,
Ankit
#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
# define DP_AUX_FRAME_SYNC_CAP(1 << 0)
@@ -683,7 +685,8 @@
#define
On 4/19/2024 6:05 PM, Jani Nikula wrote:
On Thu, 04 Apr 2024, "Nautiyal, Ankit K" wrote:
On 3/19/2024 3:16 PM, Maxime Ripard wrote:
On Mon, Mar 18, 2024 at 04:37:58PM +0200, Jani Nikula wrote:
On Mon, 11 Mar 2024, Mitul Golani wrote:
An Adaptive-Sync-capable DP protocol
, Maxime, Thomas, ack for merging these two patches via
drm-intel-next?
Ack
Maxime
Thanks for the patch, ack and reviews, pushed to drm-intel-next.
Regards,
Ankit
On 3/27/2024 7:55 PM, Imre Deak wrote:
On Wed, Mar 27, 2024 at 02:30:53PM +0530, Nautiyal, Ankit K wrote:
On 3/21/2024 1:41 AM, Imre Deak wrote:
Add a function to get the AUX device of the parent of an MST port, used
by a follow-up i915 patch in the patchset.
Cc: Lyude Paul
Cc: dri-devel
>port_parent->aux;
+}
+EXPORT_SYMBOL(drm_dp_mst_aux_for_parent);
As mentioned in previous patch, the declaration of this in the header,
got included in previous patch.
Regards,
Ankit
+
/**
* drm_dp_mst_dsc_aux_for_port() - Find the correct aux for DSC
* @port: The port to chec
y to the
Synaptics hub - or the issue has another root cause, but still related
to the mode's short HBLANK duration. Enable the quirk for the monitor
adjusting the detection for the above differences.
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak
LGTM.
Reviewed-by: A
On 3/21/2024 1:41 AM, Imre Deak wrote:
Factor out a function to check for UHBR channel coding support used by a
follow-up patch in the patchset.
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak
LGTM.
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c
_aux_for_parent(struct drm_dp_mst_port *port);
This line should be part of next patch, where this helper is defined.
Otherwise LGTM.
With the above line removed, this is:
Reviewed-by: Ankit Nautiyal
Regards,
Ankit
struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port);
static inline struct drm_dp_mst_topology_state *
ogrammed as 0, leading to a
corruption in color gradients / lines on the decompressed screen image.
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak
LGTM.
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 16 ++--
include/drm/display/drm_dsc
On 3/13/2024 9:26 AM, Mitul Golani wrote:
Compute vrr_vsync_start/end, which sets the position
for hardware to send the Vsync at a fixed position
relative to the end of the Vblank.
--v2:
- Updated VSYNC_START/END macros to VRR_VSYNC_START/END. (Ankit)
- Updated bit fields of VRR_VSYNC_START
;
intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
+ intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC);
Though not related to this patch, but IMHO we can remove extra space
between consecutive intel_write_dp_sdp.
In any case, patch looks good to me.
Reviewed-by: Ankit
On 3/7/2024 11:23 AM, Mitul Golani wrote:
Compute vrr_vsync_start/end, which sets the position
for hardware to send the Vsync at a fixed position
relative to the end of the Vblank.
--v2:
- Updated VSYNC_START/END macros to VRR_VSYNC_START/END. (Ankit)
- Updated bit fields of VRR_VSYNC_START
]
- Remove unrelated comments and changes. [Jani]
- Correct code indent. [Jani]
--v3:
- Update definition names for AS SDP which are starting from
HSW, as these defines are applicable for ADLP+.(Ankit)
--v4:
- Remove as_sdp_mode from crtc_state.
- Drop metadata keyword.
- For consistency, update ADL_
On 3/1/2024 2:15 PM, Mitul Golani wrote:
Write/Read Adaptive sync SDP only when Sink and Source is enabled
for the same. Also along with write TRANS_VRR_VSYNC values.
The subject line and commit message need to be updated.
Now we are just enabling Adaptive sync SDP.
Regards,
Ankit
On 3/1/2024 2:15 PM, Mitul Golani wrote:
Compute vrr_vsync_start/end, which sets the position
for hardware to send the Vsync at a fixed position
relative to the end of the Vblank.
--v2:
- Updated VSYNC_START/END macros to VRR_VSYNC_START/END. (Ankit)
- Updated bit fields of VRR_VSYNC_START
On 3/1/2024 2:15 PM, Mitul Golani wrote:
Enable infoframe and add state checker for Adaptive Sync
SDP enablement.
--v1:
- crtc_state->infoframes.enable, to add on correct place holder.
Signed-off-by: Mitul Golani
LGTM.
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/disp
to infoframe_type_to_idx(). [Ankit]
- Separated patch for intel_read/write_dp_sdp. [Ankit]
- _HSW_VIDEO_DIP_ASYNC_DATA_A should be from ADL onward. [Ankit]
- Fixed indentation issues. [Ankit]
--v3:
- Added VIDEO_DIP_ENABLE_AS_HSW flag to intel_dp_set_infoframes.
--v4:
- Added HAS_VRR check before
On 3/1/2024 2:14 PM, Mitul Golani wrote:
Add a wrapper function to check if both the source and
sink support Adaptive Sync SDP.
--v1:
Just use drm/i915/dp in subject line.
Signed-off-by: Mitul Golani
LGTM.
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_dp.c | 8
]
- Remove unrelated comments and changes. [Jani]
- Correct code indent. [Jani]
--v3:
- Update definition names for AS SDP which are starting from
HSW, as these defines are applicable for ADLP+.(Ankit)
--v4:
- Remove as_sdp_mode from crtc_state.
- Drop metadata keyword.
- For consistency, update ADL_
Add drm/i915/display in subject line.
With that fixed this is:
Reviewed-by: Ankit Nautiyal
On 3/1/2024 2:14 PM, Mitul Golani wrote:
Add crtc state dump for Adaptive Sync SDP to know which
crtc specifically caused the failure.
Signed-off-by: Mitul Golani
---
.../gpu/drm/i915/display
On 3/1/2024 2:14 PM, Mitul Golani wrote:
Add structure representing Adaptive Sync Secondary Data Packet (AS SDP).
Also, add Adaptive Sync SDP logging in drm_dp_helper.c to facilitate
debugging.
--v2:
- Update logging. [Jani, Ankit]
- Use 'as_sdp' instead of 'async' [Ank
On 3/1/2024 2:14 PM, Mitul Golani wrote:
Add an API that indicates support for Adaptive Sync SDP in
the sink, which can be utilized by the rest of the DP programming.
--v1:
- Format commit message properly.
Signed-off-by: Mitul Golani
LGTM.
Reviewed-by: Ankit Nautiyal
---
drivers
to infoframe_type_to_idx(). [Ankit]
- Separated patch for intel_read/write_dp_sdp. [Ankit]
- _HSW_VIDEO_DIP_ASYNC_DATA_A should be from ADL onward. [Ankit]
- Fixed indentation issues. [Ankit]
--v3:
- Added VIDEO_DIP_ENABLE_AS_HSW flag to intel_dp_set_infoframes.
--v4:
- Added HAS_VRR check before
]
- Remove unrelated comments and changes. [Jani]
- Correct code indent. [Jani]
--v3:
- Update definition names for AS SDP which are starting from
HSW, as these defines are applicable for ADLP+.(Ankit)
--v4:
- Remove as_sdp_mode from crtc_state.
- Drop metadata keyword.
- For consistency, update ADL_
On 2/29/2024 4:53 PM, Jani Nikula wrote:
On Thu, 29 Feb 2024, "Nautiyal, Ankit K" wrote:
On 2/28/2024 8:08 PM, Mitul Golani wrote:
+enum operation_mode {
+ DP_AS_SDP_AVT_DYNAMIC_VTOTAL = 0x00,
+ DP_AS_SDP_AVT_FIXED_VTOTAL = 0x01,
+ DP_AS_SDP_FAVT_TRR_NOT_REAC
as_sdp->duration_incr_ms = 0;
as_sdp->duration_incr_ms = 0;
+
+ crtc_state->infoframes.enable |=
intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
This change does not seem to belong to this patch.
Regards,
Ankit
}
static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
to infoframe_type_to_idx(). [Ankit]
- Separated patch for intel_read/write_dp_sdp. [Ankit]
- _HSW_VIDEO_DIP_ASYNC_DATA_A should be from ADL onward. [Ankit]
- Fixed indentation issues. [Ankit]
--v3:
- Added VIDEO_DIP_ENABLE_AS_HSW flag to intel_dp_set_infoframes.
--v4:
- Added HAS_VRR check before
On 2/28/2024 8:08 PM, Mitul Golani wrote:
Add a wrapper function to check if both the source and
sink support Adaptive Sync SDP.
Signed-off-by: Mitul Golani
Just use drm/i915/dp in subject line
Otherwise LGTM.
Reviewed-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display
]
- Remove unrelated comments and changes. [Jani]
- Correct code indent. [Jani]
--v3:
- Update definition names for AS SDP which are starting from
HSW, as these defines are applicable for ADLP+.(Ankit)
--v4:
- Remove as_sdp_mode from crtc_state.
- Drop metadata keyword.
- For consistency, update ADL_
On 2/28/2024 8:08 PM, Mitul Golani wrote:
Add structure representing Adaptive Sync Secondary Data Packet (AS SDP).
Also, add Adaptive Sync SDP logging in drm_dp_helper.c to facilitate
debugging.
--v2:
- Update logging. [Jani, Ankit]
- Use 'as_sdp' instead of 'async' [Ank
On 2/28/2024 8:08 PM, Mitul Golani wrote:
Add an API that indicates support for Adaptive Sync SDP in
the sink, which can be utilized by the rest of the DP programming.
--v1:
- Format commit message properly.
Signed-off-by: Mitul Golani
LGTM.
Reviewed-by: Ankit Nautiyal
---
drivers
On 2/22/2024 5:42 PM, Mitul Golani wrote:
Compute vrr_vsync_start/end which sets the position
for hardware to send the Vsync at a fixed position
relative to the end of the Vblank.
--v2:
- Update, VSYNC_START/END macros to VRR_VSYNC_START/END.(Ankit)
- Update bit fields of VRR_VSYNC_START/END
DP_SDP_ADAPTIVE_SYNC to infoframe_type_to_idx().[Ankit]
- separate patch for intel_read/write_dp_sdp [Ankit].
- _HSW_VIDEO_DIP_ASYNC_DATA_A should be from ADL onward [Ankit]
- To fix indentation [Ankit]
--v3:
- Add VIDEO_DIP_ENABLE_AS_HSW flag to intel_dp_set_infoframes.
--v4:
- Add HAS_VRR check before
]
- Remove unrelated comments and changes. [Jani]
- Correct code indent. [Jani]
--v3:
- Update definition names for AS SDP which are starting from
HSW, as these defines are applicable for ADLP+.(Ankit)
Signed-off-by: Mitul Golani
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers
]
- Remove unrelated comments and changes. [Jani]
- Correct code indent. [Jani]
--v3:
- Update definition names for AS SDP which are starting from
HSW, as these defines are applicable for ADLP+.(Ankit)
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_dp.c | 95
vrr.flipline - 1);
+
+ if (is_as_sdp_enabled)
As mentioned in Patch#4, lets use the crtc_state->vrr.as_sdp_enable,
instead of this.
Regards,
Ankit
+ intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder),
+ crtc_state->vrr.vsync_end << 16 |
crtc_state->vrr.vsync_start);
}
void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
On 2/16/2024 7:50 PM, Mitul Golani wrote:
Compute vrr_vsync_start/end which sets the position
for hardware to send the Vsync at a fixed position
relative to the end of the Vblank.
--v2:
- Update, VSYNC_START/END macros to VRR_VSYNC_START/END.(Ankit)
- Update bit fields of VRR_VSYNC_START/END
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