My current email address will stop working soon. Use
linux.dev email instead.
Signed-off-by: Abhinav Kumar
---
MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index
3bc0da6f9033be0d5da35210a84ba189be4e5c0c
I will no longer regularly work on this platform. Hence will
step down from maintainer duties.
Also, add Jessica as a reviewer to the MSM DRM subsystem to help
out with the reviews.
Signed-off-by: Abhinav Kumar
---
MAINTAINERS | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
: lu...@kernel.org
Cc: robdcl...@gmail.com
Cc: freedr...@lists.freedesktop.org
Cc: linux-arm-...@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Abhinav Kumar
---
Abhinav Kumar (2):
MAINTAINERS: drop myself as maintainer
MAINTAINERS: update my email address
On 12/23/2024 10:32 PM, Dmitry Baryshkov wrote:
On Wed, Dec 04, 2024 at 12:32:55PM +0200, Dmitry Baryshkov wrote:
On Tue, Dec 03, 2024 at 07:24:46PM -0800, Abhinav Kumar wrote:
On 12/3/2024 5:53 AM, Dmitry Baryshkov wrote:
On Mon, Dec 02, 2024 at 04:39:01PM -0800, Abhinav Kumar wrote
Hi Jens
On 5/10/2025 5:12 AM, Jens Glathe wrote:
On 06.12.24 05:31, Abhinav Kumar wrote:
base-commit: b166256c1e6ce356fa1404d4c8531830e6f100a8
Hi Abhinav,
I would like to test / play around with this patchset, unfortunately
this base commit is not easy to find. Trying to apply without
On 5/7/2025 11:18 PM, Krzysztof Kozlowski wrote:
On 23/04/2025 04:46, Abhinav Kumar wrote:
Hi Krzysztof
On 12/3/2024 12:04 AM, Krzysztof Kozlowski wrote:
On 03/12/2024 04:31, Abhinav Kumar wrote:
On some chipsets the display port controller can support more
Which chipsets?
From the
On 4/23/2025 7:23 AM, Dmitry Baryshkov wrote:
On Tue, Apr 22, 2025 at 07:46:57PM -0700, Abhinav Kumar wrote:
On 12/3/2024 5:43 AM, Dmitry Baryshkov wrote:
On Mon, Dec 02, 2024 at 07:31:41PM -0800, Abhinav Kumar wrote:
On some chipsets the display port controller can support more
than one
On 5/5/2025 5:24 AM, Dmitry Baryshkov wrote:
On Wed, Apr 30, 2025 at 03:00:51PM +0200, Krzysztof Kozlowski wrote:
v12.0 DPU on SM8750 comes with 10-bit color alpha. Add register
differences and new implementations of setup_alpha_out(),
setup_border_color() and setup_blend_config().
Reviewed
Hi Alex
On 5/7/2025 3:01 PM, Aleksandrs Vinarskis wrote:
On Tue, 6 May 2025 at 01:41, Abhinav Kumar wrote:
Hi Alex
On 5/4/2025 3:06 PM, Aleksandrs Vinarskis wrote:
On Sun, 4 May 2025 at 05:02, Abhinav Kumar wrote:
Hi Alex
Thanks for the response.
My updates below. I also had one
Hi Alex
On 5/4/2025 3:06 PM, Aleksandrs Vinarskis wrote:
On Sun, 4 May 2025 at 05:02, Abhinav Kumar wrote:
Hi Alex
Thanks for the response.
My updates below. I also had one question for Abel below.
Thanks
Abhinav
On 5/1/2025 8:56 AM, Aleksandrs Vinarskis wrote:
On Thu, 1 May 2025 at 04
On 5/5/2025 5:35 AM, Dmitry Baryshkov wrote:
On Wed, Apr 30, 2025 at 03:00:49PM +0200, Krzysztof Kozlowski wrote:
Add support for DSI on Qualcomm SM8750 SoC with notable difference:
DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as
parents before DSI PHY is configured, th
Hi Alex
Thanks for the response.
My updates below. I also had one question for Abel below.
Thanks
Abhinav
On 5/1/2025 8:56 AM, Aleksandrs Vinarskis wrote:
On Thu, 1 May 2025 at 04:11, Abhinav Kumar wrote:
On 4/29/2025 5:09 PM, Aleksandrs Vinarskis wrote:
DisplayPort requires per
On 4/29/2025 5:09 PM, Aleksandrs Vinarskis wrote:
DisplayPort requires per-segment link training when LTTPR are switched
to non-transparent mode, starting with LTTPR closest to the source.
Only when each segment is trained individually, source can link train
to sink.
Implement per-segment lin
ewed-by: Dmitry Baryshkov
Signed-off-by: Aleksandrs Vinarskis
Tested-by: Johan Hovold
Tested-by: Rob Clark
---
drivers/gpu/drm/msm/dp/dp_display.c | 17 +++--
drivers/gpu/drm/msm/dp/dp_link.h| 1 +
2 files changed, 12 insertions(+), 6 deletions(-)
Reviewed-by: Abhinav Kumar
eviewed-by: Abhinav Kumar
deletions(-)
No need to resend for this, I can even fix it up while applying,
With that addressed,
Reviewed-by: Abhinav Kumar
On 4/13/2025 9:32 AM, Dmitry Baryshkov wrote:
If the Adreno device is used in a headless mode, there is no need to
build all KMS components. Build corresponding parts conditionally, only
selecting them if modeset support is actually required.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu
drivers/gpu/drm/msm/msm_kms.h | 2 ++
3 files changed, 25 insertions(+), 6 deletions(-)
Reviewed-by: Abhinav Kumar
On 4/15/2025 1:59 AM, Dmitry Baryshkov wrote:
On 14/04/2025 18:58, Rob Clark wrote:
On Sun, Apr 13, 2025 at 9:33 AM Dmitry Baryshkov
wrote:
The global workqueue is only used for vblanks inside KMS code. Move
allocation / flushing / deallcation of it to msm_kms.c
Maybe we should also just
try Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_audio.c | 107 +++---
1 file changed, 9 insertions(+), 98 deletions(-)
LGTM,
Reviewed-by: Abhinav Kumar
Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
Reviewed-by: Abhinav Kumar
On 4/29/2025 5:16 AM, Dmitry Baryshkov wrote:
On Mon, Apr 28, 2025 at 06:33:05PM -0700, Abhinav Kumar wrote:
On 3/1/2025 1:24 AM, Dmitry Baryshkov wrote:
Neither DPU driver nor vendor SDE driver do not use TE2 definitions
(and, in case of SDE driver, never did). Semantics of the TE2
R).
Fixes: 7204df5e7e68 ("drm/msm/dpu: add support for SDM660 and SDM630 platforms")
Reported-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
Note, Konrad pointed out that vendor DT doesn't define DIPTHER support
for this platform, however I believe this is because support for this
On 3/1/2025 1:24 AM, Dmitry Baryshkov wrote:
Neither DPU driver nor vendor SDE driver do not use TE2 definitions
(and, in case of SDE driver, never did). Semantics of the TE2 feature
bit and .te2 sblk are not completely clear. Drop these bits from the
catalog with the possibility of reintroduc
completely.
Fixes: 7a6109ce1c2c ("drm/msm/dpu: Add support for MSM8953")
Reported-by: Abhinav Kumar
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 2 --
1 file changed, 2 deletions(-)
Reviewed-by: Abhinav Kumar
completely.
Fixes: 62af6e1cb596 ("drm/msm/dpu: Add support for MSM8917")
Reported-by: Abhinav Kumar
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 1 -
1 file changed, 1 deletion(-)
Reviewed-by: Abhinav Kumar
completely.
Fixes: c079680bb0fa ("drm/msm/dpu: Add support for MSM8937")
Reported-by: Abhinav Kumar
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 2 --
1 file changed, 2 deletions(-)
Reviewed-by: Abhinav Kumar
;
+ if (ret == -ENODEV)
+ return 0;
+ return ret;
+ }
Alright, I think this will protect us against the fact that there is no
panel in the DT currently like before, hence
Reviewed-by: Abhinav Kumar
On 4/25/2025 2:27 AM, Dmitry Baryshkov wrote:
On Fri, 25 Apr 2025 at 00:00, Abhinav Kumar wrote:
On 4/24/2025 3:23 AM, Dmitry Baryshkov wrote:
On Wed, Apr 23, 2025 at 07:04:16PM -0700, Abhinav Kumar wrote:
On 2/26/2025 6:25 PM, Dmitry Baryshkov wrote:
LVDS support in MDP4 driver
---
3 files changed, 34 insertions(+), 16 deletions(-)
Reviewed-by: Abhinav Kumar
On 4/25/2025 12:10 PM, Dmitry Baryshkov wrote:
On Thu, Apr 24, 2025 at 06:55:50PM -0700, Abhinav Kumar wrote:
On 4/23/2025 10:52 AM, Dmitry Baryshkov wrote:
From: Dmitry Baryshkov
The MSM DisplayPort driver implements several HDMI codec functions
in the driver, e.g. it manually manages
On 4/25/2025 12:00 PM, Dmitry Baryshkov wrote:
On Fri, Apr 25, 2025 at 11:34:18AM -0700, Jessica Zhang wrote:
On 3/7/2025 9:38 PM, Dmitry Baryshkov wrote:
From: Abhinav Kumar
In order to support more versatile configuration of the display pipes on
SC8280XP, enable SmartDMA for this
On 4/23/2025 10:52 AM, Dmitry Baryshkov wrote:
From: Dmitry Baryshkov
The MSM DisplayPort driver implements several HDMI codec functions
in the driver, e.g. it manually manages HDMI codec device registration,
returning ELD and plugged_cb support. In order to reduce code
duplication reuse drm
On 4/24/2025 3:23 AM, Dmitry Baryshkov wrote:
On Wed, Apr 23, 2025 at 07:04:16PM -0700, Abhinav Kumar wrote:
On 2/26/2025 6:25 PM, Dmitry Baryshkov wrote:
LVDS support in MDP4 driver makes use of drm_connector directly. However
LCDC encoder and LVDS connector are wrappers around drm_panel
On 4/24/2025 3:22 AM, Dmitry Baryshkov wrote:
On Wed, Apr 23, 2025 at 03:54:13PM -0700, Abhinav Kumar wrote:
On 2/26/2025 6:25 PM, Dmitry Baryshkov wrote:
The LVDS/LCDC controller uses pixel clock coming from the multimedia
controller (mmcc) rather than using the PLL directly. Stop using
On 2/26/2025 6:25 PM, Dmitry Baryshkov wrote:
LVDS support in MDP4 driver makes use of drm_connector directly. However
LCDC encoder and LVDS connector are wrappers around drm_panel. Switch
them to use drm_panel_bridge/drm_bridge_connector. This allows using
standard interface for the drm_panel
On 2/26/2025 6:25 PM, Dmitry Baryshkov wrote:
The LVDS/LCDC controller uses pixel clock coming from the multimedia
controller (mmcc) rather than using the PLL directly. Stop using LVDS
PLL directly and register it as a clock provider. Use lcdc_clk as a
pixel clock for the LCDC.
Reviewed-by: K
/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c | 27 --
.../gpu/drm/msm/disp/mdp4/mdp4_lvds_connector.c| 21 -
3 files changed, 20 insertions(+), 29 deletions(-)
Reviewed-by: Abhinav Kumar
/mdp4_lvds_pll.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Abhinav Kumar
(-)
Reviewed-by: Abhinav Kumar
dpu_plane_try_multirect_shared(struct dpu_plane_state *pstate,
+ struct dpu_plane_state
*prev_adjancent_pstate,
pls fix typo
prev_adjancent_pstate ---> prev_adjacent_pstate in this entire function
With that fixed,
Reviewed-by: Abhinav Ku
On 12/3/2024 5:43 AM, Dmitry Baryshkov wrote:
On Mon, Dec 02, 2024 at 07:31:41PM -0800, Abhinav Kumar wrote:
On some chipsets the display port controller can support more
than one pixel stream (multi-stream transport). To support MST
on such chipsets, add the binding for stream 1 pixel clock
Hi Krzysztof
On 12/3/2024 12:04 AM, Krzysztof Kozlowski wrote:
On 03/12/2024 04:31, Abhinav Kumar wrote:
On some chipsets the display port controller can support more
Which chipsets?
From the current list of chipsets which support DP, the following can
support more than one stream
, 2024 at 03:41:48PM +0200, Dmitry Baryshkov wrote:
On Tue, Dec 03, 2024 at 09:01:31AM +0100, Krzysztof Kozlowski wrote:
On 03/12/2024 04:31, Abhinav Kumar wrote:
Document the assigned-clock-parents better for the DP controller node
to indicate its functionality better.
You change the clocks
Hi Krzysztof
Sorry for the delayed response.
On 12/3/2024 12:01 AM, Krzysztof Kozlowski wrote:
On 03/12/2024 04:31, Abhinav Kumar wrote:
Display port controller on some MSM chipsets are capable of supporting
multiple streams. In order to distinguish the streams better, describe
the current
m8996.h | 4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 3 ---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 2 --
6 files changed, 15 deletions(-)
Reviewed-by: Abhinav Kumar
deletions(-)
Reviewed-by: Abhinav Kumar
.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Abhinav Kumar
--
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 3 +++
1 file changed, 3 insertions(+)
Reviewed-by: Abhinav Kumar
deletion(-)
Fixes: 795aef6f3653 ("drm/msm/dpu: remove duplicate code calculating sum
of bandwidths")
Good catch!
Reviewed-by: Abhinav Kumar
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 7ff3405c68675..0fb5789c60
On 3/5/2025 10:44 PM, Dmitry Baryshkov wrote:
On Wed, Mar 05, 2025 at 07:16:51PM -0800, Jessica Zhang wrote:
Similar to WB_MUX, CDM_MUX also needs to be adjusted to support
dedicated CWB PINGPONGs
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c | 4 +++-
1 fil
fixes tag to use here, but
since this should have ideally been addressed together while adding the
WB mux programming to handle CWB, I am going with
Fixes: a31a610fd44b ("drm/msm/dpu: add CWB support to dpu_hw_wb")
Reviewed-by: Abhinav Kumar
diff --git a/drivers/gpu/drm/msm
/dpu_9_0_sm8550.h | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 4 ++--
12 files changed, 24 insertions(+), 24 deletions(-)
Good catch!
Fixes: 15f2825defeb ("drm/msm/dpu: enable CDM_0 for DPUs 5.x+")
Reviewed-by: Abhinav Kumar
Dmitry Baryshkov
+Dmitry Baryshkov <[dbarysh...@gmail.com]>
+Dmitry Baryshkov
+Dmitry Baryshkov
+Dmitry Baryshkov
Dmitry Safonov <0x7f454...@gmail.com>
Dmitry Safonov <0x7f454...@gmail.com>
Dmitry Safonov <0x7f454...@gmail.com>
Acked-by: Abhinav Kumar
29e1a423eee5bcf9df7938aaffe5bd3e2f6a2bbe..b3a67e278a839fa14d1329a249ecf4bbec00c26c
100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7459,7 +7459,7 @@ F:include/uapi/drm/msm_drm.h
DRM DRIVER for Qualcomm display hardware
M:Rob Clark
M:Abhinav Kumar
-M: Dmitry Baryshkov
+M: Dmitry Baryshkov
On 3/4/2025 7:09 PM, Dmitry Baryshkov wrote:
On Wed, 5 Mar 2025 at 00:43, Abhinav Kumar wrote:
On 3/4/2025 12:42 PM, Dmitry Baryshkov wrote:
On Tue, Mar 04, 2025 at 11:38:24AM -0800, Abhinav Kumar wrote:
On 3/3/2025 9:32 PM, Dmitry Baryshkov wrote:
On Tue, 4 Mar 2025 at 03:44
On 3/4/2025 12:42 PM, Dmitry Baryshkov wrote:
On Tue, Mar 04, 2025 at 11:38:24AM -0800, Abhinav Kumar wrote:
On 3/3/2025 9:32 PM, Dmitry Baryshkov wrote:
On Tue, 4 Mar 2025 at 03:44, Jessica Zhang wrote:
On 3/3/2025 3:49 PM, Dmitry Baryshkov wrote:
On Mon, Mar 03, 2025 at 10:28:00AM
msm/-/issues/59
Thanks,
Jessica Zhang
Note: This patch only adds tracking for the CTL reservation, but eventually
all HW blocks used by encoders (i.e. DSC, PINGPONG, CWB) should have a
similar check to avoid the same issue.
Suggested-by: Abhinav Kumar
Closes:
https://lists.freedesktop
On 2/24/2025 7:14 PM, Dmitry Baryshkov wrote:
On Mon, 24 Feb 2025 at 20:59, Abhinav Kumar wrote:
On 2/19/2025 9:08 AM, Dmitry Baryshkov wrote:
On Wed, Feb 19, 2025 at 06:02:20PM +0100, Krzysztof Kozlowski wrote:
On 17/02/2025 19:58, Dmitry Baryshkov wrote:
On Mon, Feb 17, 2025 at 05
)
Signed-off-by: Dan Carpenter
---
drivers/gpu/drm/msm/msm_kms.c | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Abhinav Kumar
On 2/19/2025 9:08 AM, Dmitry Baryshkov wrote:
On Wed, Feb 19, 2025 at 06:02:20PM +0100, Krzysztof Kozlowski wrote:
On 17/02/2025 19:58, Dmitry Baryshkov wrote:
On Mon, Feb 17, 2025 at 05:41:26PM +0100, Krzysztof Kozlowski wrote:
Add DisplayPort controller for Qualcomm SM8750 SoC which so fa
for (i = 0; i < num_planes; i++) {
struct drm_plane_state *plane_state = states[i];
@@ -1174,9 +1274,12 @@ int dpu_assign_plane_resources(struct dpu_global_state
*global_state,
continue;
ret = dpu_plane_virtual_assign_resources(crtc, global_state,
-
files changed, 11 insertions(+)
Reviewed-by: Abhinav Kumar
users to go beyond these values and check whether this makes any
difference or fixes the issue.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 36 +--
1 file changed, 18 insertions(+), 18 deletions(-)
Reviewed-by: Abhinav Kumar
changed, 1 insertion(+), 3 deletions(-)
Reviewed-by: Abhinav Kumar
(+), 4 deletions(-)
Reviewed-by: Abhinav Kumar
would have been more accurate, but this is okay
Reviewed-by: Abhinav Kumar
rs/gpu/drm/msm/dsi/dsi_host.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
Reviewed-by: Abhinav Kumar
57897058
[2/4] drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG1 against clock driver
https://gitlab.freedesktop.org/drm/msm/-/commit/5a97bc924ae0
[3/4] drm/msm/dsi/phy: Do not overwite PHY_CMN_CLK_CFG1 when choosing bitclk
source
https://gitlab.freedesktop.org/drm/msm/-/commit/73f69c6be2a9
Best regards,
--
Abhinav Kumar
92eefebaa
Best regards,
--
Abhinav Kumar
/dpu: Don't leak bits_per_component into random DSC_ENC fields
https://gitlab.freedesktop.org/drm/msm/-/commit/144429831f44
Best regards,
--
Abhinav Kumar
enabled dither.
>
>
> [...]
Applied to msm-fixes, thanks!
[1/1] drm/msm/dpu: Disable dither in phys encoder cleanup
https://gitlab.freedesktop.org/drm/msm/-/commit/f063ac6b55df
Best regards,
--
Abhinav Kumar
itialized variable
https://gitlab.freedesktop.org/drm/msm/-/commit/978ca99d6bd8
Best regards,
--
Abhinav Kumar
On Thu, 06 Feb 2025 11:46:36 -0800, Abhinav Kumar wrote:
> Widebus allows the DP controller to operate in 2 pixel per clock mode.
> The mode validation logic validates the mode->clock against the max
> DP pixel clock. However the max DP pixel clock limit assumes widebus
> is
hanks!
[1/1] drm/msm/dpu: correct LM pairing for SM6150
https://gitlab.freedesktop.org/drm/msm/-/commit/24b50b7340ab
Best regards,
--
Abhinav Kumar
https://gitlab.freedesktop.org/drm/msm/-/commit/af0a4a2090cc
Best regards,
--
Abhinav Kumar
eviewed-by: Abhinav Kumar
| 35 ++
.../gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 5 +++-
2 files changed, 26 insertions(+), 14 deletions(-)
Reviewed-by: Abhinav Kumar
On 2/12/2025 4:04 PM, Dmitry Baryshkov wrote:
On Wed, Feb 12, 2025 at 03:03:47PM -0800, James A. MacInnes wrote:
Type-C DisplayPort inoperable due to incorrect porch settings.
- Re-used wide_bus_en as flag to prevent porch shifting
Unfortunately I don't know enough details to comment on thi
and ensured no other SoCs
are suffering from a similar problem.
- Marijn
Its indeed a bug introduced due to msm_dp_desc_sc7180 re-use. There is
no widebus on this chipset.
With the commit text fixed like above,
Reviewed-by: Abhinav Kumar
Fixes: c7c412202623 ("drm/msm/dp: enab
On 2/11/2025 4:19 PM, Abhinav Kumar wrote:
On 2/11/2025 4:13 PM, Dmitry Baryshkov wrote:
On Tue, Feb 11, 2025 at 10:23:54AM +0100, Marijn Suijten wrote:
On 2025-02-10 14:14:14, Abhinav Kumar wrote:
On 2/9/2025 7:51 PM, Ethan Carter Edwards wrote:
There is a possibility for an
On 2/12/2025 12:23 PM, Abhinav Kumar wrote:
On 2/11/2025 7:59 PM, Jessica Zhang wrote:
Disable pingpong dither in dpu_encoder_helper_phys_cleanup().
This avoids the issue where an encoder unknowingly uses dither after
reserving a pingpong block that was previously bound to an encoder that
Hi Marijn
On 2/10/2025 2:17 PM, Abhinav Kumar wrote:
On 2/10/2025 6:24 AM, Dmitry Baryshkov wrote:
On Mon, Feb 10, 2025 at 01:54:29PM +0100, Marijn Suijten wrote:
On 2025-02-10 01:11:59, Dmitry Baryshkov wrote:
On Sun, Feb 09, 2025 at 10:42:53PM +0100, Marijn Suijten wrote:
Ordering
] https://patchwork.freedesktop.org/series/144083/
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 3 +++
1 file changed, 3 insertions(+)
Was an extremely tricky issue to debug.
Glad this one is resolved,
Reviewed-by: Abhinav Kumar
On 2/11/2025 4:13 PM, Dmitry Baryshkov wrote:
On Tue, Feb 11, 2025 at 10:23:54AM +0100, Marijn Suijten wrote:
On 2025-02-10 14:14:14, Abhinav Kumar wrote:
On 2/9/2025 7:51 PM, Ethan Carter Edwards wrote:
There is a possibility for an uninitialized *ret* variable to be
returned in some
i_pll_7nm
*pll)
ndelay(250);
}
Reviewed-by: Abhinav Kumar
usly despite having a panel and
patch on the list using it without any mentioned issues.
Fixes: c110cfd1753e ("drm/msm/disp/dpu1: Add support for DSC")
Signed-off-by: Marijn Suijten
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
Good catch !
Reviewed-by: Abhinav Kumar
/hdmi_audio.c | 68 +
drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 5 ++
4 files changed, 71 insertions(+), 111 deletions(-)
Reviewed-by: Abhinav Kumar
On 2/10/2025 6:24 AM, Dmitry Baryshkov wrote:
On Mon, Feb 10, 2025 at 01:54:29PM +0100, Marijn Suijten wrote:
On 2025-02-10 01:11:59, Dmitry Baryshkov wrote:
On Sun, Feb 09, 2025 at 10:42:53PM +0100, Marijn Suijten wrote:
Ordering issues here cause an uninitialized (default STANDALONE)
usec
dpu1/dpu_plane.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
Thanks for your patch, this was addressed with
https://patchwork.freedesktop.org/patch/631567/ but since this is better
I am fine with this, will pick this one up
Reviewed-by: Abhinav Kumar
diff --git a/drivers/g
drm/msm/dsi/dsi_manager.c | 30 +++---
1 file changed, 19 insertions(+), 11 deletions(-)
Reviewed-by: Abhinav Kumar
(-)
Reviewed-by: Abhinav Kumar
On 2/7/2025 6:04 PM, Dmitry Baryshkov wrote:
On Fri, Feb 07, 2025 at 05:31:20PM -0800, Abhinav Kumar wrote:
On 2/7/2025 4:27 PM, Dmitry Baryshkov wrote:
Extend the driver to send SPD and HDMI Vendor Specific InfoFrames.
While the HDMI block has special block to send HVS InfoFrame, use
On 2/7/2025 4:27 PM, Dmitry Baryshkov wrote:
Extend the driver to send SPD and HDMI Vendor Specific InfoFrames.
While the HDMI block has special block to send HVS InfoFrame, use
GENERIC0 block instead. VENSPEC_INFO registers pack frame data in a way
that requires manual repacking in the drive
t the end of
atomic_pre_enable().
I think now this needs to be changed that, program the HDMI timings at
the beginning of atomic_pre_enable() to match the location of mode_set()
With that fixed,
Reviewed-by: Abhinav Kumar
Reviewed-by: Maxime Ripard
Signed-off-by: Dmitry Bary
On 2/7/2025 2:03 PM, Dmitry Baryshkov wrote:
On Fri, Feb 07, 2025 at 01:34:35PM -0800, Abhinav Kumar wrote:
On 2/3/2025 5:30 PM, Dmitry Baryshkov wrote:
On Mon, Feb 03, 2025 at 04:25:59PM -0800, Abhinav Kumar wrote:
On 1/24/2025 1:47 PM, Dmitry Baryshkov wrote:
Setup the HDMI
On 2/3/2025 5:30 PM, Dmitry Baryshkov wrote:
On Mon, Feb 03, 2025 at 04:25:59PM -0800, Abhinav Kumar wrote:
On 1/24/2025 1:47 PM, Dmitry Baryshkov wrote:
Setup the HDMI connector on the MSM HDMI outputs. Make use of
atomic_check hook and of the provided Infoframe infrastructure.
By
On 2/6/2025 5:19 PM, Dmitry Baryshkov wrote:
On Thu, Feb 06, 2025 at 12:41:30PM -0800, Abhinav Kumar wrote:
On 2/3/2025 4:59 PM, Dmitry Baryshkov wrote:
On Mon, Feb 03, 2025 at 11:34:00AM -0800, Abhinav Kumar wrote:
On 1/24/2025 1:47 PM, Dmitry Baryshkov wrote:
The mode_set callback
On 2/3/2025 4:59 PM, Dmitry Baryshkov wrote:
On Mon, Feb 03, 2025 at 11:34:00AM -0800, Abhinav Kumar wrote:
On 1/24/2025 1:47 PM, Dmitry Baryshkov wrote:
The mode_set callback is deprecated, it doesn't get the
drm_bridge_state, just mode-related argumetns. Also Abhinav pointed out
m/dp: change clock related programming for YUV420
over DP")
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Abhinav Kumar
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Changes in v2:
- move msm_dp_wide_bus_available() to the next line
- Link to v1:
https://lore.kernel.org/r/20250128-dp-widebus-fix-v1-1-b66d22655...@quicinc.com
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