On Fri, 14 Feb 2025 16:08:40 +0100, Krzysztof Kozlowski wrote:
> Changes in v3:
> - Define bitfields in patches 1-3, so move there parts from patch #4
> - Use FIELD_GET
> - Keep separate cached->bit_clk_div and pix_clk_div
> - I think this implements entire feedback from Dmitry
> - Link to v2:
> https://lore.kernel.org/r/20250203-drm-msm-phy-pll-cfg-reg-v2-0-862b136c5...@linaro.org
>
> [...]
Applied to msm-fixes, thanks!
[1/4] drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG0 updated from driver side
https://gitlab.freedesktop.org/drm/msm/-/commit/588257897058
[2/4] drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG1 against clock driver
https://gitlab.freedesktop.org/drm/msm/-/commit/5a97bc924ae0
[3/4] drm/msm/dsi/phy: Do not overwite PHY_CMN_CLK_CFG1 when choosing bitclk
source
https://gitlab.freedesktop.org/drm/msm/-/commit/73f69c6be2a9
Best regards,
--
Abhinav Kumar <quic_abhin...@quicinc.com>
