On Thu, 06 Feb 2025 11:46:36 -0800, Abhinav Kumar wrote:
> Widebus allows the DP controller to operate in 2 pixel per clock mode.
> The mode validation logic validates the mode->clock against the max
> DP pixel clock. However the max DP pixel clock limit assumes widebus
> is already enabled. Adjust the mode validation logic to only compare
> the adjusted pixel clock which accounts for widebus against the max DP
> pixel clock. Also fix the mode validation logic for YUV420 modes as in
> that case as well, only half the pixel clock is needed.
>
> [...]
Applied to msm-fixes, thanks!
[1/1] drm/msm/dp: account for widebus and yuv420 during mode validation
https://gitlab.freedesktop.org/drm/msm/-/commit/df9cf852ca30
Best regards,
--
Abhinav Kumar <quic_abhin...@quicinc.com>
